Department of Electrical Engineering

Faculty of Engineering & Applied Sciences

Riphah International University, Islamabad, Pakistan

Program: B.Sc. Electrical Engineering Semester: VIII

Subject EE-472-L VLSI Design Date: …………….
Experiment 2: To implement and verify the schematic and layout of CMOS Inverter
OBJECTIVES:
(i) To understand the concept and working of CMOS Inverter
(ii) To implement and simulate the schematic of CMOS Inverter in DSCH
(iii) To implement and simulate the layout of CMOS Inverter in Microwind

Performance Lab Report

Description Total Marks Description Total Marks

Marks Obtained Marks Obtained
Ability to 5 Organization/Structure 5
conduct
Experiment
Implementation 5 Data Presentation 5
&
Results
Total Marks obtained

Remarks (if any): ………………………………….

Name & Signature of faculty: …………………………………

Complementary metal–oxide–semiconductor (CMOS) is a technology for constructing integrated
circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and
other digital logic circuits. CMOS logic circuits consist of complementary arrangements of NMOS
and PMOS transistors. A CMOS circuit is reliable because its design guarantees that its output is
always shorted to either ground or VDD but not both at the same time. As a consequence, the
design also ensures that VDD is never shorted to ground through Z, which makes CMOS circuits
power-efficient. In general, a static CMOS gate has an nMOS pull-down network to connect the
output to 0 (GND) and pMOS pull-up network to connect the output to 1 (VDD), as shown in
Fig.1. The networks are arranged such that one is ON and the other OFF for any input pattern.

Fig.1. CMOS general structure

CMOS Inverter:

The inverter is a basic building block in digital electronics. An inverter or NOT gate is a logic
gate which implements logical negation. Fig.2 shows the schematic and symbol for a CMOS
inverter or NOT gate using one nMOS transistor and one pMOS transistor. When the input A is 0,
the nMOS transistor is OFF and the pMOS transistor is ON. Thus, the output Y is pulled up to 1
because it is connected to VDD but not to GND. Conversely, when A is 1, the nMOS is ON, the
pMOS is OFF, and Y is pulled down to‘0.’

Fig.2. CMOS Inverter

Experimental Procedure:

1) Open the DSCH software to draw the schematic of Inverter.

2) Select the required components as shown in Fig.3.
3) Follow the Fig.4, draw the complete schematic and run the simulation.
4) Once the schematic verification is done then next step is to design the layout for inverter
5) Open the Microwind Software and follow the Figures

Fig.3. Components in DSCH

Fig.4. Schematic diagram of Inverter

 Fig.5. Layout of Inverter

Fig.6. Simulation results of inverter layout