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R.M.D ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING

21EC503 - VLSI DESIGN (Lab Integrated)

Department :Electronics and Communication

Engineering

Batch/Year :2021-2025/III

Created by :Ms.P.Santhoshini
:Ms.S.Gayathri Priya

Date 23.09.2023

4 4
 TABLE OF CONTENTS

S.No Contents Page

Number
1 Course Objectives 7
2 Pre Requisites 8
3 Syllabus 9
4 Course outcomes 10
5 CO- PO/PSO Mapping 14
6 Unit V- IMPLEMENTATION STRATEGIES AND TESTING 15
6.1 Lecture Plan 16

6.2 Activity based learning 17

6.3 Lecture Notes 18

FPGA Building Block Architecture ACTEL FPGA 19

XILINX FPGA 25
ALTERA FPGA 29
FPGA Interconnect Routing Procedures 31
Design for Testability: Ad hoc testing 37
BIST 42
IDDQ Testing 43

Design for Manufacturability 44

Boundary Scan 46
6.4 Assignments 48
6.5 Part A Q & A 49

6.6 Part B Questions 54

6.7 Supportive online Certification courses 55
6.8 Real time Applications in day to day life and to Industry 57
6.9 Contents beyond the Syllabus 58

5
 TABLE OF
CONTENTS
S.No Contents Page
Numbe
r
7 Assessment Schedule 60

8 Prescribed Text Books & Reference Books 61

9 Mini Project suggestions 62

6
 1. COURSE OBJECTIVE

OBJECTIVES:

❖ To study the fundamentals of CMOS circuits and its characteristics.

❖ To learn the design and realization of combinational & sequential digital

circuits.
❖ To study the Architectural choices and performance tradeoffs involved in
designing and realizing the circuits in CMOS technology are discussed.
❖ To learn the different FPGA architectures and testability of VLSI circuits.
❖ To learn Hardware Descriptive Language (Verilog / VHDL) and to
familiarize fusing of logical modules on FPGAs.

7
 2. PRE REQUISITES

1.21EC303 - DIGITAL ELECTRONICS

By learning this course,the student will have a thorough knowledge
about designing combinational and sequential circuits.

2. 21EC404 – LINEAR INTEGRATED CIRCUITS

By learning this course,the student will have deep insight in fabrication
and designing ICs

8
 3. SYLLABUS

Subject Code Subject Name L T P C

21EC503 VLSI Design (Lab 3 0 2 4

Integrated)

UNIT I INTRODUCTION TO MOS TRANSISTOR 15

MOS Transistor, CMOS logic, Inverter, Layout Design Rules, Gate Layouts, Stick
Diagrams, Long-Channel I-V Characteristics, C-V Characteristics, Non ideal I-V
Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay, Linear Delay
Model, Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling.

LIST OF EXPERIMENTS
1. Design of inverter using LT-SPICE
2. Layout verification of CMOS inverter, NOR and NAND gates

UNIT II COMBINATIONAL MOS LOGIC CIRCUITS 15

Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic,
Dynamic Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail
Domino, CPL, DCVSPG, DPL, CMOS Power Dissipation. Design of combinational
circuits using Verilog.

LIST OF EXPERIMENTS
1. Design of adder and subtractor
2. Design of multiplexer and demultiplexer

UNIT III SEQUENTIAL CIRCUIT DESIGN 15

Static latches and Registers, Dynamic latches and Registers, Pulse Registers,
Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential
Circuits. Timing Issues: Timing Classification of Digital System, Synchronous Design,
Design of sequential circuits using Verilog.

LIST OF EXPERIMENTS
1.Design of Flipflops
2.Design of counter
3. Design of universal shift register
4. Design of Mealy and Moore State Machines
5. Design of random Access Memory

9
UNIT IV DESIGN OF ARITHMETIC BUILDING BLOCKS AND
SUBSYSTEM 15
Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters, ALUs, power
and speed tradeoffs, Designing Memory and Array structures: Memory Architectures
and Building Blocks, Memory Core, Memory Peripheral Circuitry.

LIST OF EXPERIMENTS
1.Design of Arithmetic Logic Unit
2.Design of Ripple Carry Adder
3.Design of Carry Select Adder
4.Design of Multiplier

UNIT V IMPLEMENTATION STRATEGIES AND TESTING 15

FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design
for Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Boundary Scan.

10
 4. COURSE OUTCOMES

After successful completion of the course, the students should be

able to

Highest
Course Outcomes Cognitive
Level
Understand the fundamental principles of VLSI circuit design in
CO1 K2
digital domain

CO2 Realize the combinational circuits using different logic families K3

Understand the memory design in sequential logic circuits K3

CO3

Analyze the architectural choice and performance tradeoff

CO4 K3
involved in data path unit design

Understand the different FPGA architectures and its testing K2

CO5

Design, Simulate to verify the functionality of logic modules

CO6 using EDA tools and familiarize fusing of logical modules on K2
FPGA

11
 Program Outcomes(PO)
Program Engineering Graduates will be able to
Outcome
Engineering Apply the knowledge of mathematics,science,engineering
fundamentals, and an engineering specialization to the solution of
PO1 Knowledge
complex engineering problems.

Identify, formulate, review research literature, and analyze complex

Problem
engineering problems reaching substantiated conclusions using first
PO2 Analysis
principles of mathematics, natural sciences, and engineering sciences

Design solutions for complex engineering problems and design

Design/
system components or processes that meet the specified needs with
Development
PO3 appropriate consideration for the public health and safety, and the
of Solutions
cultural, societal, and environmental considerations.

Conduct
Use research-based knowledge and research methods including
Investigations
design of experiments, analysis and interpretation of data, and
PO4 of Complex
synthesis of the information to provide valid conclusions.
Problems

Create, select, and apply appropriate techniques, resources, and

Modern Tool modern engineering and IT tools including prediction and modeling to
PO5 Usage complex engineering activities with an understanding of the
limitations.

Apply reasoning informed by the contextual knowledge to assess

The Engineer
societal, health, safety, legal and cultural issues and the consequent
PO6 and Society
responsibilities relevant to the professional engineering practice.

Environment Understand the impact of the professional engineering solutions in

and societal and environmental contexts, and demonstrate the knowledge
PO7
Sustainability of, and need for sustainable development.

12
 Program Outcomes(PO)
Program Engineering Graduates will be able to
Outcome
Ethics Apply ethical principles and commit to professional ethics and
PO8
responsibilities and norms of the engineering practice
Individual and Function effectively as an individual, and as a member or leader in
Team Work
PO9 diverse teams, and in multidisciplinary settings

Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able
Communication
PO10 to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive
clear instructions
Project Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a
Management
PO11 member and leader in a team, to manage projects and in
and Finance
multidisciplinary environments

Lifelong Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context
PO12 Learning
of technological change.

13
 Program Specific Outcomes(PSO)

Program
Specific Electronics and Communication Engineering Graduates will be
Outcomes able to

To analyze, design and develop solutions by applying

PSO1 foundational concepts of Electronics and Communication
Engineering.

PSO2
To apply design principles and best practices for developing
quality products for scientific and business applications

To adapt to emerging information and communication

PSO3 technologies (ICT) to innovate ideas and solutions to
existing/novel problems.

14
 5. CO- PO/PSO Mapping

Program
Course Level
Outcom of Program Outcomes Specific
es CO Outcomes
K3,K5
K K4 K4 K5 A3 A2 A3 A3 A3 A3 A2 K6 K5 K3
,K6
3
P
PO-
O- PO-2 PO-3 PO-4 PO-6 PO-7 PO-8 9 PO-10 PO-11 PO-12 PSO-1 PSO-2 PSO-3
PO-5
1

CO1 K2 2 1 1 - - - - - - - - - - 1 1

CO2 K3 1 2 - - - - - - - - - - - 2 1

CO3 K3 2 1 2 - - - - - - - - - - 1 1

CO4 K3 1 2 1 - - - - - - - - - - 1 2

CO5 K3 1 2 - - - - - - - - - - - 1 2

CO6 K2 2 1 1 - - - - - - - - - - 1 1

15
UNIT V IMPLEMENTATION STRATEGIES AND TESTING

FPGA Building Block Architectures, FPGA Interconnect Routing Procedures.

Design for Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing,
Design for Manufacturability, Boundary Scan.

16
 LECTURE PLAN
UNIT V -IMPLEMENTATION STRATEGIES AND
TESTING
S No. Proposed Ac Per Reaso
. of Date tu tai Taxonom Mode of n or
N Per al nin y level Delivery Devia
o Topic iods Da g tion
te CO

FPGA Building Block K3 Chalk -

1 CO5
1 Architectures,
Apply and talk

FPGA Building Block K3 Chalk

1 CO5 -
2 Architectures, Apply and talk

FPGA Interconnect Routing K3 Chalk

1 CO5 -
3 Procedure Apply and talk

FPGA Interconnect K3 Chalk -

4 1 CO5
Routing Procedure Apply and talk

K3 Chalk -
5
Design for Testability
1 CO6 Apply and talk

K3 Chalk -
6
Design for Testability
1 CO6 Apply and talk

Ad Hoc Testing, Scan K3 Chalk -

7 Design, 1 CO6 Apply and talk

K2
Chalk -
BIST, IDDQ Testing, 1 Under
8 CO6 and talk
stand

Design for K1 Chalk

Manufacturability, 1 and talk -
9 Boundary Scan. CO6 Remember

Total No. of Periods : 9

18
 6.2 Activity Based Learning

1. Live Assessment on testing:

2. Role Play: A group of 10 students are given the following topic and instructed
to demonstrate a role play.

―comparative performance of ACTEl,XILINX

18
 6.3 LECTURE NOTES
UNIT V IMPLEMENTATION STRATEGIES AND
TESTING

Introduction
FPGAs are the newest member of the ASIC family and are rapidly growing in
importance, replacing TTL in microelectronic systems. Even though an FPGA is a
type of gate array, we do not consider the term gate-array based ASICs to include
FPGAs.

The important characteristics of an FPGA are none of the mask layers are
customized.

A method for programming the basic logic cells and the interconnect.The core
is a regular array of programmable basic logic cells that can implement
combinational as well as sequential logic (flip-flops).A matrix of programmable
interconnect surrounds the basic logic cells. Programmable I/O cells surround the
core. Design turn around is a few hours.

FPGA stands for Field Programmable Gate Array. FPGAs are popular with
Microsystems designers because they fill the gap between TTL and PLD design
and also expensive ASICs. FPGAs are ideal for prototyping systems or for low-
volume production. Normally FPGAs comprises of :
Programmable logic blocks which implement logic
functions.
Programmable routing that connects these logic
functions.
I/O blocks that are connected to logic blocks through routing interconnect and
thatmake off-chip connections.

19
1.FPGA Building Block Architectures
ACTEL ACT FPGA:

1. ACT 1 Logic Module

The ACT 1 family uses just one type of Logic Module (LM). ACT 2 and ACT 3 FPGA
families both use two different types of LM.
Logi c modules are design based on Multiplexers.

Figure 5.1 ACT 1 Logic

Module

Logic Module is the ACTEL basic logic cell

Logic module can be implemented using pass transistors (without any
buffering)

20
 The ACT 1 family uses just one type of Logic Module (LM). ACT 2 and ACT 3
FPGA families both use two different types of LM

Figure 5.2 LM Implementation using Pass transistor

Example:
Design F=(A ·B) +(B' ·C)+D using ACTEL ACT1 logic module
using Shannon’s Expansion theorem
F=(A·B) + (B'·C) + D
Expand F wtB:r F=B·(A + D) + B'·(C + D) =B·F2 + B'·F1
F = 2:1 MUX, with B selecting between two inputs: F(A='1') and

F(A='0') F also describes the output of the ACT 1 LM

21
Now we need to split up F1 and F2
Expand F2 wrtA,and F1 wrtC: F2=A + D=(A·1) + (A'·D); F1=C +
D=(C·1) + (C'·D)
A, B, C connect to the select lines and '1' and D are the inputs of the MUXes in
the ACT 1 LM
Connections: A0=D, A1='1', B0=D, B1='1', SA=C, SB=A, S0='0', and S1=B

Figure 5.4 Implementation of F=(A·B) + (B'·C) +

D

Using multiplexer we can able to design an logic functions

22
Example:
Wheel functions to implement F=NAND(A, B)=(A·B)‘
1. First express F as the output of a 2:1 MUX: we do this by expanding F
wrtA(or
wrtB;since F is symmetric) F=A·(B') + A'·('1')
2. Assign WHEEL1 to implement INV(B), and WHEEL2 to implement '1'
3.Set the select input to the MUX connecting WHEEL1 and WHEEL2, S0+S1=A.
We can do this using S0=A, S1='1‘

Figure 5.5 2:1 MUX as Function

Wheel

23
Figure 5.6 The ACT 1 Logic Module is two function wheels, an OR gate,
and a 2:1 MUX

A 2:1 MUX is a function wheel that can generate BUF, INV, AND-11, AND1-1,
OR, AND
WHEEL(A, B) =MUX(A0, A1, SA)
MUX(A0, A1, SA)=A0·SA' +

A1·SA

The inputs (A0, A1, SA) ={A, B, '0', '1'}

Each of the inputs (A0, A1, and SA) may be A, B, '0', or '1'
The ACT 1 LM is built from two function wheels, a 2:1 MUX, and a two-input
OR gate
ACT 1 LM =MUX [WHEEL1, WHEEL2, OR(S0, S1)]

24
5.1.2 ACT 2 and ACT 3 Logic Modules
ACT 1 requires 2 LMs per flip-flop: with unknown interconnect capacitance ACT 2
and ACT 3 use two types of LMs, one includes a D flip-flop
ACT 2 C-Module is similar to the ACT 1 LM but can implement five-input logic
functions and combinational element.

ACT 2 S-Module (sequential module) contains a C-Module and a sequential

element

Figure 5.7 The ACT 2 & ACT 3 C

Module

Figure 5.8 The ACT 2 & ACT 3 S

Modules

25
 Figure 5.9 The SE element in ACT 2 & ACT 3 S Modules

2. XILINX FPGA:
Xilinx Logic Cell Array (LCA) contains Configurable Logic Block (CLB) and follows
coarse – grain architecture

Xilinx FPGA uses LUT (Look Up Table) based architecture design.

1. XILINX XC3000 CLB:

A 32-bit look-up table (LUT)
CLB propagation delay is fixed (the LUT access time) and independent of the
logic function
7 inputs to the XC3000 CLB: 5 CLB inputs (A–E), and 2 flip-flop outputs (QX
and QY)

26
2 outputs from the LUT (F and G). Since a 32-bit LUT requires only five
variables to form a unique address (32=25), there are several ways to use the
LUT:
Use 5 of the 7 possible inputs (A–E, QX, QY) with the entire 32-bit LUT (the CLB
outputs (F and G) are then identical)

Split the 32-bit LUT in half to implement 2 functions of 4 variables each; choose
4 input variables from the 7 inputs (A–E, QX, QY).You have to choose 2 of the
inputs from the 5 CLB inputs (A–E); then one function output connects to F and
the other output connects to G.

You can split the 32-bit LUT in half, using one of the 7 input variables as a select
input to a 2:1 MUX that switches between F and G (to implement some functions
of 6 and 7 variables).

Figure 5.10 XILINX XC3000

CLB

27
5.2.2 XILINX XC4000
CLB:

Figure 5.11 XILINX XC4000 CLB

The use of a LUT has advantages and

disadvantages: An inverter is as slow as a
five-input NAND

A LUT simplifies timing of synchronous logic Matched to large SRAM

programming technology

28
Xilinx uses two speed-grade systems:
Maximum guaranteed toggle rate of a CLB flip-flop (in MHz) as a suffix—higher
is faster
Example: Xilinx XC3020-125 has a toggle frequency of 125MHz
Delay time of the combinational logic in a CLB in ns—lower is

faster Example: XC4010-6 has tILO=6.0ns

Correspondence between grade and tILO is fairly accurate for the

XC2000, XC4000, and XC5200 but not for the XC3000

Figure 5.12 XILINX XC5200

CLB

29
3. ALTERA FPGA:

1. ALTERA FLEX (Flexible Logic Element

MatriX)

Figure 5.13 ALTERA FLEX Architecture

Figure 5.13 shows the basic logic cell, a Logic Element ( LE ), that Altera uses in its
FLEX 8000 series of FPGAs. Apart from the cascade logic (which is slightly simpler in
the FLEX LE) the FLEX cell resembles the XC5200 LC architecture. This is not
surprising since both architectures are based on the same SRAM programming
technology. The FLEX LE uses a four-input LUT, a flip-flop, cascade logic, and carry
logic. Eight LEs are stacked to form a Logic Array Block (the same term as used in
the MAX series, but with a different meaning).

30
5.3.2 ALTERA
MAX

Figure 5.14 ALTERA MAX Architecture

Figure 5.14 shows an Altera MAX macrocell and illustrates the architectures of
several different product families. The implementation details vary among the
families, but the basic features: wide programmable-AND array, narrow fixed-OR
array, logic expanders, and programmable inversion are very similar. Each family has
the following individual characteristics:

31
 A typical MAX 5000 chip has: 8 dedicated inputs (with both true and
complement forms); 24 inputs from the chipwide interconnect (true and
complement); and either 32 or 64 shared expander terms (single polarity). The
MAX 5000 LAB looks like a 32V16 PLD (ignoring the expander terms).

The MAX 7000 LAB has 36 inputs from the chipwide interconnect and 16
shared expander terms; the MAX 7000 LAB looks like a 36V16 PLD.

The MAX 9000 LAB has 33 inputs from the chipwide interconnect and 16 local
feedback inputs (as well as 16 shared expander terms); the MAX 9000 LAB
looks like a 49V16 PLD.

5.4 FPGA Interconnect Routing Procedures

Routing architecture comprises of programmable switches and wires. Routing
provides connection between I/O blocks and logic blocks, and between one logic
block and another logic block. The type of routing architecture decides area
consumed by routing and density of logic blocks. Routing technique used in an FPGA
largely decides the amount of area used by wire segments and programmable
switches as compared to area consumed by logic blocks. A wire segment can be
described as two end points of an interconnect with no programmable switch
between them. A sequence of one or more wire segments in an FPGA can be termed
as a track. Typically an FPGA has logic blocks, interconnects and Input/Output blocks.
Input Output blocks lie in the periphery of logic blocks and interconnect. Wire
segments connect I/O blocks to wire segments through connection blocks.
Connection blocks are connected to logic blocks, depending on the design
requirement one logic block is connected to another and so on.

32
5.4.1 Xilinx Routing Architecture
In Xilinx routing, connections are made from logic block into the channel through a
connection block. As SRAM technology is used to implement Lookup Tables,
connection sites are large. A logic block is surrounded by connection blocks on all
four sides. They connect logic block pins to wire segments. Pass transistors are
used to implement connection for output pins, while use of multiplexers for input
pins saves the number of SRAM cells required per pin. The logic block pins
connecting to connection blocks can then be connected to any number of wire
segments through switching blocks.

33
There are four types of wire segments available :
• general purpose segments, the ones that pass through switches in the
switch block.

• Direct interconnect : ones which connect logic block pins to four

surrounding connecting blocks

• long line : high fan out uniform delay connections

• clock lines : clock signal provider which runs all over the chip

5.4.2 Actel Routing Architecture

34
Actel's design has more wire segments in horizontal direction than in vertical
direction. The input pins connect to all tracks of the channel that is on the same
side as the pin. The output pins extend across two channels above the logic block
and two channels below it. Output pin can be connected to all 4 channels that it
crosses. The switch blocks are distributed throughout the horizontal channels. All
vertical tracks can make a connection with every incidental horizontal track. This
allows for the flexibility that a horizontal track can switch into a vertical track, thus
allowing for horizontal and vertical routing of same wire. The drawback is more
switches are required which add up to more capacitive load.

5.4.3 Altera Routing Architecture

Altera routing architecture has two level hierarchy. At the first level of the
hierarchy, 16 or 32 of the logic. blocks are grouped into a Logic Array Block,
structure of the LAB is very similar to a traditional PLD. the connection is formed
using EPROM- like floating-gate transistors. The channel here is set of wires that
run vertically along the length of the FPGA. Tracks are used for four types of
connections :

connections from output of all logic blocks in

LAB. connection from logic expanders.

connections from output of logic blocks in other

LABs connections to and from Input output pads

35
36
All four types of tracks connect to every logic block in the array block. The
connection block makes sure that every such track can connect to every logic block
pin. Any track can connect to into any input which makes this routing simple. The
intra-LAB routing consists of segmented channel, where segments are as long as
possible. Global interconnect structure called programmable interconnect array(PIA)
is used to make connections among LABs. Its internal structure is similar to internal
routing of a LAB. Advantage of this scheme is that regularity of physical design of
silicon allows it to be packed tightly and efficiently. The disadvantage is the large
number of switches required, which adds to capacitive load.

37
5. Design For Testability
The keys to designing circuits that are testable are controllability and observability.
Restated, controllability is the ability to set (to 1) and reset (to 0) every node internal to
the circuit. Observability is the ability to observe, either directly or indirectly, the state of
any node in the circuit. Good observability and controllability reduce the cost of
manufacturing testing because they allow high fault coverage with relatively few test
vectors. Moreover, they can be essential to silicon debug because physically probing
internal signals has become so difficult.

The 3 main approached towards Design for Testability (DFT)

are: Ad hoc testing

Scan-based

approaches Built-in

self-test (BIST)

1. Ad hoc Testing
Ad hoc test techniques are collections of ideas aimed at reducing the combinational
explosion of testing. They are summarized here for historical reasons. They are only
useful for small designs where scan, ATPG, and BIST are not available. A complete
scan-based testing methodology is recommended for all digital circuits. The following are
common techniques for ad hoc testing:

Partitioning large sequential circuits Adding test

points Adding multiplexers Providing for easy state

reset

38
A technique classified in this category is the use of the bus in a bus-oriented
system for test purposes. Each register has been made loadable from the bus
and capable of being driven onto the bus. Here, the internal logic values that
exist on a data bus are enabled onto the bus for testing purposes.

Frequently, multiplexers can be used to provide alternative signal paths during

testing.

In CMOS, transmission gate multiplexers provide low area and delay overhead.
Any design should always have a method of resetting the internal state of the chip
within a single cycle or at most a few cycles.

Apart from making testing easier, this also makes simulation faster as a few cycles
are required to initialize the chip.

In general, adhoctesting techniques represent a bag of tricks developed over the

years by designers to avoid the overhead of a systematic approach to testing.

5.5.2 Scan Design

The strategy for testing has evolved to provide observability and controllability at
each register. In designs with scan, the registers operate in one of two modes.
Therefore, scan mode gives easy observability and controllability of every register in
the system. Modern scan is based on the use of scan registers, as shown in Figure
5.15.

The scan register is a Dflip-flop preceded by a multiplexer. When the SCAN signal is
de-asserted, the register behaves as a conventional register, storing data on the
Dinput. When SCAN is asserted, the data is loaded from the SI pin, which is
connected in shift register fashion to the previous register Qoutput in the scan chain.
For the circuit to load the scan chain, SCAN is asserted and CLK is pulsed eight times
to load the first two ranks of 4-bit registers with data. SCAN is de-asserted and CLK is
asserted for one cycle to operate the circuit normally with predefined inputs. SCAN is
then reasserted and CLK asserted eight times to read the stored data out. At the
same time, the new register contents can be shifted in for the next test.
39
 Figure 5.15 Scan based Testing
Testing proceeds in this manner of serially clocking the data through the scan
register to the right point in the circuit, running a single system clock cycle and
serially clocking the data out for observation. In this scheme, every input to the
combinational block can be controlled and every output can be observed. In
addition, running a random pattern of 1s and 0s through the scan chain can test
the chain itself.

Test generation for this type of test architecture can be highly automated. ATPG
techniques can be used for the combinational blocks and, as mentioned, the scan
chain is easily tested. The prime disadvantage is the area and delay impact of the
extra multiplexer in the scan register. Designers (and managers alike) are in
widespread agreement that this cost is more than offset by the savings in debug
time and production test cost.

40
5.5.2.1 Parallel Scan
The basic idea is shown in Figure 5.16. The figure shows a two-by-two register
section. Each register receives a column (column<m>) and row (row<n>) access
signal along with a row data line (data<n>). A global write signal (write) is
connected to all registers. By asserting the row and column access signals in
conjunction with the write signal, any register can be read or written in exactly
the same method as a conventional RAM. The notional logic is shown to the right
of the four registers. Implementing the logic required at the transistor level can
reduce the overhead for each register.

Figure 5.16 Basic Structure of Parallel

Scan

41
5.5.3 Built in Self Test (BIST)
Self-test and built-in test techniques, as their names suggest, rely on augmenting
circuits to allow them to perform operations upon themselves that prove correct
operation. These techniques add area to the chip for the test logic, but reduce the
test time required and thus can lower the overall system cost.

One method of testing a module is to use a (CFSR), shown in Figure 5.18, includes
the zero state that may be required in some test situations. An n-bit LFSR is
converted to an n-bit CFSR by adding an n–1 input NOR gate connected to all but
the last bit. When in state 0…01, the next state is 0…00. When in state 0…00, the
next state is 10…0. Otherwise, the sequence is the same. Alternatively, the bottom
nbits of an n+ 1-bit LFSR can be used to cycle through the all zeros state without
the delay of the NOR gate.

Figure 5.17 Pseudo Random Sequence Generator

(PRSG)

42
 Figure 5.17 PRSG for the sequence f(x) = 1 + x + x3

A signature analyzer receives successive outputs of a combinational logic block

and produces a syndromethatis a function of these outputs. The syndrome is
reset to 0, and then XORed with the output on each cycle. The syndrome is
swizzled each cycle so that a fault in one bit is unlikely to cancel itself out. At the
end of a test sequence, the LFSR contains the syndrome that is a function of all
previous outputs. This can be compared with the correct syndrome (derived by
running a test program on the good logic) to determine whether the circuit is
good or bad. If the syndrome contains enough bits, it is improbable that a
defective circuit will produce the correct syndrome.

5.5.3.1 BIST
The combination of signature analysis and the scan technique creates a structure known as
BIST—for Built-In Self-Test or BILBO—for Built-In Logic Block Observation. The 3-bit BIST

register shown in Figure 5.18 is a scannable, resettable register that also can serve as a

pattern generator and signature analyzer. C[1:0] specifies the mode of operation. In the

reset mode (10), all the flip-flops are synchronously initialized to 0. In normal mode (11),

the flip-flops behave normally with their D input and Q output.

43
 In scan mode (00), the flip-flops are configured as a 3-bit shift register between
SIand SO.Note that there is an inversion between each stage. In test mode (01),
the register behaves as a pseudo-random sequence generator or signature
analyzer. If all the Dinputs are held low, the Qoutputs loop through a pseudo-
random bit sequence, which can serve as the input to the combinational logic. If
the Dinputs are taken from the combinational logic output, they are swizzled with
the existing state to produce the syndrome. In summary, BIST is performed by
first resetting the syndrome in the output register. Then both registers are placed

in the test mode to produce the pseudo-random inputs and calculate the
syndrome. Finally, the syndrome is shifted out through the scan chain.

Figure 5.18 BIST 3-bit

Register

5.6 IDDQ Testing

A method of testing for bridging faults is called IDDQ test (VDDsupply current
Quiescent) or supply current monitoring. This relies on the fact that when a
CMOS logic gate is not switching, it draws no DC current (except for leakage).
When a bridging fault occurs, then for some combination of input conditions, a
measurable DC IDwill flow.

44
 Testing consists of applying the normal vectors, allowing the signals to settle, and
then measuring ID.As potentially only one gate is affected, the IDDQ test has to
be very sensitive. In addition, to be effective, any circuits that draw DC power
such as pseudo-nMOS gates or analog circuits have to be disabled. Dynamic
gates can also cause problems. As current measuring is slow, the tests must be
run slower (of the order of 1 ms per vector) than normal, which increases the test
time.

IDDQ testing can be completed externally to the chip by measuring the current
drawn on the VDD line or internally using specially constructed test circuits. This
technique gives a form of indirect massive observability at little circuit overhead.
However, as subthreshold leakage current increases, IDDQ testing ceases to be
effective because variations in subthreshold leakage exceed currents caused by
the faults.

5.7 Design for Manufacturability

Circuits can be optimized for manufacturability to increase their yield. This can
be done in a number of different ways

1. Physical
At the physical level (i.e., mask level), the yield and hence manufacturability can be
improved by reducing the effect of process defects. The design rules for particular
processes will frequently have guidelines for improving yield. The following list is
representative:

Increase the spacing between wires where possible––this reduces the chance of
a defect causing a short circuit.

Increase the overlap of layers around contacts and vias––this reduces the
chance that a misalignment will cause an aberration in the contact structure.

Increase the number of vias at wire intersections beyond one if

possible––this reduces the chance of a defect causing an open circuit.

Increasingly, design tools are dealing with these kinds of optimizations automatically.

45
2. Redundancy
Redundant structures can be used to compensate for defective components on a
chip. For example, memory arrays are commonly built with extra rows. During
manufacturing test, if one of the words is found to be defective, the memory can
be reconfigured to access the spare row instead. Laser-cut wires or electrically
programmable fuses can be used for configuration. Similarly, if the memory has
many banks and one or more are found to be defective, they can be disabled,
possibly even under software control.

3. Power
Elevated power can cause failure due to excess current in wires, which in turn can
cause metal migration failures. In addition, high-power devices raise the die
temperature, degrading device performance and, over time, causing device
parameter shifts. The method of dealing with this component of manufacturability
is to minimize power through design techniques described elsewhere in this text.
In addition, a suitable package and heat sink should be chosen to remove excess
heat.

4. Process Spread
We have seen that process simulations can be carried out at different process
corners. Monte Carlo analysis can provide better modeling for process spread
and can help with centering a design within the process variations.

5. Yield Analysis
When a chip has poor yield or will be manufactured in high volume, dice that fail
manufacturing test can be taken to a laboratory for yield analysis to locate the root
cause of the failure. If particular structures are determined to have caused many of
the failures, the layout of the structures can be redesigned. For example, during
volume production ramp-up for the Pentium microprocessor, the silicide over long
thin polysilicon lines was found to crack and raise the wire resistance This in turn
led to slower-than-expected operation for the cracked chips. The layout was
modified to widen polysilicon wires or strap them with metal wherever possible,
boosting the yield at higher frequencies.

46
5.8 Boundary Scan
Many system defects occur at the board level, including open or shorted printed
circuit board traces and incomplete solder joints. At the board level,
“bed-of-nails” testers historically were used to test boards. In this type of a
tester, the board- under-test is lowered onto a set of test points (nails) that
probe points of interest on the board. These can be sensed (the observable
points) and driven (the controllable points) to test the complete board. At the
chassis level, software programs are frequently used to test a complete board
set. For instance, when a computer boots, it might run a memory test on the
installed memory to detect possible faults.

Figure 5.19 Boundary Scan

Architecture

47
The increasing complexity of boards and the movement to technologies such as surface
mount technologies (with an absence of through board vias) resulted in system designers
agreeing on a unified scan-based methodology called by scanfortesting chips at the board
(and system) level. Boundary scan was originally developed by the Joint Test Access
Group and hence is commonly referred to as JTAG. Boundary scan has become a popular
standard interface for controlling BIST features as well.

The IEEE 1149 boundary scan architecture is shown in Figure 5.19. All of the I/O pins of
each IC on the board are connected serially in a standardized scan chain accessed
through the T e s t Access P a t so that every pin can be
observed and controlled remotely through the scan chain. At the board level, Ics obeying
the standard can be connected in series to form a scan chain spanning the entire
board. Connections between ICs are tested by scanning values into the outputs of each
chip and checking that those values are received at the inputs of the chips they drive.
Moreover, chips with internal scan chains and BIST can access those features through
boundary scan to provide a unified testing framework.

48
 6.4
Assignment
Assignments ( For higher level learning and Evaluation
- Examples: Case study, Comprehensive design,
etc.,)
UNIT V
CO BT
Q.No Questions
Level Level
Compare Xilinx, Altera and Actel FPGAs based on
1. CO5 K3
the architecture and performance.

Choose an example by your own and apply D algorithm

2. CO6 K3
to sensitize the path to find the faults present in any
path.

49
 6.5 Part A Q &
A Unit-V

S.NO Question and Answers CO K

lev
el
1 CO5 K2
What is an FPGA?
A field programmable gate array (FPGA) is a programmable logic device
that supports implementation of relatively large logic circuits. FPGAs can
be used to implement a logic circuit with more than 20,000 gates whereas

a CPLD can implement circuits of upto about 20,000 equivalent gates.

2 CO5 K2
What are the characteristics of FPGA?
1. None of the mask layers are customized
2. A method of programming the basic logic cells and the interconnect.
3. The core is a array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip flops).

4. A matrix of programmable interconnect surrounds the basic logic cells.

5. Design turnaround is a few hours
3 CO5 K2
What is programmable logic array?
A programmable logic array (PLA) is a programmable device used to
implement combinational logic c i rcuits. The PLA has a set of
programmable AND planes, which link to a programmable OR planes,
which can then be conditionally complemented to produce an output. This
layout allows for a large number of logic functions to be synthesized in
the sum of products canonical forms.

4 Write the various ways of routing procedure? CO5 K2

Routing is typically a very complex combinatorial problem. To make it
manageable, the routing problem is usually solved by use of a two stage

approach of global routing followed by detailed routing.

1. Global Routing 2. Detailed Routing

50
 6.5 Part A Q &
A Unit-V

S.No Question and Answers CO K

5. CO5 K2
Name the element in a configuration logic block.
Look-Up Table, Multiplexers, Flip-Flops
6. Draw the general structure of FPGA. CO5 K2

7. What are the different commercial FPGA products? CO5 K2

1. Actel Act 1,2 and 3,MX,SX
2. Altera FLEX 6000,8000 and 10k APEX 20k
3. Atmel AT6000, AT40k
4. Lucent ORCA 1,2 and 3
5. Quick Logic pASIC 1,2 and 3
6. Vantis VFI
7. Xilinx XC3000,XC4000,XC5200,Virtex

51
 6.5 Part A Q &
A Unit-V
S.No Question and Answers CO K

8. CO6 K2
What are the categories of testing?
1. Functionality Tests
2. Manufacturing Tests
9. CO6 K2
Write notes on functionality tests?
Functionality tests verify that the chip performs its intended function.
These tests assert that all the gates in the chip, acting in concert,
achieve a desired function. These tests are usually used early in the
design cycle to verify the functionality of the circuit.

10. CO6 K2
Write notes on manufacturing tests?
Manufacturing tests verify that every gate and register in the chip
functions correctly. These tests are used after the chip is manufactured
to verify that the silicon is intact.

11. CO6 K2
What are the tests for I/O integrity?
1. I/O level test
2. Speed Test
3. IDD Test
12. CO6 K2
What is meant by observability?
The observability of a particular internal circuit node is the degree to
which one can observe that node at the outputs of an integrated
circuit
13. CO6 K2
What is meant by controllability?
The controllability of an internal circuit node within a chip is a
measure of the ease of setting the node to a 1 or 0 state.

52
 6.5 Part A Q &
A Unit-V
S.No Question and Answers CO K

14. CO6 K2
What are the self-test techniques?
a. Signature analysis and BILBO
b. Memory self-test
c. Iterative logic array testing
15. CO6 K2
What is known as BILBO?
Signature analysis can be merged with the scan technique to create a
structure known as BILBO- for Built In Logic Block Observation.

16. CO6 K2
What is known as IDDQ testing?
A popular method of testing for bridging faults is called IDDQ or
current- supply monitoring. This relies on the fact that when a
complementary CMOS logic gate is not switching, it draws no DC
current. When a bridging fault occurs, for some combination of input
conditions a measurable DC IDD will flow

17. CO6 K2
What is boundary scan?
The i n c rea s i n g c om p l ex i ty of boards and the movem en t
to technologies like multichip modules and surface-mount technologies
resulted in system designers agreeing on a unified scan- based
methodology for testing chips at the board. This is called boundary
scan

18. CO6 K2
What is the test access port (TAP)?
The Test Access Port (TAP) is a definition of the interface that needs to
be included in an IC to make it capable of being included in a
boundary-scan architecture. The port has four or five single bit
connections, as follows:

• TCK(The Test Clock Input)

• TMS(The Test Mode Select)
• TDI(The Test Data Input)
• TDO(The Test Data Output) It also has an optional signal
• TRST(The Test Reset Signal)

53
 6.5 Part A Q &
A Unit-V
S.No Question and Answers CO K

19. CO6 K2
What are the contents of the test architecture?
The test architecture consists of:
• The TAP interface pins
• A set of test-data registers
• An instruction register
• A TAP controller
20. What is the TAP controller? CO6 K2
The TAP controller is a 16-state FSM that proceeds from state to state
based on the TCK and TMS signals. It provides signals that control the

test data registers, and the instruction register. These include serial-

shift clocks and update clocks.

54
 6.6 Part B Questions
S.No Questions CO K
1 CO5 K2
Explain the Architectures of ACTEL FPGA with neat sketch
2 CO5 K2
Explain the Architectures of ALTERA FPGA with neat sketch
3 CO5 K2
Explain the Architectures of XILINX FPGA with neat sketch

4 Explain the routing procedures of various FPGAs CO5 K2

5 Explain DFT in detail. CO6 K2

6 Explain Boundary Scan Architecture in detail CO6 K2

7 CO6 K2
Explain briefly
i) Scan Design
ii) BIST
8 CO6 K2
Discuss about
i) Boundary Scan
ii) IDDQ Testing

55
 6.7 Supportive online Certification courses (NPTEL,
Swayam, Coursera, Udemy, etc.,) for EC8095 VLSI DESIGN

S.nO Name of Name of Duration Link

the the
Course online
platfor
m
1 MOS Transistor Coursera 18 hours https://www.co
u r s era.org/learn/mosf
et

2 CMOS Digital NPTEL 8 weeks https://onlinec

VLSI Design ou r s e s.n ptel .a
c . i n / n o c 2
1_ee09/preview
3 VSD Custom Layout Udemy 4.5 https://www.ude
hours m
y.com/course/vlsi-
academy-custom-
layout/
4 VSD Physical Udemy 5 hours https://www.ude
Design Flow m
y.com/course/vlsi-
academy-physical-
design-flow/

56
 Supportive Link to
Videos UNIT V

S.No Topic Link

https://youtu.be/CfmlsDW3Z4c
1 What is an FPGA
Basics of Programmable
https://youtu.be/jbOjWp4C3V4
2 Logic: FPGA
Architecture

https://youtu.be/lRf_UPXOnVU
3 Testing of VLSI Circuits

https://youtu.be/bevAfHg140o
4 Fault Modelling

57
6.8 Real time Applications in day to day life and
to Industry

1. CMOS technology is used in a wide range of analog circuits which includes data
converters, image sensors & highly incorporated transceivers for several kinds of
communication.
2. Used in designing Computer memories and CPUs.
3. Used in the implementation of Microprocessor designs.
4. Used in the implementation of Flash memory chip designing.
5. Used in desgning the application-specific integrated circuits (ASICs).
6. It is used in the Real time applications of Pendrive, External Hard Disk, Smart
Watch, Air Conditioner, Washing Machine, Microwave Oven, Refrigerator,
Calculator, Toaster ,Dish Washer, Digital Alarm Clockand Thermostat

58
 6.9 Contents beyond the
Syllabus Unit V
Introduction to GO Board
Nandland Go Board
Technical Specifications
The Nandland Go Board is designed specifically to have an excellent balance of external
peripherals, without bogging down someone who has never used an FPGA with
complicated interfaces that are more advanced. Once you exhaust all of the features of
the Go Board (which will take a very long time!) you can consider getting into a
Development Board that costs hundreds of dollars. The Go Board allows you to learn as
much as possible, as inexpensively as possible.

Lattice ICE40 HX1K FPGA

EASY USB Connection for power, communication, and programming
Dual 7-Segment LED Display

VGA Connector
Four User Settable LEDs
Four Push-Buttons
External Connector (PMOD)

25 MHz on-board clock

1 Mb Flash for booting up your FPGA

Powering, Programming, Communicating:

In order to make the board as easy to use as possible, I made the board such that it can
be powered, programmed, and communicated with over a single USB cable. For power,

once you plug your Micro USB cable in from your computer, the Go Board is powered and

ready to go! Secondly, if you've never worked with an FPGA board before, know that

many of them require expensive programming cables, just to program your FPGA.

59
This increases the cost and complexity. The Go Board is able to be programmed via an
on- board FT 2232 H. This basically moves the big programmer onto the FPGA
development board, saving you money and complexity. Finally, the FT2232H can be used
as a UART, so that your computer can talk to the FPGA. This is amazing for a new
designer! It will make it easy for you to get started!

What's Possible?
There's nearly an infinite number of projects that are possible, but to give you some
specific examples of what's possible, check out the video above. I will be creating
YouTube tutorials that show you how to program the board and to do many projects.
These will be available in both VHDL and Verilog, so you can learn whichever language
you prefer. I have created full projects for the following:

□ LED Blinker
□ 7-Segment Illumination
□ Communication to Computer (UART)
□ Conway's Game of Life
□ Temperature Sensor, via I2C Communication
□ PONG
□ Many More To Come

60
 7. ASSESSMENT
SCHEDULE

ASSESSMENT PROPOSED DATE ACTUAL DATE

Internal Assessment 1

Internal Assessment 2

Model Exam

61
 8.Prescribed Text Books & Reference
Books
TEXT BOOKS:
1. Neil H.E. Weste, David Money Harris ―CMOS VLSI Design: A Circuits and Systems

Perspectiveǁ, 4th Edition, Pearson , 2017 (UNIT I,II,V)

2. Jan M. Rabaey ,Anantha Chandrakasan, Borivoje. Nikolic, Digital Integrated

Circuits:A Design perspectiveǁ, Second Edition , Pearson ,2016.(UNIT III,IV)

REFERENCES :
1. M.J. Smith, ―Application Specific Integrated Circuitsǁ, Addisson Wesley, 1997
2.Sung-Mo kang, Yusuf leblebici, Chulwoo Kim ―CMOS Digital Integrated Circuits:

Analysis & Designǁ,4th edition McGraw Hill Education,2013

3.Wayne Wolf, ―Modern VLSI Design: System On Chipǁ, Pearson Education, 2007
4.R.Jacob Baker, Harry W.LI., David E.Boyee, ―CMOS Circuit Design, Layout and
Simulationǁ, Prentice Hall of India 2005.

62
 9 MINI
PROJECT
S.no Name of The Mini Project K
LEV
EL
1. Design of ALU. K3

2. Design of 16*4 RAM. K3

3. Design of Instruction decoder. K3

4. Integrate the blocks 1,2 and 3. K2

5. Implement the complete design in any Xilinx FPGA K2

9. Mini
Project
suggestions

63
 Thank
you

Disclaimer:

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61