BID YUT KARMAK AR

e-mail: karmakar.bidyut@gmail.com
mobile: 09632831337

CAREER OBJECTIVE: To work as a VLSI engineer and gain experience to become specialized in the field of IC design.

ACADEMICS:

 Advance Diploma in ASIC Design RV-VLSI DESIGN CENTRE,Bangalore.

 B.tech. (8.1 CGPA) form Padmanava College of Eng. Rourkela(BPUT).
 Intermediate (62%) from St. Xavier's College Ranchi(JIEC).
 Xth (79%) from St. Mary's school Barbil (ICSE board).

CORE COMPETENCIES:

 Understanding of the complete ASIC Design flow.

 Knowledge of Verilog as Hardware Description Language and HDL Simulators.
 Knowledge of Verification using Verilog.
 Knowledge of Synthesis ,Design For Test and Static Timing Analysis.
 Knowledge of Physical Design : Floor-planning, Placement and Routing.
 Basic understanding of schematic-editor, simulation tool, layout editor and L.V.S tool.
 Basic knowledge of Linux, Vi, Perl ,C and C++.

TRAININGS:

 Undergone a 25 days training at IIT KGP on NETWORK MANAGEMENT on Linux Environment.

 Undergone an industrial training at Rourkela Steel Plant(RSP-SAIL) for a month.

ACHIEVEMENTS:

 Received a NATIONAL AWARD for the BEST B.TECH PROJECT for the year 2007 by the INDIAN SOCIETY FOR
TECHNICAL EDUCATION (ISTE-NEWDELHI) . The project was based on the advanced version of my own
invention of ELECTRO- MAGNETIC INDUCTION ENGINE(E.M.I.E).(ref. The Times of India 16thOct. 2007). ref.-
www.isteonline.in
 Designed a Missile Launcher Model “KOMODO”. Published in the HINDUSTAN.

PROJECTS AT RV-VLSI

MAIN PROJECT: UART(front-end).

A ) DESIGN
• Designed the RECEIVER of the UART.

• An asynchronous FIFO was part of the receiver.

• The design was coded using verilog and simulated with hdl simulator.
• The functional bugs reported for receiver were corrected.

• Linting was done using leda.

Key challenges faced
Designing of the asynchronous FIFO :prevention of metastability and synchronization of the pointers, generation of full and
empty signal, prevention of write operation when fifo-full flag was high. Similarly the generation of empty signal and
prevention of read operation when empty signal was high.

B) VERIFICATION

• Verified the Transmitter of the UART and the synchronous FIF0.

• A verification plan was prepared to verify the transmitter and its FIFO using self-checking test-benches.

• First the transmitter FIFO was verified for functionality and then the transmitter.

• The code modules were simulated individually and then the integrated code was simulated.

• Tool used for simulation vcs from Synopsys.

• The functional bugs were reported for the transmitter.

• Linting was done using leda.

Key challenges faced
Verifying the synchronous FIFO: looking for the corner cases, wrapping of address pointers. Checking the transmitter for its
corner cases and various possible combinations of the configurations viz. five characters,even parity enabled with stick parity.

C) SYNTHESIS, DFT and STA

• The receiver of the UART was then synthesized using Design Compiler.

• To make the design testable scan chain was inserted.

• Also the Static Timing Analysis was done to verify timing.
Key challenges faced
The multiple clock issues in the receiver (SCLK & RCLK) and the generated clocks(RCLK & SAMPLE).

LESSONS LEARNT: This gave us an idea and of how the industry is like thereby boosting our confidence. Here the prior idea
of SYNTHESIZABLE-CONSTRUCTS was useful thereby helping in making the code synthesis friendly for the synthesis tool.

MAIN PROJECT : RISC PROCESSOR (back-end)

FLOOR-PLANNING,PLACEMENT AND ROUTING

• The floor-planning of ORCA was done at chip-level.

• Then placement of standard cells and macros was done followed by Clock Tree Synthesis.
• Global routing was done and upon meeting timing the Detailed routing was done.

Key challenges faced

Proper placement of macros to obtain a optimal floor-plan, avoiding congestion. The proper floor-planning can yield better
timing results as well as area and congestion can be optimized. Due to four metal layer process congestion minimization was
challenging.

MINI PROJECTS:
1. Front-end project. Design of an Elevator Controller chip . This was our first exposure to understanding of the
specification and its importance. We also learnt the importance of making the code synthesis friendly.
Designed the elevator-cotroller using verilog. Verified the Elevator Controller using test-benches.
2. Front-end project. A DIGITAL-LOCK was designed. We learnt the importance of making the code synthesis friendly.
Designed the digital-lock using verilog. Verified the Digital Lock using test-benches.
CONCEPTUAL LABS FOR A.S.I.C DESIGN FLOW.
 LOGIC DESIGN:
Implementing basic logic circuits, adders, multiplexers, designing MEALY and MOORE finite state machines and
counters. There were many labs in this Logic design module which
were helpful on Digital Logics and their implementation. This module was a foundation for the RTL module.
 Verilog RTL DESIGN:
In this we implemented basic logic circuits, adders, multiplexers, designing MEALY and MOORE finite state machines
and counters using Verilog at Gate,RTL level, and Behavioral model. Design Sequence detectors both overlapping and
non over-lapping . Avoiding Combinational feed-back and making sequential and combinational blocks separate were
some of the important concepts learnt in this module.
 RTL VERIFICATION:
Test benches (linear) were written to verify the small designs like adders, sequence detectors etc. In this module we
realized the importance of Verification and the importance of writing good testbenches.

 SIMULATING A R-C CIRCUIT:

This lab was useful in the understanding the basics of the RC circuits and the contribution of time-constant in the delay of
a circuit. How the capacitive loading increases the delay.

 SIMULATING A INVERTER :
The schematic of a layout was done using the Virtuso Composer Schematic editor, this was then simulated using Spectre
simulator.

 LAYOUT,DRC AND LVS:

This lab was used to make and understand the layout of the inverter we designed in the lab. DESIGN RULE CHECK and
LAYOUT VERSUS
SCHEMATIC was done.

 Implementation-Synthesis, DFT & STA:

In this module we synthesized i2c design. DFT was implemented using scan-chains. The ATPG tool was used for
generation of test vectors.
 Physical Design
In this module the floor-planning and place and route of i2c design was done at block-level. Learnt about the various
Design Complexities of Physical Design. Placement of macros: hard and soft blockages and their usage in floorplannig.

HOBBIES :

 PHOTOGRAPHY
 RIFLE SHOOTING
 CYCLING
 LISTENING TO WESTERN MUSIC
 WATCHING MOVIES AND DOCUMENTARIES
 EXPERIMENTING IN MY HOME LABORATORY

PERSONAL DETAILS:
Father's name : Badal Karmakar.

Date of birth : September 4th,1984.

Gender : Male.

Address : Qr. No 2RA/176,

Kalinga Nagar,
at/po- Matkembed-758036,
Orissa.
(Bidyut Karmakar)