Digital Design Lab Manual

VIDYA VIKAS INSTITUTE OF ENGINEERING & TECHNOLOGY
Department of Computer Science & Engineering
LABORATORY MANUAL
DIGITAL DESIGN AND COMPUTER

ORGANIZATION
BC S302
VISION & MISSION PEO’s
& PSO’s
VIDYA VIKAS INSTITUTE OF ENGINEERING &
TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
VISION
“To produce proficient computer professionals, having essential technical

knowledge and skills, with good work ethics”
MISSION
M1: To promote growth of an individual by imparting comprehensive knowledge

using latest tools and technologies.
M2: To inculcate professionalism, social awareness and to promote creativity,

Research aptitude by mentoring the students.
M3: To establish industry institute interaction, to enable students to cater the

ever changing industry demands and to nurture entrepreneurial qualities.
M4: To provide state-of-the-art environment and opportunities to enhance

professional skills.
PROGRAMME EDUCATIONAL OUTCOMES
PEO 1: To provide Graduates of computer science & engineering course with

a solid foundation in the principles and practices of computer science and
engineering enabling them to have successful professional career.
PEO 2: To encourage Graduates of computer science & engineering course to

pursue higher education.
PEO 3: To prepare Graduates of computer science & engineering course to

adapt to technological advancements by engaging in lifelong learning.
PROGRAMME SPECIFIC OUTCOMES
PSO 1: Use the knowledge of algorithms and programming skills to efficiently build,
testand maintain software systems.
PSO 2: Design and build systems, catering the needs of industry and society.
DO’s and DON’Ts
DO’s and DON’Ts
Do’s
 Students should be in proper uniform and dress code with identity cards in the laboratory.
 Students should bring their observation, manual and record compulsorily.
 Students should maintain discipline in the laboratory.
 Students are required to handle all the equipment’s/Computers properly.
 Students are required to follow the safety precautions.
 Enter the lab in time as per the given time table.
 Enter time-in and time-out in log book.
 Comply with the instructions given by faculty and instructor.
 Arrange the chairs/ equipment’s before leaving the lab.
 Take signature in the observation, before leaving the lab.
Don’ts
 Mobile phones are strictly banned.
 Ragging is punishable.
 Do not turn on the power supply before verification of the circuits by the Batch in Charge.
 Do not operate any peripherals or accessories without supervision.
 Avoid stepping on computer cables and electrical wires.
 Do not walk around in the lab unnecessarily.
 Do not go out of the lab without permission.
COURSE OBJECTIVES
&
COURSE OUTCOMES
COURSE OBJECTIVES & COURSE OUTCOMES
COURSE OBJECTIVES:
This course will enable students to,

a. To demonstrate the functionalities of binary logic system
b. To explain the working of combinational and sequential logic system To realize the basic
structure of computer system
c. To illustrate the working of I/O operations and processing unit
COURSE OUTCOME:
The students should be able to:
CO1: Apply the K–Map techniques to simplify various Boolean expressions.

CO2: Design different types of combinational and sequential circuits along with
Verilog programs.
CO3: Describe the fundamentals of machine instructions, addressing modes and
Processor performance.
CO4: Explain the approaches involved in achieving communication between processor
and I/O devices.
CO5:Analyze internal Organization of Memory and Impact of cache/Pipelining on
Processor Performance.
COURSE SYLLABUS
CONTENT
PROGRAMS
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MKV-TEMPLATE for IPCC (26.04.2022) Annexure-III
Digital Design and Computer Organization Semester 3

Course Code BCS302 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:2:0 SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 20 Hours of Practicals Total Marks 100
Credits 04 Exam Hours 3
Examination nature (SEE) Theory
Course objectives:
● To demonstrate the functionalities of binary logic system
● To explain the working of combinational and sequential logic system
● To realize the basic structure of computer system
● To illustrate the working of I/O operations and processing unit
Teaching-Learning Process (General Instructions)

These are sample Strategies; that teachers can use to accelerate the attainment of the various course outcomes.
1. Chalk and Talk
2. Live Demo with experiments
3. Power point presentation
MODULE-1 8 Hr
Introduction to Digital Design: Binary Logic, Basic Theorems And Properties Of Boolean Algebra,
Boolean Functions, Digital Logic Gates, Introduction, The Map Method, Four-Variable Map, Don’t-Care
Conditions, NAND and NOR Implementation, Other Hardware Description Language – Verilog Model of a
simple circuit.
Text book 1: 1.9, 2.4, 2.5, 2.8, 3.1, 3.2, 3.3, 3.5, 3.6, 3.9
MODULE-2 8 Hr
Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary Adder- Subtractor,
Decoders, Encoders, Multiplexers. HDL Models of Combinational Circuits – Adder, Multiplexer, Encoder.
Sequential Logic: Introduction, Sequential Circuits, Storage Elements: Latches, Flip-Flops.
Text book 1: 4.1, 4.2, 4.4, 4.5, 4.9, 4.10, 4.11, 4.12, 5.1, 5.2, 5.3, 5.4.
MODULE-3 8 Hr
Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus structure, Performance –
Processor Clock, Basic Performance Equation, Clock Rate, Performance Measurement.Machine
Instructions and Programs: Memory Location and Addresses, Memory Operations, Instruction and
Instruction sequencing, Addressing Modes.
Text book 2: 1.2, 1.3, 1.4, 1.6, 2.2, 2.3, 2.4, 2.5
MODULE-4 8 Hr
Input/output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and Disabling
Interrupts, Handling Multiple Devices, Direct Memory Access: Bus Arbitration, Speed, size and Cost of
memory systems. Cache Memories – Mapping Functions.
Text book 2: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4, 5.4, 5.5.1
MODULE-5 8 Hr
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Basic Processing Unit: Some Fundamental Concepts: Register Transfers, Performing ALU operations,
fetching a word from Memory, Storing a word in memory. Execution of a Complete Instruction. Pipelining:
Basic concepts, Role of Cache memory, Pipeline Performance.
Text book 2: 7.1, 7.2, 8.1
PRACTICAL COMPONENT OF IPCC
Sl.N Experiments
O Simulation packages preferred: Multisim, Modelsim, PSpice or any other relevant
1 Given a 4-variable logic expression, simplify it using appropriate technique and simulate the same
using basic gates.
2 Design a 4 bit full adder and subtractor and simulate the same using basic gates.
3 Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioural model.
4 Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and Full
Subtractor.
5 Design Verilog HDL to implement Decimal adder.
6 Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.
7 Design Verilog program to implement types of De-Multiplexer.
8 Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:
CO1: Apply the K–Map techniques to simplify various Boolean expressions.
CO2: Design different types of combinational and sequential circuits along with Verilog programs.
CO3: Describe the fundamentals of machine instructions, addressing modes and Processor performance.
CO4: Explain the approaches involved in achieving communication between processor and I/O devices.
CO5:Analyze internal Organization of Memory and Impact of cache/Pipelining on Processor Performance.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50) and for the
SEE minimum passing mark is 35% of the maximum marks (18 out of 50 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/
course if the student secures a minimum of 40% (40 marks out of 100) in the sum total of the CIE
(Continuous Internal Evaluation) and SEE (Semester End Examination) taken together.
CIE for the theory component of the IPCC (maximum marks 50)
● IPCC means practical portion integrated with the theory of the course.
● CIE marks for the theory component are 25 marks and that for the practical component is 25
marks.
● 25 marks for the theory component are split into 15 marks for two Internal Assessment Tests (Two
Tests, each of 15 Marks with 01-hour duration, are to be conducted) and 10 marks for other
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assessment methods mentioned in 22OB4.2. The first test at the end of 40-50% coverage of the
syllabus and the second test after covering 85-90% of the syllabus.
● Scaled-down marks of the sum of two tests and other assessment methods will be CIE marks for the
theory component of IPCC (that is for 25 marks).
● The student has to secure 40% of 25 marks to qualify in the CIE of the theory component of IPCC.
CIE for the practical component of the IPCC
● 15 marks for the conduction of the experiment and preparation of laboratory record, and 10 marks
for the test to be conducted after the completion of all the laboratory sessions.
● On completion of every experiment/program in the laboratory, the students shall be evaluated
including viva-voce and marks shall be awarded on the same day.
● The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks. Marks of
all experiments’ write-ups are added and scaled down to 15 marks.
● The laboratory test (duration 02/03 hours) after completion of all the experiments shall be
conducted for 50 marks and scaled down to 10 marks.
● Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 25 marks.
● The student has to secure 40% of 25 marks to qualify in the CIE of the practical component of the
IPCC.
SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module.
4. Marks scored by the student shall be proportionally scaled down to 50 Marks
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will
have a CIE component only. Questions mentioned in the SEE paper may include questions from
the practical component.
Suggested Learning Resources:
Books
1. M. Morris Mano & Michael D. Ciletti, Digital Design With an Introduction to Verilog Design, 5e,
Pearson Education.
2. Carl Hamacher, ZvonkoVranesic, SafwatZaky, Computer Organization, 5th Edition, Tata McGraw
Hill.
Web links and Video Lectures (e-Resources):

https://cse11-iiith.vlabs.ac.in/
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Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
Assign the group task to Design the various types of counters and display the output accordingly
Assessment Methods
● Lab Assessment (25 Marks)
● GATE Based Aptitude Test
4
Contents
Sl. No. Name of the Experiments Page No

1 Given a 4-variable logic expression, simplify it using appropriate technique 1
and simulate the same using basic gates.
2 Design a 4 bit full adder and subtractor and simulate the same using basic 2
gates.
3 Design Verilog HDL to implement simple circuits using structural, Data 3
flow and Behavioural model.
4 Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full 7
Adder, Half and Full Subtractor.
5 Design Verilog HDL to implement Decimal adder. 11
6 Design Verilog program to implement Different types of multiplexer like 13
2:1, 4:1 and 8:1.
7 Design Verilog program to implement types of De-Multiplexer. 17
8 Design Verilog program for implementing various types of Flip-Flops such 20
as SR, JK and D.
3rd SEM, B.E [CSE] : Digital Design And Computer Organization[BCS302]
EXPERIMENT 1
Given a 4-variable logic expression, simplify it using appropriate technique and simulate the
same using basic gates.
E=A’B’C’D’+A’B’C’D+A’B’CD+A’BC’D+A’BCD+AB’C’D’+AB’C’D+AB’CD+ABC’D+AB
CD
K-Map Simplification
AB/CD C’D’ C’D CD CD’

A’B’ 1 1 1 0
A’B 0 1 1 0
AB 0 1 1 0
A’B’ 1 1 1 0
E=D+B’C’
Verilog Code for above Expression:

module expression(B,C,D,E);
input B,C,D;
output E;
wire W1,W2,W3;
not(W1,B);
not(W2,C);
and(W3,W1,W2);
or(E,D,W3);
endmodule
module expression_tb();
reg B,C,D;
wire E;
expression EX(.B(B),.C(C),.D(D),.E(E));
initial
begin
B=0; C=0; D=0; #10;
B=0; C=0; D=1; #10;
B=0; C=1; D=0; #10;
B=0; C=1; D=1; #10;
B=1; C=0; D=0; #10;
B=1; C=0; D=1; #10;
B=1; C=1; D=0; #10;
B=1; C=1; D=1; #10;
end
endmodule
Dept. of CSE, VVIET, Mysuru 1

Output

EXPERIMENT 2
Design a 4 bit full adder and subtractor and simulate the same using basic gates.
//4-bit fulladder
module fulladder_4bit(A,B,Cin,Sum,Cout);
input [3:0]A,B;
input Cin;
output [3:0]Sum;
output Cout;
assign {Cout,Sum}=A+B+Cin;
endmodule
module TB_FA();
reg [3:0]a,b;
reg cin;
wire [3:0]sum;
wire cout;
fulladder_4bit fl(.A(a),.B(b),.Cin(cin),.Sum(sum),.Cout(cout));
initial
begin
a=4'b0000;b=4'b0001;cin=1'b0;#10;
a=4'b0011;b=4'b0011;cin=1'b0;#10;
a=4'b1111;b=4'b1011;cin=1'b0;#10;
a=4'b0011;b=4'b0001;cin=1'b0;#10;
end
endmodule
Output

//4-bit fullsubtractor
module fullsub_4bit(A,B,Bin,Diff,Bout);
input [3:0]A,B;
input Bin;
output [3:0]Diff;
output Bout;
assign {Bout,Diff}=A-B-Bin;
endmodule
module TB_FS();
reg [3:0]a,b;
reg bin;
wire [3:0]diff;
wire bout;
fullsub_4bit fs(.A(a),.B(b),.Bin(bin),.Diff(diff),.Bout(bout));
initial
begin
a=4'b0000;b=4'b0001;bin=1'b0;#10;
a=4'b0011;b=4'b0011;bin=1'b0;#10;
a=4'b1111;b=4'b1011;bin=1'b0;#10;
a=4'b0011;b=4'b0001;bin=1'b0;#10;
end
endmodule
Output

EXPERIMENT 3
Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.
E=A+BC+B’D
Structural Modelling
module structural(A,B,C,D,E);
input A,B,C,D;
output E;
wire W1,W2,W3,W4;
and(W1,D,C);
not(W2,B);
and(W3,W2,D);
or(W4,W1,W3);
or(E,A,W4);
endmodule
module structural_tb();
reg A,B,C,D;
wire E;
structural EX(.A(A),.B(B),.C(C),.D(D),.E(E));
initial
begin
A=0; B=0; C=0; D=0; #10;
A=0; B=0; C=0; D=1; #10;
A=0; B=0; C=1; D=0; #10;
A=0; B=0; C=1; D=1; #10;
A=0; B=1; C=0; D=0; #10;
A=0; B=1; C=0; D=1; #10;
A=0; B=1; C=1; D=0; #10;
A=0; B=1; C=1; D=1; #10;
A=1; B=0; C=0; D=0; #10;
A=1; B=0; C=0; D=1; #10;
A=1; B=0; C=1; D=0; #10;
A=1; B=0; C=1; D=1; #10;
A=1; B=1; C=0; D=0; #10;

A=1; B=1; C=0; D=1; #10;

A=1; B=1; C=1; D=0; #10;
A=1; B=1; C=1; D=1; #10;
end
endmodule
Output:
DataFlow Modelling
module dataflow(A,B,C,D,E);
input A,B,C,D;
output E;
assign E = A|(D&C)|(~B&D);
endmodule
module dataflow_tb();
reg A,B,C,D;
wire E;
dataflow EX(.A(A),.B(B),.C(C),.D(D),.E(E));
initial
begin
A=0; B=0; C=0; D=0; #10;
A=0; B=0; C=0; D=1; #10;
A=0; B=0; C=1; D=0; #10;
A=0; B=0; C=1; D=1; #10;
A=0; B=1; C=0; D=0; #10;
A=0; B=1; C=0; D=1; #10;
A=0; B=1; C=1; D=0; #10;
A=0; B=1; C=1; D=1; #10;
A=1; B=0; C=0; D=0; #10;
A=1; B=0; C=0; D=1; #10;
A=1; B=0; C=1; D=0; #10;
A=1; B=0; C=1; D=1; #10;

A=1; B=1; C=0; D=0; #10;

A=1; B=1; C=0; D=1; #10;
A=1; B=1; C=1; D=0; #10;
A=1; B=1; C=1; D=1; #10;
end
endmodule
Output

EXPERIMENT 4
Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and
Full Subtractor.
//Halfadder
module halfadder(A,B,sum,carry);
input A,B;
output sum, carry;
assign sum = A^B;
assign carry = A&B;
endmodule
module halfadder_tb();
reg A,B;
wire sum, carry;
halfadder HA(.A(A),.B(B),.sum(sum),.carry(carry));
initial
begin
A=0; B=0; #10;
A=0; B=1; #10;
A=1; B=0; #10;
A=1; B=1; #10;
end
endmodule
Output

//Fulladder
module fulladder(A,B,C,sum,cout);
input A,B,C;
output sum, cout;
assign sum = A^B^C;
assign cout = (A&B)|(B&C)|(C&A);
endmodule
module fulladder_tb();
reg A,B,C;
wire sum, cout;
fulladder FA(.A(A),.B(B),.C(C),.sum(sum),.cout(cout));
initial
begin
A=0; B=0; C=0; #10;
A=0; B=0; C=1; #10;
A=0; B=1; C=0; #10;
A=0; B=1; C=1; #10;
A=1; B=0; C=0; #10;
A=1; B=0; C=1; #10;
A=1; B=1; C=0; #10;
A=1; B=1; C=1; #10;
end
endmodule
Output

//Halfsubtractor
module halfsubtractor(A,B,diff,borrow);
input A,B;
output diff, borrow;
assign diff = A^B;
assign borrow = ~A&B;
endmodule
module halfsubtractor_tb();
reg A,B;
wire diff, borrow;
halfsubtractor HS(.A(A),.B(B),.diff(diff),.borrow(borrow));
initial
begin
A=0; B=0; #10;
A=0; B=1; #10;
A=1; B=0; #10;
A=1; B=1; #10;
end
endmodule
Output

//Fullsubtractor
module fullsubtractor(A,B,C,diff,bout);
input A,B,C;
output diff, bout;
assign diff = A^B^C;
assign bout = (~A&B)|(B&C)|(~A&C);
endmodule
module fullsubtractor_tb();
reg A,B,C;
wire diff, bout;
fullsubtractor FS(.A(A),.B(B),.C(C),.diff(diff),.bout(bout));
initial
begin
A=0; B=0; C=0; #10;
A=0; B=0; C=1; #10;
A=0; B=1; C=0; #10;
A=0; B=1; C=1; #10;
A=1; B=0; C=0; #10;
A=1; B=0; C=1; #10;
A=1; B=1; C=0; #10;
A=1; B=1; C=1; #10;
end
endmodule
Output:

EXPERIMENT 5
Design Verilog HDL to implement Decimal adder.
module decimal_adder(a,b,cin,sum,carry);
input [3:0]a,b;
output [3:0]sum;
input cin;
output carry;
reg[4:0]sum_temp;
reg[4:0]sum;
reg carry;
always @(a,b,cin)
begin
sum_temp=a+b+cin;
if(sum_temp>9)
begin
sum_temp=sum_temp+6;
carry=1;
sum=sum_temp[3:0];
end
else
begin
carry=0;
sum=sum_temp[3:0];
end
end
endmodule
module decimal_adder_TB();
reg [3:0]a;
reg [3:0]b;
reg cin;
wire [3:0]sum;
wire carry;
decimal_adder DA(.a(a),.b(b),.cin(cin),.sum(sum),.carry(carry));
initial
begin
a=0; b=0; cin=0; #10;
a=6; b=9; cin=0; #10;
a=3; b=3; cin=0; #10;
a=4; b=5; cin=0; #10;
a=8; b=2; cin=0; #10;
a=9; b=9; cin=0; #10;
end
endmodule

Output

EXPERIMENT 6
Design Verilog program to implement Different types of multiplexer like 2:1, 4:1 and 8:1.
//2:1 muultiplexer
module Mux2to1(I0,I1,S,Out);
input I0,I1,S;
output reg Out;
always @(*)begin
case(S)
1'b0:Out=I0;
1'b1:Out=I1;
endcase
end
endmodule
module Mux2to1_TB();
reg I0,I1,S;
wire Out;
Mux2to1 MX(.I0(I0),.I1(I1),.S(S),.Out(Out));
initial begin
S=0; I0=1; I1=0; #10;
S=1; I0=0; I1=1; #10;
end
endmodule
Output

//4:1 muultiplexer
module Mux4to1(d0,d1,d2,d3,Sel,Out);
output reg Out;
input [1:0]Sel;
input d0,d1,d2,d3;
always @(Sel)
begin
case(Sel)
2'b00:Out=d0;
2'b01:Out=d1;
2'b10:Out=d2;
2'b11:Out=d3;
endcase
end
endmodule
reg [1:0]Sel;
reg d0;
reg d1;
reg d2;
reg d3;
wire Out;
Mux4to1 MUX(.d0(d0),.d1(d1),.d2(d2),.d3(d3),.Sel(Sel),.Out(Out));
initial begin
d0=1; d1=0; d2=0; d3=0; Sel=0; #10;
d0=0; d1=1; d2=0; d3=0; Sel=1; #10;
d0=0; d1=0; d2=1; d3=0; Sel=2; #10;
d0=0; d1=0; d2=0; d3=1; Sel=3; #10;
end
endmodule
Output

//8:1 Multiplexer
module Mux8to1(d0,d1,d2,d3,d4,d5,d6,d7,Sel,Out);
output reg Out;
input [2:0]Sel;
input d0,d1,d2,d3,d4,d5,d6,d7;
always @(Sel)
begin
case(Sel)
3'b000:Out=d0;
3'b001:Out=d1;
3'b010:Out=d2;
3'b011:Out=d3;
3'b100:Out=d4;
3'b101:Out=d5;
3'b110:Out=d6;
3'b111:Out=d7;
endcase
end
endmodule
reg [2:0]Sel;
reg d0;
reg d1;
reg d2;
reg d3;
reg d4;
reg d5;
reg d6;
reg d7;
wire Out;
Mux8to1
MUX(.d0(d0),.d1(d1),.d2(d2),.d3(d3),.d4(d4),.d5(d5),.d6(d6),.d7(d7),.Sel(Sel),.Out(Out));
initial begin
d0=1; d1=0; d2=0; d3=0; d4=0; d5=0; d6=0; d7=0; Sel=0; #10;
d0=0; d1=1; d2=0; d3=0; d4=0; d5=0; d6=0; d7=0; Sel=1; #10;
d0=0; d1=0; d2=1; d3=0; d4=0; d5=0; d6=0; d7=0; Sel=2; #10;
d0=0; d1=0; d2=0; d3=1; d4=0; d5=0; d6=0; d7=0; Sel=3; #10;
d0=0; d1=0; d2=0; d3=0; d4=1; d5=0; d6=0; d7=0; Sel=4; #10;
d0=0; d1=0; d2=0; d3=0; d4=0; d5=1; d6=0; d7=0; Sel=5; #10;
d0=0; d1=0; d2=0; d3=0; d4=0; d5=0; d6=1; d7=0; Sel=6; #10;
d0=0; d1=0; d2=0; d3=0; d4=0; d5=0; d6=0; d7=1; Sel=7; #10;
end
endmodule

Output

EXPERIMENT 7
Design Verilog program to implement types of De-Multiplexer.
//2:1 Demultiplexer
module Demux2to1(I,S,Y0,Y1);
input I,S;
output Y0,Y1;
assign {Y0,Y1}=S?{1'b0,I}:{I,1'b0};
endmodule
module Demux2to1_TB();
reg I,S;
wire Y0,Y1;
Demux2to1 DEMUX(I,S,Y0,Y1);
initial begin
S=0;I=1;#10;
S=1;I=1;#10;
end
endmodule
Output

//4:1 Demultiplexer
module Demux4to1(I,S0,S1,Y0,Y1,Y2,Y3);
input I,S0,S1;
output Y0,Y1,Y2,Y3;
assign Y0=(~S0)&(~S1)&I;
assign Y1=(~S0)&(S1)&I;
assign Y2=(S0)&(~S1)&I;
assign Y3=(S0)&(S1)&I;
endmodule
reg I,S0,S1;
wire Y0,Y1,Y2,Y3;
Demux4to1 DEMUX(I,S0,S1,Y0,Y1,Y2,Y3);
initial begin
S0=0;S1=0;I=1;#10;
S0=0;S1=1;I=1;#10;
S0=1;S1=0;I=1;#10;
S0=1;S1=1;I=1;#10;
end
endmodule
Output

//8:1 Demultiplexer
module Demux8to1(I,S0,S1,S2,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7);
input I,S0,S1,S2;
output Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
assign Y0=(~S0)&(~S1)&(~S2)&I;
assign Y1=(~S0)&(~S1)&(S2)&I;
assign Y2=(~S0)&(S1)&(~S2)&I;
assign Y3=(~S0)&(S1)&(S2)&I;
assign Y4=(S0)&(~S1)&(~S2)&I;
assign Y5=(S0)&(~S1)&(S2)&I;
assign Y6=(S0)&(S1)&(~S2)&I;
assign Y7=(S0)&(S1)&(S2)&I;
endmodule
reg I,S0,S1,S2;
wire Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
Demux8to1 DEMUX(I,S0,S1,S2,Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7);
initial begin
S0=0;S1=0;S2=0;I=1;#10;
S0=0;S1=0;S2=1;I=1;#10;
S0=0;S1=1;S2=0;I=1;#10;
S0=0;S1=1;S2=1;I=1;#10;
S0=1;S1=0;S2=0;I=1;#10;
S0=1;S1=0;S2=1;I=1;#10;
S0=1;S1=1;S2=0;I=1;#10;
S0=1;S1=1;S2=1;I=1;#10;
end
endmodule
Output

EXPERIMENT 8
Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.
//SR FLIP FLOP
module SR_FF(S,R,CLK,Q,Qbar);
input S,R,CLK;
output Q,Qbar;
wire s1,r1;
nand n1(s1,S,CLK);
nand n2(r1,R,CLK);
nand n3(Q,s1,Qbar);
nand n4(Qbar,r1,Q);
endmodule
module SR_FF_TB();
reg S,R,CLK;
wire Q;
wire Qbar;
SR_FF SR(S,R,CLK,Q,Qbar);
initial begin
$monitor("S=%b,R=%b,CLK=%b,Q=%b,Qbar=%b",S,R,CLK,Q,Qbar);
S=1;R=0;CLK=1;
#10;
S=0;R=0;CLK=1;
#10;
S=0;R=1;CLK=1;
#10;
S=1;R=1;CLK=1;
end
endmodule

Output
S=1,R=0,CLK=1,Q=1,Qbar=0
# S=0,R=0,CLK=1,Q=1,Qbar=0
# S=0,R=1,CLK=1,Q=0,Qbar=1
# S=1,R=1,CLK=1,Q=1,Qbar=1
//JK FLIP FLOP
module JK_FF(J,K,Q,CLK);
input J,K,CLK;
output reg Q;
always @(posedge CLK)
case({J,K})
2'b00:Q<=Q;
2'b01:Q<=0;
2'b10:Q<=1;
2'b11:Q<=~Q;
endcase
endmodule
module JK_FF_TB();
reg J,K,CLK;
wire Q;
JK_FF JK(J,K,Q,CLK);
initial begin
CLK=0;
forever #10 CLK=~CLK;
end
initial begin

J=0;K=0;
#10;
J=0;K=1;
#10;
J=1;K=0;
#10;
J=1;K=1;
#10;
end
endmodule
Output
D Flip Flop
module D_FF(Q,D,CLK,RST);
input D,CLK,RST;
output reg Q;
always @(posedge CLK or posedge RST)
begin
if(RST==1)
Q<=0;
else
Q<=D;
end
endmodule
module D_FF_TB();
reg D,CLK,RST;
wire Q;
D_FF DFF(Q,D,CLK,RST);

initial begin
CLK=0;
forever
#10
CLK=~CLK;
end
initial begin
RST=1;
#10;
RST=0;
#10;
D=0;
#10;
D=1;
#10;
end
endmodule
Output

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VIDYA VIKAS INSTITUTE OF ENGINEERING & TECHNOLOGY

Department of Computer Science & Engineering

DIGITAL DESIGN AND COMPUTER

“To produce proficient computer professionals, having essential technical

M1: To promote growth of an individual by imparting comprehensive knowledge

M2: To inculcate professionalism, social awareness and to promote creativity,

M3: To establish industry institute interaction, to enable students to cater the

M4: To provide state-of-the-art environment and opportunities to enhance

PROGRAMME EDUCATIONAL OUTCOMES

PEO 1: To provide Graduates of computer science & engineering course with

PEO 2: To encourage Graduates of computer science & engineering course to

PEO 3: To prepare Graduates of computer science & engineering course to

PROGRAMME SPECIFIC OUTCOMES

This course will enable students to,

CO1: Apply the K–Map techniques to simplify various Boolean expressions.

Digital Design and Computer Organization Semester 3

Teaching-Learning Process (General Instructions)

Text book 2: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4, 5.4, 5.5.1

Text book 2: 7.1, 7.2, 8.1

PRACTICAL COMPONENT OF IPCC

5 Design Verilog HDL to implement Decimal adder.

7 Design Verilog program to implement types of De-Multiplexer.

Course outcomes (Course Skill Set):

Web links and Video Lectures (e-Resources):

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Sl. No. Name of the Experiments Page No

AB/CD C’D’ C’D CD CD’

Verilog Code for above Expression:

Dept. of CSE, VVIET, Mysuru 1

Dept. of CSE, VVIET, Mysuru 2

Dept. of CSE, VVIET, Mysuru 3

Dept. of CSE, VVIET, Mysuru 4

Dept. of CSE, VVIET, Mysuru 5

A=1; B=1; C=0; D=1; #10;

Dept. of CSE, VVIET, Mysuru 6

A=1; B=1; C=0; D=0; #10;

Dept. of CSE, VVIET, Mysuru 7

Dept. of CSE, VVIET, Mysuru 8

Dept. of CSE, VVIET, Mysuru 9

Dept. of CSE, VVIET, Mysuru 10

Dept. of CSE, VVIET, Mysuru 11

Design Verilog HDL to implement Decimal adder.

Dept. of CSE, VVIET, Mysuru 12

Dept. of CSE, VVIET, Mysuru 13

Dept. of CSE, VVIET, Mysuru 14

Dept. of CSE, VVIET, Mysuru 15

Dept. of CSE, VVIET, Mysuru 16

Dept. of CSE, VVIET, Mysuru 17

Design Verilog program to implement types of De-Multiplexer.

Dept. of CSE, VVIET, Mysuru 18

Dept. of CSE, VVIET, Mysuru 19

Dept. of CSE, VVIET, Mysuru 20

//SR FLIP FLOP

Dept. of CSE, VVIET, Mysuru 21

//JK FLIP FLOP

Dept. of CSE, VVIET, Mysuru 22

Dept. of CSE, VVIET, Mysuru 23

Dept. of CSE, VVIET, Mysuru 24

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