Dpco

ARUNAI ENGINEERING COLLEGE
Thiruvannamalai
B.E
DEPARTMENT OF COMPUTER SCIENCE AND

ENGINEERING (CYBER SECURITY)
2023 - 2024
THIRD
SEMESTER
CS3351-DIGITAL PRINCIPLES AND

COMPUTER ORGANIZATON LABORATORY
ARUNAI ENGINEERING COLLEGE
Thiruvannamalai
B.E
DEPARTMENT OF COMPUTER SCIENCE AND

ENGINEERING (CYBER SECURITY)
CERTIFICATE
Certified that this is a bonafide record of work done by
Name :
University Reg.No :
Semester :
Branch :
Year :
Staff-in-Charge HOD/CSE-CS
Submitted for the Practical Examination held on
Internal Examiner External Examiner

lOMoARcPSD|246 973 82
I. PROGRAM EDUCATIONAL OBJECTIVES (PEOs)
Graduates can
1. Utilize their proficiencies in the fundamental knowledge of basic sciences, mathematics,
Artificial Intelligence, data science and statistics to build systems that require management
and analysis of large volumes of data.
2. Advance their technical skills to pursue pioneering research in the field of AI and Data
Science and create disruptive and sustainable solutions for the welfare of ecosystems.
3. Think logically, pursue lifelong learning and collaborate with an ethical attitude in a
multidisciplinary team.
4. Design and model AI based solutions to critical problem domains in the real world.
5. Exhibit innovative thoughts and creative ideas for effective contribution towards economy
building.
II. PROGRAM OUTCOMES (POs)
PO# Graduate Attribute

1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineeringproblems.
2 Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principlesof
mathematics, natural sciences, and engineering sciences.
3 Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4 Conduct investigations of complex problems: Use research-based knowledge
and research methods including design of experiments, analysis and interpretation of data,and
synthesis of the information to provide valid conclusions.
5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex engineering
activities with an understanding of the limitations.
6 The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
For sustainable development.
8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
Norms of the engineering practice.
9 Individual and team work: Function effectively as an individual, and as a member or
Leader in diverse teams, and in multidisciplinary settings.
10 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and
Receive clear instructions.
11 Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12 Life-long learning: Recognize the need for, and have the preparation and ability to
Engage in independent and life-long learning in the broadest context of technologicalchange.
III. PROGRAM SPECIFIC OUTCOMES (PSOs)
Graduates should be able to:
1. Evolve AI based efficient domain specific processes for effective decision making in several
domains such as business and governance domains.
2. arrive at actionable Foresight, Insight, hindsight from data for solving business and
engineering problems
3. create, select and apply the theoretical knowledge of AI and Data Analytics along with
practical industrial tools and techniques to manage and solve wicked societal problems
4. Develop data analytics and data visualization skills, skills pertaining to knowledge
acquisition, knowledge representation and knowledge engineering, and hence be capableof
coordinating complex projects.
5. Able to carry out fundamental research to cater the critical needs of the society through
cutting edge technologies of AI.
CS3351 DIGITAL PRINCIPLES AND COMPUTER L T P C

ORGANIZATION
3 0 2 4
OBJECTIVES:
 To analyze and design combinational circuits

 To analyze and design sequential circuits
 To study the design of data path unit, control unit for processor and to
familiarizewith the hazards
 To understand the concept of various memories and I/O interfacing
 To introduce the concepts of adaptive filters and its application to
communicationengineering
UNIT I COMBINATIONAL LOGIC 9
Combinational Circuits – Karnaugh Map - Analysis and Design Procedures – Binary Adder –
Subtractor – Decimal Adder - Magnitude Comparator – Decoder – Encoder – Multiplexers –
Demultiplexers
UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9

Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables,
Triggering ofFF, Analysis and design of clocked sequential circuits – Design – Moore/Mealy
models, state minimization, state assignment, circuit implementation - Registers –
Counters.
UNIT III COMPUTER FUNDAMENTALS 9

Functional Units of a Digital Computer: Von Neumann Architecture – Operation and
Operands of Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory
Location, Address and Operation – Instruction and Instruction Sequencing – Addressing
Modes, Encoding of Machine Instruction – Interaction between Assembly and High Level
Language.
UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control,
Microprogrammed Control – Pipelining – Data Hazard – Control Hazards.
UNIT V MEMORY AND I/O 9

Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial
Interface – Interrupt I/O – Interconnection Standards: USB, SATA
45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture
OUTCOMES:
UPON COMPLETION OF THE COURSE, STUDENTS SHOULD BE ABLE TO

 Design various combinational digital circuits using logic gates
 Design sequential circuits and analyze the design procedures
 State the fundamentals of computer systems and analyze the execution of an instruction
 Analyze different types of control design and identify hazards
 Identify the characteristics of various memory systems and I/O communication
TOTAL : 75 PERIODS
TEXT BOOKS:
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog
HDL,VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and Design,
TheHardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier,
2020.
REFERENCES:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer

Organizationand Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing for Performance”,
Tenth Edition, Pearson Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
PROGRAM : COMPUTER SCIENCE AND ENGINEERING DEGREE : B.E
COURSE : DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION SEMESTER : III CREDITS :4
COURSE CODE: CS3351

COURSE TYPE : NON-CORE
REGULATION: 2021A
COURSE AREA/DOMAIN :DIGITAL ELECTRONICS AND COMPUTER CONTACT HOURS: 6
ORGANIZATION
LAB COURSE NAME (IF ANY) DPCO
CORRESPONDING LAB COURSE CODE (IF ANY): CS3351
INTEGRATED LAB
SYLLABUS:
UNIT DETAILS HOURS
COMBINATIONAL LOGIC
Combinational Circuits – Karnaugh Map – Analysis and Design Procedures – Binary Adder –
I Subtractor – Decimal Adder – Magnitude Comparator – Decoder – Encoder – Multiplexers – 9
Demultiplexer.
SYNCHRONOUS SEQUENTIAL LOGIC

II
Introduction to Sequential Circuits – Flip-Flops – operation and excitation tables, Triggering of 9
FF, Analysis and design of clocked sequential circuits – Design – Moore/Mealy models, state
minimization, state assignment, circuit implementation – Registers – Counters.
COMPUTER FUNDAMENTALS
Functional Units of a Digital Computer: Von Neumann Architecture – Operation and Operands
III of Computer Hardware Instruction – Instruction Set Architecture (ISA): Memory Location, 9
Address and Operation – Instruction and Instruction Sequencing – Addressing Modes,
Encoding of Machine Instruction – Interaction between Assembly and High Level Language.
PROCESSOR
IV Instruction Execution – Building a Data Path – Designing a Control Unit – Hardwired Control, 9
Microprogrammed Control – Pipelining – Data Hazard – Control Hazards
MEMORY AND I/O
Memory Concepts and Hierarchy – Memory Management – Cache Memories: Mapping and 9
V
Replacement Techniques – Virtual Memory – DMA – I/O – Accessing I/O: Parallel and Serial
Interface – Interrupt I/O – Interconnection Standards: USB, SATA.
TOTAL THEORY HOURS 45
PRACTICAL EXERCISES:
1. Verification of Boolean theorems using logic gates.
2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture
TOTAL PRACTICAL HOURS 30
TOTAL HOURS 75
TEXT/REFERENCE BOOKS:
T/R BOOK TITLE/AUTHORS/PUBLICATION

M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the Verilog HDL, VHDL, and System
T
Verilog”, Sixth Edition, Pearson Education, 2018.
David A. Patterson, John L. Hennessy, “Computer Organization and Design, The Hardware/Software Interface”, Sixth
T
Edition, Morgan Kaufmann/Elsevier, 2020.
Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization and Embedded Systems”,
R
Sixth Edition, Tata McGraw-Hill, 2012.
William Stallings, “Computer Organization and Architecture – Designing for Performance”, Tenth Edition, Pearson
R
Education, 2016.
R M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
COURSE PRE-REQUISITES:
C.CODE COURSE NAME DESCRIPTION SEM
BE3251 Basic Electrical And Electronics Engineering Study of Number Systems and K-Map Simplification II
COURSE OBJECTIVES:
1 To Analyze and Design Combinational circuits.
2 To Analyze and Design Sequential circuits.
3 To understand the basic structure and operation of a digital Computer.
4 To study the design of data path unit, control unit for processor and familiarize with the hazards.
5 To understand the concept of various memories and I/O interfacing.
CO1 : CO2 : CO3 : CO4 : CO5 : COURSE OUTCOMES:
S.NO. DESCRIPTION PO(1..12) PSO(1,2)

At the end of the course the students can able to MAPPING MAPPING
PO1, PO2, PO3, PO4, PO5, PSO1,

1 Design various combinational digital circuits using logic gates PO6, PO7, PO8, PO9, PSO2,PS03
PO10, PO11, PO12
2 Design sequential circuits and analyze the design procedures PO6, PO7, PO8, PO9, PSO2,PS03
PO10, PO11, PO12
State the fundamentals of computer systems and analyze the PO1, PO2, PO3, PO6, PO8, PSO1,
3 PO9, PO10, PO11, PO12 PSO2,PS03
execution of an instruction
4 Analyze different types of control design and identify hazards PO9, PO10, PO11, PO12 PSO2,PS03
Identify the characteristics of various memory systems and PO1, PO2, PO3, PO6, PO8, PSO1,
5 PO9, PO10, PO11, PO12 PSO2,PS03
I/O communication
COURSE OVERALL PO/PSO MAPPING : PO6, PO7, PO8, PO9, PSO2,PS03
PO10, PO11, PO12
COURSE OUTCOMES VS POs MAPPING (DETAILED; HIGH:3; MEDIUM:2; LOW:1):

SNO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
1 3 3 3 2 2 1 1 1 2 2 2 3 2 2 3
2 3 3 3 2 2 1 1 1 2 2 2 3 2 2 3
3 3 2 3 1 1 2 2 2 2 2 2 3
4 3 2 3 1 1 2 2 2 2 2 2 3
5 3 2 3 1 1 2 2 2 2 2 2 3
* 3 2 3 1 1 1 1 1 2 2 2 2 2 2 3
* For Entire Course, PO & PSO Mapping
POs & PSO REFERENCE:

PO1 Engineering PO7 Environment & PSO1 Exhibit design and programming skills to build and
Knowledge Sustainability automate business solutions using cutting edge
technologies.
PO2 Problem PO8 Ethics PSO2 Strong theoretical foundation leading to excellence and
Analysis excitement towards research, to provide elegant
solutions to complex problems.
PO3 Design & PO9 Individual & Team PSO3 Ability to work effectively with various engineering
Development Work fields as a team to design, build and develop system
applications.
PO4 Investigations PO10 Communication
Skills
PO5 Modern Tools PO11 Project Mgt. &
Finance
PO6 Engineer & PO12 Life Long Learning
Society
COs VS POs MAPPING JUSTIFICATION:

S.NO PO/PSO MAPPED LEVEL OF MAPPING JUSTIFICATION
PO1 HIGH Students understand the need for logic expression simplification and their methods.
Students will be able to analyze the problem and apply appropriate minimization
PO2 HIGH
technique.
PO3 HIGH It gives the knowledge of combinational circuits and their designing procedure.
Students can able to investigate the input and output expression based on the
PO4 MEDIUM
application of the circuit
To design combinational circuits, modern IT tools may be created and applied for
PO5 MEDIUM
simulation.
Applying reasoning informed by the contextual knowledge to assess digital circuits
PO6 LOW
knowledge.
I
PO7 LOW While planning digital circuits knowledge is essential.
PO8 LOW While planning for digital circuits ethical principles are to be applied.
PO9 MEDIUM To identify the need for digital circuits system team work is needed.
PO10 MEDIUM While identifying the need for future digital circuits Communication is essential.
The project work needs project management, demonstration of one’s knowledge to
PO11 MEDIUM
other members in a team.
The identification of digital circuits may be done effectively to match with the present
PO12 HIGH
demands with the continuous improvement in the knowledge about present scenario.
To built an automated business solution student can able to exhibit design and
PSO1 LOW
programming skills
Based on theoretical and practical foundations students can able to do research to
PS02 LOW
provide solutions for complex problems
PS03 HIGH Students can able to design,build and develop system application.
PO1 HIGH By applying Engineering Knowledge student can able to design sequential circuits.
PO2 HIGH While designing the sequential circuits circuits ,analyzing process is essential.
PO3 HIGH Student can able to design and develop the sequential circuits based on the application.
Students can able to investigate the input and output expression based on the
PO4 MEDIUM
application of the circuit
To design combinational circuits, modern IT tools may be created and applied for
PO5 MEDIUM
simulation.
Applying reasoning informed by the contextual knowledge to assess digital circuits
PO6 LOW
knowledge.
PO7 LOW While planning digital circuits knowledge is essential.
PO8 LOW While planning for digital circuits ethical principles are to be applied.
II
PO9 MEDIUM To identify the need for digital circuits system team work is needed.
PO10 MEDIUM While identifying the need for future digital circuits Communication is essential.
The project work needs project management, demonstration of one’s knowledge to
PO11 MEDIUM
other members in a team.
The identification of digital circuits may be done effectively to match with the present
PO12 HIGH
demands with the continuous improvement in the knowledge about present scenario.
To built an automated business solution student can able to exhibit design and
PSO1 LOW
programming skills
Based on theoretical and practical foundations students can able to do research to
PS02 LOW
PS03 HIGH Students can able to design ,build and develop system application.
Students can able to know the fundamentals of computer and gain engineering
PO1 HIGH
knowledge.
By analysing different methods student can understand the concept of computer
PO2 MEDIUM
architecture.
PO3 HIGH Using problem analysis one can design a basic Functional units of Computer.
By using proper techniques one can design the basic computer by considering society
PO6 LOW
needs
While planning to design any functional units of computer ethical principles are to be
PO8 LOW applied
III MEDIUM Team work is good for analyzing, faults in computer systems.
PO9
MEDIUM Proper instructions may be communicated between professionals and the society or
PO10
between professionals about the various computer systems.
MEDIUM While analyzing the Project work, knowledge may be demonstrated to understand
PO11
Computer fundamentals.
MEDIUM To analyze the Project work, life-long learning is essential to adapt for new changes in
PO12
technology.
MEDIUM To built an automated business solution student can able to exhibit design and
PSO1
programming skills
MEDIUM Based on theoretical and practical foundations students can able to do research to
PS02
Students can able to know the Processor unit of computer and gain engineering
PO1 HIGH
knowledge.
By analysing different methods student can understand the concept of control unit
PO2 MEDIUM
design.
PO3 HIGH Using problem analysis one can design a basic control units of Computer.
PO6 LOW
needs
While planning to design any fprocessor units of computer ethical principles are to be
PO8 LOW applied
MEDIUM Team work is good for analyzing, faults in computer systems.

PO9
IV MEDIUM Proper instructions may be communicated between professionals and the society or
PO10
PO11
Computer fundamentals.
PO12
technology.
PSO1
programming skills
PS02
Students can able to know the Processor unit of computer and gain engineering
PO1 HIGH
knowledge.
By analysing different methods student can understand the concept of control unit
PO2 MEDIUM
design.
PO3 HIGH Using problem analysis one can design a basic control units of Computer.
PO6 LOW
needs
While planning to design any fprocessor units of computer ethical principles are to be
PO8 LOW applied
MEDIUM Team work is good for analyzing, faults in computer systems.

PO9
V MEDIUM Proper instructions may be communicated between professionals and the society or
PO10
PO11 Computer fundamentals.
PO12
technology.
PSO1
programming skills
PS02
GAPS IN THE SYLLABUS – TO MEET INDUSTRY/PROFESSION REQUIREMENTS, Pos & PSOs:

SNO DESCRIPTION PROPOSED
ACTIONS
1 Digital design using verilog NPTEL
2 Design of simple computer using CPU sim YOUTUBE
TOPICS BEYOND SYLLABUS/ADVANCED TOPICS/DESIGN:

1. HDL Models of Combinational Circuits.
2. HDL Models of Registers and Counters
3. Hardware Multithreading
4 Exception handling in MIPS Architecture
5 Introduction to Graphics Processor Units.
WEB SOURCE REFERENCES:

1. https://onlinecourses.nptel.ac.in/noc22_ee110/unit?unit=41&lesson=46
2. https://onlinecourses.nptel.ac.in/noc22_ee110/unit?unit=57&lesson=60
3. https://nptel.ac.in/courses/106105163
4. https://www.youtube.com/watch?v=Ol8D69VKX2k
5. https://www.youtube.com/results?search_query=computer+architecture+and+organization+in+one+video
DELIVERY/INSTRUCTIONAL METHODOLOGIES:
☐ CHALK & TALK ☐ STUD. ASSIGNMENT ☐ WEB RESOURCES ☐ NPTEL/OTHERS
☐ LCD/SMART BOARDS ☐ STUD. SEMINARS ☐ ADD-ON COURSES ☐ WEBNIARS
ASSESSMENT METHODOLOGIES-DIRECT
☐ ASSIGNMENTS ☐ STUD. SEMINARS ☐ TESTS/MODEL EXAMS ☐ UNIV. EXAMINATION
☐ STUD. LAB PRACTICES ☐ STUD. VIVA ☐ MINI/MAJOR PROJECTS ☐ CERTIFICATIONS
☐ ADD-ON COURSES ☐ OTHERS
ASSESSMENT METHODOLOGIES-INDIRECT
☐ ASSESSMENT OF COURSE OUTCOMES (BY FEEDBACK, ONCE) ☐ STUDENT FEEDBACK ON FACULTY (TWICE)
☐ ASSESSMENT OF MINI/MAJOR PROJECTS BY EXT. EXPERTS ☐ OTHERS
INNOVATIONS IN TEACHING/LEARNING/EVALUATION PROCESSES:
1. Introduction and use of specialized software tools for the analysis of computer architecture
2. Teaching other simulation software used for solving digital circuit’s problem.
LIST OF EXPERIMENTS
Page Marks Signature
Sl. No. Date Name of the Experiment
No.
Verification of Boolean theorems using logic

1 gates.
Design and implementation of combinational

2 circuits using gates for arbitrary functions.
Implementation of binary adder/subtractor

3
circuits.
Implementation of code converters.

4
Implementation of BCD adder, encoder and

5 decoder circuits
Implementation of functions using

6 Multiplexers.
7 Implementation of the synchronous counters
8 Implementation of a Universal Shift register.
Simulator based study of Computer

9 Architecture
Ex.No.-1 VERIFICATION OF BOOLEAN THEOREMS USING LOGIC GATES
AIM:
To verify the Boolean Theorems using logic gates.
APPARATUS REQUIRED:
SL. NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
5. CONNECTING WIRES As per
- required
THEORY:
BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A
2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
1. A+AB = A
2. A+AB = A+B
5. Involution (or) Double complement Law

1. A = A
6. Idempotent Law
1. A+A = A
2. A.A = A
7. Complementary Law
1. A+A' = 1
2. A.A' = 0
8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
ASSOCIATIVE LAW
A+(B+C) = (A+B)+C A * (B * C) = (A * B) * C
TRUTH TABLE:
DISTRIBUTIVE LAW
A.(B+C) = (A.B)+(A.C)
TRUTH TABLE
DEMORGAN’S THEOREM
De-Morgan's First Theorem:
According to the first theorem, the complement result of the AND operation is equal to the
OR operation of the complement of that variable. Thus, it is equivalent to the NAND function
and is a negative-OR function proving that (A.B)' = A'+B' and we can show this using the
following table.
De-Morgan's Second Theorem
According to the second theorem, the complement result of the OR operation is equal to
the AND operation of the complement of that variable. Thus, it is the equivalent of the NOR
function and is a negative-AND function proving that (A+B)' = A'.B' and we can show this using
the following truth table.
COMMUTATIVE LAW
A.B=B.A
A+B = B+A
PROCEDURE:
1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
RESULT
Thus the above stated Boolean laws are verified.

Ex.No.-2 DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING

GATES FOR ARBITRARY FUNCTIONS.
AIM:
To design and implementation of combinational circuits using gates for arbitrary
functions.
APPARATUS REQUIRED
SL.NO. COMPONENT SPECIFICATION QTY

1 DC Power Supply 5V 1
Digital Trainer (Logic
2 - 1
Probe)
3 Breadboard - 1
4 DIP Switch - 1
5 NAND gate IC7400 1
6 NOR gate IC7402 1
7 Inverter IC7404 1
8 AND gate IC7408 1
9 OR gate IC7432 1
THEORY
Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT
gates that are “combined” or connected together to produce more complicated switching
circuits. These logic gates are the building blocks of combinational logic circuits. An example
of a combinational circuit is a decoder, which converts the binary code data present at its
input into a number of different output lines, one at a time producing an equivalent decimal
code at its output. PROCEDUE
Procedure:
1) Determine required number of inputs and outputs from the specifications.

2) Derive the truth table for each of the outputs based on their relationships to the input.
3) Simplify the Boolean expression for each output. ...
4) Draw a logic diagram that represents the simplified Boolean expression.
.
NAND Gate
Let's look at the outputs of a NAND gate. This means A NOT-AND B, or A.B (A dot B).
Graphically this is represented by a line over the A.B in the diagram.
Logic Gate Circuit Diagram
NOR Gate
The NOR, or NOT-OR gate means that if ANY of the inputs are ON, then the gate is
OFF. In other words, if both are off, then the output is ON. This is indicated by an A + B
notation, with the line above (as in the NAND gate). Let's look at the diagram first.
Logic Diagram
Converting From One to the Other

Let's put it all together and look at our full circuit as shown in Figure 4. We still have
theNAND gate and the NOR gate, but now we have the input C.
But, based on the diagram, we know that we have a NAND and a NOR. Look at input C:
there isno gate, so if C is ON, and none of the other switches are on, then Q is ON.
Given the diagram, we can build a Boolean Expression as seen in Figure 5. Each dot (.)
means anAND condition. It's a NAND gate AND a NOR gate AND gate C.
RESULT:
Thus the combinational circuits for arbitrary functions designed and implemented
using logic gates.
Ex.No -3 IMPLEMENTATION OF BINARY ADDER/SUBTRACTOR CIRCUITS.
AIM:
To design and implementation of binary adder/subtractor circuits
APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.

2. X-OR GATE IC 7486 1
6. PATCH CORDS - 23
THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
thesum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR
Gate the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists ofthree inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry
output will be takenfrom OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor
has two input and two outputs. The outputs are difference and borrow. The difference can
be applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be
difference output of full subtractor. The expression AB assembles the borrow output of the
half subtractor and the second term is the inverted difference outputof first X-OR.
HALF ADDER
LOGIC DIAGRAM TRUTH TABLE
K-Map for SUM: K-Map for CARRY:
1
1
SUM = A’B + AB’ CARRY = AB

FULL ADDER
LOGIC DIAGRAM:
TRUTH TABLE:
K-Map for SUM
1 1
1 1
SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY
CARRY = AB + BC + AC
HALF SUBTRACTOR
LOGIC DIAGRAM TRUTH TABLE
K-Map for DIFFERENCE K-Map for BORROW
1 1
DIFFERENCE = A’B + AB’ BORROW = A’B

FULL SUBTRACTOR
LOGIC DIAGRAM
TRUTH TABLE
K-Map for Difference
Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow
Borrow = A’B + BC + A’C
PROCEEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT
Thus, the half adder, full adder, half subtractor and full subtractor circuits are designed,
constructed and verified the truth table using logic gates.
EX.No:4 IMPLEMENTATION OF CODE CONVERTERS
AIM
To design and implement 4-bit
(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
APPARATUS REQUIRED
Sl. Component Specification Qty.

No.
1. X-OR GATE IC 7486 1
6. PATCH CORDS - 35
THEORY:
The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by different systems. A conversion circuit must be
inserted between the two systems if each uses different codes for same information. Thus,
code converter is a circuit that makes the two systems compatible even though each uses
different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input
lines must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents one
of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D has been used to implement
partially each of three outputs.
BINARY TO GRAY CODE CONVERTOR
LOGIC DIAGRAM
K-Map for G3 K-Map for G2
G3 = B3
K-Map for G1 K-Map for G0

Truth Table
Binary input | Gray code output
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
GRAY CODE TO BINARY CONVERTOR
Logic Diagram
K-Map for B3 K-Map for B2
B3 = G3
K-Map for B1 K-Map for B0
Truth Table
BCD TO EXCESS-3 CONVERTOR
Logic Diagram
K-Map for E3 K-Map for E2
E3 = B3 + B2 (B0 + B1)
K-Map for E1 K-Map for E0
Truth Table
EXCESS-3 TO BCD CONVERTOR
Logic Diagram
K-Map for A K-Map for B
A = X1 X2 + X3 X4 X1
K-Map for C K-Map for D
Truth Table
PROCEDURE
(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
RESULT
Thus, binary to gray code converter, Gray to binary code converter, BCD to excess-3 code
converter, Excess-3 to BCD code converter was implemented.
IMPLEMENTATION OF BCD ADDER, ENCODER AND

EX.No:5
DECODER CIRCUITS
AIM
To design and implement of BCD adder, encoder and decoder circuits
Apparatus Required
Sl. No. Component Specification Qty.
1. IC IC 7483 1
2. EX-OR Gate IC 7486 1
3. OR Gate IC 7432 3
4. NOT Gate IC 7404 1
5. 3 I/P NAND Gate IC 7410 2
6. IC Trainer Kit - 1
7. Patch Cords - 40
BCD ADDER
THEORY
Consider the arithmetic addition of two decimal digits in BCD, together withan
input carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal
digits must be represented in BCD and should appear in the form listed in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the binary
sum.
Pin Diagram for IC 7483
LOGIC DIAGRAM
K- MAP
Y = S4 (S3 + S2)
TRUTH TABLE:
BCD SUM CARRY
S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
ENCODER AND DECODER
THEORY
ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder.
An encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight inputs,
one for each octal digit and three output that generate the corresponding binary code. In
encoder it is assumed that only one input has a value of one at any given time otherwise the
circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero.
The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word
i.e there is one to one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2 n possible outputs. 2n
output values arefrom 0 through out 2n– 1.
LOGIC DIAGRAM FOR ENCODER
TRUTH TABLE
Logic Diagram for Decoder
TRUTH TABLE
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
Procedure

RESULT
Thus, the BCD Adder, Encoder and Decoder were designed using logic gates and implemented
successfully.
IMPLEMENTATION OF FUNCTIONS USING

EX.No:6 MULTIPLEXERS.
AIM
To Implementation of functions using Multiplexers.
APPARATUS REQUIRED
Sl. No. Component Specification Qty.

1. 3 I/P AND GATE IC 7411 2
3. PATCH CORDS - 32
THEORY
MULTIPLEXER
Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n input line
andn selection lines whose bit combination determine which input is selected.
Block Diagram for 4:1 Multiplexer

Circuit Diagram For Multiplexer
Truth Table
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Procedure

RESULT
Thus, the multiplexer was designed using logic gates and implemented successfully.
IMPLEMENTATION OF THE SYNCHRONOUS

EX. No: 7
COUNTERS
AIM:
To design and Implementation of the synchronous counters.
APPARATUS REQUIRED:
S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
2. D Flip Flop IC 7474 4
3. NAND gate IC 7400 1
4. Connecting wires As required
THEORY
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There
are two types of counter, synchronous and asynchronous. In synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then
each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of
second stage is triggered by output of first stage. Because of inherent propagation delay time
all flip flops are not activated at same time which results in asynchronous operation.
TRUTH TABLE:
OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM
PROCEDURE:

RESULT:
Thus the synchronous counters are designed, implemented and verified its truth
table.
EX.No:8 IMPLEMENTATION OF A UNIVERSAL SHIFT REGISTER
AIM
To design and Implementation of a Universal Shift register
APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
4. PATCH CORDS - 35
THEORY:
A register is capable of shifting its binary information in one or both directions is known
as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded
with output of one flip flop connected to input of next flip flop. All flip flops receive common
clock pulses which causes the shift in the output of the flip flop. The simplest possible shift
register is onethat uses only flip flop. The output of a given flip flop is connected to the input of
next flip flop of the register. Each clock pulse shifts the content of register one bit position to
right.
PIN DIAGRAM OF IC 7474:

SERIAL IN SERIAL OUT
LOGIC DIAGRAM:
TRUTH TABLE:
CLK Serial In Serial Out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1
SERIAL IN PARALLEL OUT
LOGIC DIAGRAM:
TRUTH TABLE:
OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
PARALLEL IN SERIAL OUT
LOGIC DIAGRAM:
TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
PARALLEL IN PARALLEL OUT
LOGIC DIAGRAM:
TRUTH TABLE:
DATA INPUT OUTPUT

CLK
DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
PROCEDURE:
RESULT:
The Serial in serial out, Serial in parallel out, Parallel in serial out and Parallel in
parallelout shift registers are designed and implemented.
SIMULATOR BASED STUDY OF COMPUTER

EX.No: 9 ARCHITECTURE
AIM
To Simulator based study of Computer Architecture
THEORY
Computer architecture simulators are used for the following purposes:
 Lowering cost by evaluating hardware designs without building physical hardware systems.
 Enabling access to unobtainable hardware.
 Increasing the precision and volume of computer performance data.
 Introducing abilities that are not normally possible on real hardware such as running code
backwards when an error is detected or running in faster-than-real time
FULL-SYSTEM SIMULATORS
A full-system simulator is execution-driven architecture simulation at such a level of

detail that complete software stacks from real systems can run on the simulator without any
modification. A full system simulator provides virtual hardware that is independent of the
nature of the host computer. The full-system model typically includes processor cores,
peripheral devices, memories, interconnection buses, and network connections. Emulators are
full system simulators that imitate obsolete hardware instead of under development hardware.
The defining property of full-system simulation compared to an instruction set simulator is that
themodel allows real device drivers and operating systems to be run, not just single programs.
Thus, full-system simulation makes it possible to simulate individual computers and networked
computernodes with all their software, from network device drivers to operating systems,
network stacks, middleware, servers, and application programs.
Full system simulation can speed the system development process by making it easier to detect,
recreate and repair flaws. The use of multi-core processors is driving the need for full system
simulation, because it can be extremely difficult and time-consuming to recreate and debug
errors without the controlled environment provided by virtual hardware. This also allows the
software development to take place before the hardware is ready, thus helping to validate
design decisions.
CYCLE-ACCURATE SIMULATOR
A cycle-accurate simulator is a computer program that simulates a micro architecture
on a cycle-by-cycle basis. In contrast an instruction set simulator simulates an instruction set
architecture usually faster but not cycle-accurate to a specific implementation of this
architecture;
they are often used when emulating older hardware, where time precision is important for
legacy reasons. Often, a cycle-accurate simulator is used when designing new microprocessors
– they can be tested, and benchmarked accurately (including running full operating system, or
compilers) without actually building a physical chip, and easily change design many times to
meet expected plan.
Cycle-accurate simulators must ensure that all operations are executed in the proper
virtual (or real if it is possible) time – branch prediction, cache misses, fetches, pipeline stalls,
thread context switching, and many other subtle aspects of microprocessors.
INSTRUCTION SET SIMULATOR (ISS).

An instruction set simulator (ISS) is a simulation model, usually coded in a high-level
programming language, which mimics the behavior of a mainframe or microprocessor by
"reading" instructions and maintaining internal variables which represent the processor's
registers.
Instruction simulation is a methodology employed for one of several possible reasons:
 To simulate the machine code of another hardware device or entire computer for
upward compatibility—a full system simulator typically includes an instruction set
simulator.
For example, the IBM 1401 was simulated on the later IBM/360 through
use of microcode emulation.
 To monitor and execute the machine code instructions (but treated as an input stream)
on the same hardware for test and debugging purposes, e.g. with memory protection
(which protects against accidental or deliberate buffer overflow).
 To improve the speed performance—compared to a slower cycle-accurate
simulator—of simulations involving a processor core where the processor itself is not
one of the elements being verified; in hardware description language design using
Verilog where simulation with tools like ISS[citation needed] can be run faster by means of
"PLI" (not to be confused with PL/1, which is a programming language).
SIMULATION TYPES
 Discrete Event Simulation. Modeling a system as it progresses through time,

forexample; ...
 Dynamic Simulation. Modeling a system as it progresses through space, for example; ...
 Process Simulation.
SIMULATION SOFTWARES
1. 20-SIM - Bond Graph-Based Multi-Domain Simulation Software

2. MATLAB - a programming, modeling and simulation tool developed by Math Works
3. SIMUL8 - software for discrete event or process based simulation
4. SIMULINK - a tool for block diagrams, electrical mechanical systems and machines
from Math Works.
5. ADVANCED SIMULATION LIBRARY - open-source hardware accelerated
metaphysicssimulation software
6. GNU Octave - an open-source mathematical modeling and simulation software very
similarto using the same language as MATLAB and Free mat
7. VSim - a multiphysics simulation software tool designed to run computationally
intensiveelectromagnetic, electrostatic, and plasma simulations
COMPUTER ARCHITECTURE
SIMULATION MODELS
RESULT
Thus the studied simulator based computer architecture are implemented.

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ARUNAI ENGINEERING COLLEGE

DEPARTMENT OF COMPUTER SCIENCE AND

CS3351-DIGITAL PRINCIPLES AND

DEPARTMENT OF COMPUTER SCIENCE AND

Submitted for the Practical Examination held on

Internal Examiner External Examiner

I. PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

II. PROGRAM OUTCOMES (POs)

PO# Graduate Attribute

III. PROGRAM SPECIFIC OUTCOMES (PSOs)

Graduates should be able to:

CS3351 DIGITAL PRINCIPLES AND COMPUTER L T P C

 To analyze and design combinational circuits

UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9

UNIT III COMPUTER FUNDAMENTALS 9

UNIT V MEMORY AND I/O 9

PRACTICAL EXERCISES: 30 PERIODS

1. Verification of Boolean theorems using logic gates.

UPON COMPLETION OF THE COURSE, STUDENTS SHOULD BE ABLE TO

1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer

PROGRAM : COMPUTER SCIENCE AND ENGINEERING DEGREE : B.E

COURSE : DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION SEMESTER : III CREDITS :4

COURSE CODE: CS3351

SYNCHRONOUS SEQUENTIAL LOGIC

T/R BOOK TITLE/AUTHORS/PUBLICATION

2 To Analyze and Design Sequential circuits.

3 To understand the basic structure and operation of a digital Computer.

5 To understand the concept of various memories and I/O interfacing.

CO1 : CO2 : CO3 : CO4 : CO5 : COURSE OUTCOMES:

S.NO. DESCRIPTION PO(1..12) PSO(1,2)

PO1, PO2, PO3, PO4, PO5, PSO1,

COURSE OUTCOMES VS POs MAPPING (DETAILED; HIGH:3; MEDIUM:2; LOW:1):

POs & PSO REFERENCE:

COs VS POs MAPPING JUSTIFICATION:

PO7 LOW While planning digital circuits knowledge is essential.

MEDIUM Team work is good for analyzing, faults in computer systems.

MEDIUM Team work is good for analyzing, faults in computer systems.

GAPS IN THE SYLLABUS – TO MEET INDUSTRY/PROFESSION REQUIREMENTS, Pos & PSOs:

2 Design of simple computer using CPU sim YOUTUBE

TOPICS BEYOND SYLLABUS/ADVANCED TOPICS/DESIGN:

WEB SOURCE REFERENCES:

INNOVATIONS IN TEACHING/LEARNING/EVALUATION PROCESSES:

Verification of Boolean theorems using logic

Design and implementation of combinational

Implementation of binary adder/subtractor

Implementation of code converters.

Implementation of BCD adder, encoder and

Implementation of functions using

7 Implementation of the synchronous counters

8 Implementation of a Universal Shift register.

Simulator based study of Computer

Ex.No.-1 VERIFICATION OF BOOLEAN THEOREMS USING LOGIC GATES

To verify the Boolean Theorems using logic gates.

SL. NO. COMPONENT SPECIFICATION QTY.

BASIC BOOLEAN LAWS

5. Involution (or) Double complement Law

De-Morgan's First Theorem:

De-Morgan's Second Theorem

1. Obtain the required IC along with the Digital trainer kit.

Thus the above stated Boolean laws are verified.

Ex.No.-2 DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING

SL.NO. COMPONENT SPECIFICATION QTY

1) Determine required number of inputs and outputs from the specifications.