ADDRESSING MODES:

MICROPROCESSOR:
8085
Types of addressing modes –
In 8085 microprocessor there are 5 types of addressing modes:

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Immediate Addressing Mode –

In immediate addressing mode the source operand is always data. If the data is
8-bit, then the instruction will be of 2 bytes, if the data is of 16-bit then the
instruction will be of 3 bytes.

Examples:

MVI B 45 (move the data 45H immediately to register B)

LXI H 3050 (load the H-L pair with the operand 3050H immediately)

JMP address (jump to the operand address immediately)

Register Addressing Mode –

In register addressing mode, the data to be operated is available inside the

register(s) and register(s) is(are) operands. Therefore the operation is performed
within various registers of the microprocessor.

Examples:

MOV A, B (move the contents of register B to register A)

ADD B (add contents of registers A and B and store the result in register A)

INR A (increment the contents of register A by one)

Direct Addressing Mode –

In direct addressing mode, the data to be operated is available inside a memory

location and that memory location is directly specified as an operand. The
operand is directly available in the instruction itself.

Examples:

LDA 2050 (load the contents of memory location into accumulator A)

LHLD address (load contents of 16-bit memory location into H-L register pair)

IN 35 (read the data from port whose address is 35)

Register Indirect Addressing Mode –

In register indirect addressing mode, the data to be operated is available inside a

memory location and that memory location is indirectly specified by a register
pair.

Examples:

MOV A, M (move the contents of the memory location pointed by the H-L pair
to the accumulator)

LDAX B (move contents of B-C register to the accumulator)

LXIH 9570 (load immediate the H-L pair with the address of the location 9570)

Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to be

operated is available in the instruction itself.

Examples:

CMA (finds and stores the 1’s complement of the contents of accumulator A in
A)

RRC (rotate accumulator A right by one bit)

RLC (rotate accumulator A left by one bit)

 MICROPROCESSOR:
8086

Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is
known as immediate addressing mode.

Example
MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFH

Register addressing mode

It means that the register is the source of an operand for an instruction.

Example
MOV CX, AX ; copies the contents of the 16-bit AX register into
; the 16-bit CX register),
ADD BX, AX

Direct addressing mode

The addressing mode in which the effective address of the memory location is
written directly in the instruction.

Example
MOV AX, [1592H], MOV AL, [0300H]

Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through
an offset address held in any of the following registers: BP, BX, DI & SI.

Example
MOV AX, [BX] ; Suppose the register BX contains 4895H, then the
contents
; 4895H are moved to AX
ADD CX, {BX}

Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of
contents of the BX/BP registers and 8-bit/16-bit displacement.

Example
MOV DX, [BX+04], ADD CL, [BX+08]
Indexed addressing mode
In this addressing mode, the operands offset address is found by adding the
contents of SI or DI register and 8-bit/16-bit displacements.

Example
MOV BX, [SI+16], ADD AL, [DI+16]

Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing
the base register to the contents of an Index register.

Example
ADD CX, [AX+SI], MOV AX, [AX+DI]

Based indexed with displacement mode

In this addressing mode, the operands offset is computed by adding the base
register contents. An Index registers contents and 8 or 16-bit displacement.

Example
MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]

MICROCONTROLLER:
 8081
Immediate Addressing
In Immediate Addressing mode, the operand, which follows the Opcode, is a
constant data of either 8 or 16 bits. The name Immediate Addressing came from
the fact that the constant data to be stored in the memory immediately follows
the Opcode.

The constant value to be stored is specified in the instruction itself rather than
taking from a register. The destination register to which the constant data must
be copied should be the same size as the operand mentioned in the instruction.

Example: MOV A, #030H

Here, the Accumulator is loaded with 30 (hexadecimal). The # in the operand

indicates that it is a data and not the address of a Register.

Immediate Addressing is very fast as the data to be loaded is given in the

instruction itself.

Register Addressing
In the 8051 Microcontroller Memory Organization Tutorial, we have seen the
organization of RAM and four banks of Working Registers with eight Registers
in each bank.

In Register Addressing mode, one of the eight registers (R0 – R7) is specified as
Operand in the Instruction.

It is important to select the appropriate Bank with the help of PSW Register. Let
us see a example of Register Addressing assuming that Bank0 is selected.

Example: MOV A, R5

Here, the 8-bit content of the Register R5 of Bank0 is moved to the

Accumulator.

Direct Addressing
In Direct Addressing Mode, the address of the data is specified as the Operand
in the instruction. Using Direct Addressing Mode, we can access any register or
on-chip variable. This includes general purpose RAM, SFRs, I/O Ports, Control
registers.

Example: MOV A, 47H

Here, the data in the RAM location 47H is moved to the Accumulator.

Register Indirect Addressing

In the Indirect Addressing Mode or Register Indirect Addressing Mode, the
address of the Operand is specified as the content of a Register. This will be
clearer with an example.

Example: MOV A, @R1

The @ symbol indicates that the addressing mode is indirect. If the contents of
R1 is 56H, for example, then the operand is in the internal RAM location 56H.
If the contents of the RAM location 56H is 24H, then 24H is moved into
accumulator.

Only R0 and R1 are allowed in Indirect Addressing Mode. These register in the
indirect addressing mode are called as Pointer registers.

Indexed Addressing Mode

With Indexed Addressing Mode, the effective address of the Operand is the sum
of a base register and an offset register. The Base Register can be either Data
Pointer (DPTR) or Program Counter (PC) while the Offset register is the
Accumulator (A).

In Indexed Addressing Mode, only MOVC and JMP instructions can be used.
Indexed Addressing Mode is useful when retrieving data from look-up tables.

Example: MOVC A, @A+DPTR

Here, the address for the operand is the sum of contents of DPTR and
Accumulator.
INTERRUPTS
Interrupts in 8085
Interrupts are the signals generated by the external devices to
request the microprocessor to perform a task. There are 5 interrupt
signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their
parameter −
 Vector interrupt − In this type of interrupt, the interrupt
address is known to the processor. For example: RST7.5,
RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt
address is not known to the processor so, the interrupt
address needs to be sent externally by the device to perform
interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable
the interrupt by writing some instructions into the
program. For example: RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot
disable the interrupt by writing some instructions into the
program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer
has to add the instructions into the program to execute the
interrupt. There are 8 software interrupts in 8085, i.e. RST0,
RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used
as hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5,
INTA.
8086 INTERRUPTS
Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through
a specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-
maskable interrupt and INTR is a maskable interrupt having lower priority. One
more interrupt pin associated is INTA called interrupt acknowledge.

NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the
maskable interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of the
return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.

INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted
only if interrupts are enabled using set interrupt flag instruction. It should not be
enabled using clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is
disabled, then the microprocessor first completes the current execution and sends
‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get
ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from
the programmable interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return
address are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0
Software Interrupts

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides
the interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed
on to the stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H
similarly for type2 is 00008H and ……so on. The first five pointers are dedicated
interrupt pointers. i.e. −
 TYPE 0 interrupt represents division by zero situation.
 TYPE 1 interrupt represents single-step execution during the debugging of a
program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors, and interrupts from 32 to Type 255 are available for hardware and
software interrupts.

INT 3-Break Point Interrupt Instruction

It is a 1-byte instruction having op-code is CCH. These instructions are inserted into
the program so that when the processor reaches there, then it stops the normal
execution of program and follows the break-point procedure.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed
on to the stack.
 IP is loaded from the contents of the word location 3×4 = 0000CH
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction
is CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is active
only when the overflow flag is set to 1 and branches to the interrupt handler whose
interrupt type number is 4. If the overflow flag is reset then, the execution continues
to the next instruction.
Its execution includes the following steps −
 Flag register values are pushed on to the stack.
 CS value of the return address and IP value of the return address are pushed
on to the stack.
 IP is loaded from the contents of word location 4×4 = 00010H
 CS is loaded from the contents of the next word location.
 Interrupt flag and Trap flag are reset to 0

8051- INTERRRUPTS
Interrupts are the events that temporarily suspend the main program, pass the
control to the external sources and execute their task. It then passes the control
to the main program where it had left off.
8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt
can be enabled or disabled by setting bits of the IE register and the whole
interrupt system can be disabled by clearing the EA bit of the same register.

The 8051 controller has six hardware interrupts of which five are available to
the programmer. These are as follows:
 
1. RESET interrupt – This is also known as Power on Reset (POR). When the
RESET interrupt is received, the controller restarts executing code from 0000H
location. This is an interrupt which is not available to or, better to say, need not
be available to the programmer.
 
2. Timer interrupts – Each Timer is associated with a Timer interrupt. A timer
interrupt notifies the microcontroller that the corresponding Timer has finished
counting.
 
3. External interrupts – There are two external interrupts EX0 and EX1 to
serve external devices. Both these interrupts are active low. In AT89C51, P3.2
(INT0) and P3.3 (INT1) pins are available for external interrupts 0 and 1
respectively. An external interrupt notifies the microcontroller that an external
device needs its service.
 
4. Serial interrupt – This interrupt is used for serial communication. When
enabled, it notifies the controller whether a byte has been received or
transmitted.

FLAG REGISTERS 8085

Sign Flag (S) – After any operation if the MSB (B(7)) of the result is
1, it indicates the number is negative and the sign flag becomes set,
i.e. 1. If the MSB is 0, it indicates the number is positive and the sign
flag becomes reset i.e. 0.
from 00H to 7F, sign flag is 0
from 80H to FF, sign flag is 1
1- MSB is 1 (negative)
0- MSB is 0 (positive)

Example:
MVI A 30 (load 30H in register A)
MVI B 40 (load 40H in register B)
SUB B (A = A – B)
These set of instructions will set the sign flag to 1 as 30 – 40 is a
negative number.

MVI A 40 (load 40H in register A)

MVI B 30 (load 30H in register B)
SUB B (A = A – B)
These set of instructions will reset the sign flag to 0 as 40 – 30 is a
positive number.

Zero Flag (Z) – After any arithmetical or logical operation if the

result is 0 (00)H, the zero flag becomes set i.e. 1, otherwise it
becomes reset i.e. 0.
00H zero flag is 1.
from 01H to FFH zero flag is 0
1- zero result
0- non-zero result

Example:
MVI A 10 (load 10H in register A)
SUB A (A = A – A)
These set of instructions will set the zero flag to 1 as 10H – 10H is
00H

Auxiliary Carry Flag (AC) – This flag is used in BCD number

system(0-9). If after any arithmetic or logical operation D(3)
generates any carry and passes on to B(4) this flag becomes set i.e. 1,
otherwise it becomes reset i.e. 0. This is the only flag register which is
not accessible by the programmer
1-carry out from bit 3 on addition or borrow into bit 3 on subtraction
0-otherwise

Example:

MOV A 2B (load 2BH in register A)

MOV B 39 (load 39H in register B)
ADD B (A = A + B)
These set of instructions will set the auxiliary carry flag to 1, as on
adding 2B and 39, addition of lower order nibbles B and 9 will
generate a carry.
Parity Flag (P) – If after any arithmetic or logical operation the result
has even parity, an even number of 1 bits, the parity register becomes
set i.e. 1, otherwise it becomes reset i.e. 0.
1-accumulator has even number of 1 bits
0-accumulator has odd parity

Example:

MVI A 05 (load 05H in register A)

This instruction will set the parity flag to 1 as the BCD code of 05H is
00000101, which contains even number of ones i.e. 2.

Carry Flag (CY) – Carry is generated when performing n bit

operations and the result is more than n bits, then this flag becomes
set i.e. 1, otherwise it becomes reset i.e. 0.
During subtraction (A-B), if A>B it becomes reset and if (A<B) it
becomes set.
Carry flag is also called borrow flag.
1-carry out from MSB bit on addition or borrow into MSB bit on
subtraction
0-no carry out or borrow into MSB bit

Example:

MVI A 30 (load 30H in register A)

MVI B 40 (load 40H in register B)
SUB B (A = A – B)
These set of instructions will set the carry flag to 1 as 30 – 40
generates a carry/borrow.

MVI A 40 (load 40H in register A)

MVI B 30 (load 30H in register B)
SUB B (A = A – B)
These set of instructions will reset the sign flag to 0 as 40 – 30 does
not generate any carry/borrow.

flag 8086
Status Flag Registers:
1. Overflow Flag (OF):

Overflow Flag is set to 1 when there is a signed overflow. For

example, when you add bytes 100 + 50 (result is not in range -128…
127).

2. Sign Flag (SF):

Sign Flag is set to 1 when result is negative. When result is positive it

is set to 0. This flag takes the value of the most significant bit.

3. Zero Flag (ZF):

Zero Flag (ZF) is set to 1 when result is zero. For non-zero result this
flag is set to 0.
4. Auxiliary Flag (AF):

Auxiliary Flag is set to 1 when there is an unsigned overflow for low

nibble (4 bits).

5. Parity Flag (PF):

Parity Flag is set to 1 when there is even number of one bits in result,
and to 0 when there is odd number of one bits.

6. Carry Flag (CF);

Carry Flag is set to 1 when there is an unsigned overflow. For

example when you add bytes 255 + 1 (result is not in range 0…255).
When there is no overflow this flag is set to 0.

Control Flag Registers:

1. Direction Flag (DF):

Direction Flag is used by some instructions to process data chains,

when this flag is set to 0 – the processing is done forward, when this
flag is set to 1the processing is done backward.

2. Interrupt Enable Flag (IF):

When Interrupt Enable Flag is set to 1 CPU reacts to interrupts from

external devices.

3. Trap Flag (TF):

Trap Flag is used for on-chip debugging.

flag 8051
The two unused bits are user-defined flags. Four of the flags are
called conditional flags, which means that they indicate a condition
which results after an instruction is executed. These four are CY
(Carry), AC (auxiliary carry), P (parity), and OV (overflow)

 CY, the carry flag − This carry flag is set (1) whenever there is
a carry out from the D7 bit. It is affected after an 8-bit addition
or subtraction operation. It can also be reset to 1 or 0 directly by
an instruction such as "SETB C" and "CLR C" where "SETB"
stands for set bit carry and "CLR" stands for clear carry.
 AC, auxiliary carry flag − If there is a carry from D3 and D4
during an ADD or SUB operation, the AC bit is set; otherwise,
it is cleared. It is used for the instruction to perform binary
coded decimal arithmetic.
 P, the parity flag − The parity flag represents the number of 1's
in the accumulator register only. If the A register contains odd
number of 1's, then P = 1; and for even number of 1's, P = 0.
 OV, the overflow flag − This flag is set whenever the result of
a signed number operation is too large causing the high-order
bit to overflow into the sign bit. It is used only to detect errors
in signed arithmetic operations.