INSTRUCTION SYNTAX

General syntax for 8051 assembly language is as follows.

LABEL: OPCODE OPERAND ;COMMENT

LABEL : The Label is programmer chosen name for a Memory Location or a

statement in a program. The Label part of the statement is optional and if present,
the Label must be terminated with a Colon (:).
OPCODE: Opcode is the symbolic representation of the operation. The
assembler converts the opcode to a unique binary code or hex code(machine
language).

OPERAND: Operand specifies where to perform that action. The operand field
generally contains the source and destination of the data. In some cases only
source or destination will be available instead of both. The operand will be either
address of the data, or data itself.

COMMENT: Comments are statements included by the developer for easier

understanding of the code and is used for proper documentation of the Program.
Always comment will begin with ; or // symbol

ADDRESSING MODES
Various methods of accessing the data are called addressing modes. . 8051
addressing modes are classified as follows.

1. Immediate addressing.
 Register addressing.
2.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Indexed addressing.
1.Immediate addressing.
In this addressing mode the data is provided as a part of instruction itself. In other
words data immediately follows the instruction

Eg: MOV A, #99d -(Moves the value 99 into the accumulator (note this is 99
decimal since we used 99d).
ADD A, #83H -(add 83(hex no) with accumulator)
The # symbol tells the assembler that the immediate addressing mode is to be used
2 .Register addressing.
In this addressing mode the register will hold the data. One of the eight general
registers (R0 to R7) can be used and specified as the operand.

Eg. MOV A,R0 –Move contents of R0 register to accumulator

ADD A, R5 ; Adds register R5 to A (accumulator)

R0 – R7 will be selected from the current selection of register bank(by PSW). The
default register bank will be bank 0. One advantage of register addressing is that
the instructions tend to be short, single byte instructions
3.Direct addressing
This mode allows you to specify the operand by giving its actual memory
address (typically specified in hexadecimal format) or by giving its
abbreviated name (e.g. P3)
Eg: MOV A, P3 ;Transfer the contents of ;Port 3 to the accumulator
MOV A, 47H ;Transfer the contents of RAM ;location 27H to the
accumulator
4.Indirect addressing
This mode uses a pointer to hold the effective address of the operand .Only
registers R0, R1 and DPTR can be used as the pointer registers .The R0 and R1
registers can hold an 8-bit address, whereas DPTR can hold a 16-bit address. The
@ symbol indicated that the indirect addressing mode is used.

Eg: MOV A, @R0

R0 contains a value, for example 54h, which is to be used as the address of the
internal RAM location, which contains the operand data.
Indirect addressing refers to Internal RAM only and cannot be used to refer to SFR
registers

5.Relative addressing.

This mode of addressing is used with some type of jump instructions, like SJMP
(short jump) and conditional jumps like JNZ. These instructions transfer control
from one part of a program to another . The destination address must be within -
128 and +127 bytes from the current instruction address because an 8-bit offset is
used (2^8 = 256)
 6.Indexed Addressing.

Either the program counter, PC, or the data pointer DTPR(16 bit), is used as a base
address and the accumulator(8 bit) is used as an offset address. The effective
address is formed by adding the value from the base address to the value from the
offset address. The Indexed addressing is useful when there is a need to retrieve
data from a look-up table.
Eg:

MOVC is a move instruction, which moves data from the external code memory
space
MOV A,#08H ;Offset from table start

MOV DPTR,#01F00H ;Table start address

MOVC A,@A+DPTR ;Gets target value from the table ;start address + offset and
puts it ;in A

The DPTR value is referred to as the base address and the accumulator value us
referred to as the index address.
7.Long Addressing
The long addressing mode within the 8051 is used with the instructions LJMP and
LCALL. The address specifies a full 16 bit destination address so that a jump or a
call can be made to a location within a 64KByte code memory space (2^16 = 64K).
An example instruction is:
Eg:
LJMP 5000h ; full 16 bit address is specified in operand
8.Bit Inherent Addressing
In this addressing, the address of the flag which contains the operand, is
implied in the opcode of the instruction.
Eg:
CLR C ; Clears the carry flag to 0
9.Bit Direct Addressing
In this addressing mode the direct address of the bit is specified in the instruction.
The RAM space 20H to 2FH and most of the special function registers are bit
addressable
Eg:

CLR 07H ; Clears the bit 7 of 20H RAM space

SETB 07H ; Sets the bit 7 of 20H RAM space.

TYPES OF INSTRUCTIONS

The assembly level instructions include: data transfer instructions, arithmetic

instructions, logical instructions, program control instructions, and some special
instructions such as the rotate instructions

1.Data Transfer
Many computer operations are concerned with moving data from one location to
another. The 8051 uses five different types of instruction to move data:

• MOV
• MOVX
• MOVC
• PUSH and POP
• XCH

MOV

The MOV instruction is concerned with moving data internally, i.e. between
Internal RAM, SFR registers, general registers etc.MOV instruction having
following format.
MOV destination, source
The instruction copies (copy is a more accurate word than move) data from a
defined source location to a destination location.
Eg:

MOV R2, #80h ; Move immediate data value 80h to register R2

MOV R4, A ; Copy data from accumulator to register R4

MOV DPTR, #0F22Ch ; Move immediate value F22Ch to the DPTR register

MOV R2, 80h ; Copy data from 80h (Port 0 SFR) to R2

MOV 52h, #52h ; Copy immediate data value 52h to RAM location 52h

MOV 52h, 53h ; Copy data from RAM location 53h to RAM 52h
MOV A, @R0 ; Copy contents of location addressed in R0 to A (indirect
addressing)
MOVX

The 8051 the external memory can be addressed using indirect addressing only.

DPTR register is used to hold the address of the external data memory(RAM)
(since DPTR is a 16-bitregister it can address 64KByte locations: 2^16 = 64K).
The 8 bit registers R0 or R1 can also be used for indirect addressing of external
memory but the address range is limited to the lower 256 bytes of memory (2^8 =
256 bytes).
The MOVX instruction is used to access the external memory (X indicates
eXternal memory access). All external moves must work through the A register
(accumulator).
Eg:
MOVX @DPTR, A ; Copy data from A to the address specified in DPTR
MOVX A, @DPTR ; Copy data from address specified in DPTR to A

MOVC

The MOVC instruction is used to read data from the external code memory (ROM)

For this instruction indexed addressing mode is used(dptr-having base address and
accumulator having offset address)

Like the MOVX instruction all moves must be done through register A

The following sequence of instructions provides an example:

MOV DPTR, # 2000h ; Copy the data value 2000h to the DPTR register
MOV A, #80h ; Copy the data value 80h to register A
MOVC A, @A+DPTR ; Copy the contents of the address 2080h (2000h + 80h)
; to register A

PUSH and POP

PUSH and POP instructions are used with the stack only

Example for push and pop instruction

XCH

• The above “MOV” instructions copy data from a source location to a

destination location, leaving the source data unaffected.
• A special XCH (exchange) instruction will actually swap the data between
source and destination, effectively changing the source data.
• XCH instructions must use register A
• XCHD is a special case of the exchange instruction where just the lower
nibbles are exchanged
Examples using the XCH instruction are:

XCH A, R3 ; Exchange bytes between A and R3

XCH A, @R0 ; Exchange bytes between A and RAM location whose address is in
R0
XCH A, A0h ; Exchange bytes between A and RAM location A0h (SFR port 2)

XCHD A,@R1 :Exchange the lower order nibble of Accumulator (A0-A3) with
lower order nibble of the internal RAM location which is indirectly addressed by
the register R1

XCHD A,@R0 :Exchange the lower order nibble of Accumulator (A0-A3) with
lower order nibble of the internal RAM location which is indirectly addressed by
the register R1

2. ARITHMETIC

• Some key flags within the PSW, i.e. C, AC, OV, P, are utilized in many of
 the arithmetic instructions
• The arithmetic instructions can be grouped as follows
1. Addition
2. Subtraction
3. Increment/decrement
4. Multiply/divide
5. Decimal adjust
Addition

Register A (the accumulator) is used to hold the result of any addition operation.

Some simple addition examples are:

ADD A, #25h ; Adds the number 25h to A, putting sum in A

ADD A, R3 ; Adds the register R3 value to A, putting sum in A

The ADDC instruction is used to include the carry bit in the addition process

ADDC A, #55h ; Add contents of A, the number 55h, the carry bit; and put the
sum in A

ADDC A, R4 ; Add the contents of A, the register R4, the carry bit; and put
the sum in A

Subtraction
• Computer subtraction can be achieved using 2’s complement arithmetic
• The accumulator, register A, will contain the result (difference) of the
subtraction
Operation
• The C (carry) flag is treated as a borrow flag
• Some examples of subtraction instructions are:
SUBB A, #55d ; Subtract the number 55 (decimal) and the C flag from A; and put
the result in A.

SUBB A, R6 ; Subtract R6 the C flag from A; and put the result in A.

SUBB A, 58h ; Subtract the number in RAM location 58h and the C flag
From A; and put the result in A.

INCREMENT/DECREMENT
 • The increment (INC) instruction has the effect of simply adding a binary 1 to
a number
• Decrement (DEC) instruction has the effect of subtracting a binary 1from a
number
• The increment and decrement instructions can use the addressing modes:
direct, indirect and register
• The flags C, AC, and OV are not affected by the increment or decrement
instructions
• If a value of FFh is increment it overflows to 00h
• If a value of 00h is decrement it underflows to FFh
• The DPTR register cannot be decremented using a DEC instruction
Eg:

INC R7 ; Increment register R7

INC A ; Increment A
INC @R1 ; Increment the number which is the content of the address in R1
DEC A ; Decrement register A
DEC 43h ; Decrement the number in RAM address 43h
INC DPTR ; Increment the DPTR register

Multiply / Divide

• The 8051 supports 8-bit multiplication and division

• For the MUL or DIV instructions the A and B registers must be used and
only unsigned numbers are supported
• The MUL instruction is used as follows (note absence of a comma between
the A and B operands):

MUL AB ; Multiply A by B.
• The resulting product resides in registers A and B, the low-order byte is in A
and the high order byte is in B.
• DIV AB ; A is divided by B.
• The remainder is put in register B and the integer part of the quotient is put
in register A.

Decimal Adjust (Special)

• The 8051 performs all arithmetic in binary numbers (i.e. it does not support
BCD arithmetic)
• If two BCD numbers are added then the result can be adjusted by using the
 DA, decimal adjust, instruction
• DA A ; Decimal adjust A following the addition of two BCD numbers

LOGICAL

The following Boolean operations can operate on byte level or bit level data

• ANL Logical AND

• ORL Logical OR
• CPL Complement (logical NOT)
• XRL Logical XOR (exclusive OR)

Logical operations at the BYTE level

• The destination address of the operation can be the accumulator (register A),
a general register, or a direct address.
• Flags are not affected by these logical operations

ANL A, #55h ; AND each bit in A with corresponding bit in number 55h, leaving
the result in A.

ANL 42h, R4 ; AND each bit in RAM location 42h with corresponding bit in R4,
leaving the result in RAM location 42h.

ORL A,@R1 ; OR each bit in A with corresponding bit in the number whose
address is contained in R1 leaving the result in A.

XRL R4, 80h ; XOR each bit in R4 with corresponding bit in RAM location 80h
(port 0), leaving result in A.

CPL R0 ; Complement each bit in R0

Logical operations at the BIT level

• The C (carry) flag is the destination of most bit level logical operations
• The following SFR registers only are addressable in bit level operations
PSW ,IE, IP, TCON ,SCON

Examples of bit level logical operations are as follows:

SETB 2Fh ; Bit 7 of Internal RAM location 25h is set

CLR C ; Clear the carry flag (flag =0)

CPL 20h ; Complement bit 0 of Internal RAM location 24h

MOV C, 87h ; Move to carry flag the bit 7of Port 0 (SFR at 80h)

ANL C,90h ; AND C with the bit 0 of Port 1 (SFR at 90)

ORL C, 91h ; OR C with the bit 1 of Port 1 (SFR at 90)

ROTATE INSTRUCTIONS

The ability to rotate the A register (accumulator) data is useful to allow

examination of individual bits

1) RL A ; Rotate A one bit to the left. Bit 7 rotates to the bit 0 position

2) RLC A ; The Carry flag is used as a ninth bit in the rotation loop

3) RR A ; Rotates A to the right (clockwise)

 4) RRC A ; Rotates to the right and includes the carry bit as the 9th bit.

5) SWAP A ; The Swap instruction swaps the accumulator’s high order

nibble with the low-order nibble using the instruction

PROGRAM CONTROL INSTRUCTIONS

The 8051 supports three kind of jump instructions: LJMP SJMP AJMP

LJMP

• LJMP (long jump) causes the program to branch to a destination address

defined by the 16-bit operand in the jump instruction
 • Because a 16-bit address is used the instruction can cause a jump to any
location within the 64KByte program space (2^16 = 64K).
Eg:

LJMP LABEL_X ; Jump to the specified label

LJMP 0F200h ; Jump to address 0F200h

LJMP @A+DPTR ; Jump to address which is the sum of DPTR and Reg. A

SJMP

• SJMP (short jump) uses a singe byte address.

• This address is a signed 8-bit number and allows the program to branch to a
distance –128 bytes back from the current PC address or +127 bytes forward
from the current PC address.
• The address mode used with this form of jumping (or branching) is referred
to as relative addressing,
• The jump is calculated relative to the current PC address

SJMP <relative address>; this is unconditional jump

AJMP

• This is a special 8051 jump instruction, which allows a jump with a 2KByte
address boundary (a 2K page)
• In this case only 11bits of the absolute jump address are needed
• The absolute jump address is calculated in the following manner.
1. In 8051, 64 kbyte of program memory space is divided into 32 pages of 2
kbyte each
2. The hexadecimal addresses of the pages are given as follows
 • It can be seen that the upper 5bits of the program counter (PC) hold the page
number and the lower 11bits of the PC hold the address within that page

SUBROUTINES AND PROGRAM FLOW CONTROL

A subroutine(Subroutine is a group of instructions Written separately from the

main program to perform a function that occurs repeatedly in the main program) is
called using the LCALL or the ACALL instruction

LCALL
• This instruction is used to call a subroutine at a specified address.
• The address is 16 bits long so the call can be made to any location within the
64KByte memory space.
• When a LCALL instruction is executed the current PC content is
automatically
pushed onto the stack of the PC.
• When the program returns from the subroutine the PC contents is returned
from the stack so that the program can resume operation from the point
where the LCALL was made
• The return from subroutine is achieved using the RET instruction, which
simply pops the PC back from the stack.

ACALL(11 bit-2 Byte instruction)

 • The ACALL instruction is logically similar to the LCALL but has a limited
address range similar to the AJMP instruction
• CALL is a generic call instruction supported by many 8051 assemblers.
• The assembler will decide which type of call instruction, LCALL or
ACALL, to use so as to choose the most efficient instruction

PROGRAM CONTROL USING CONDITIONAL JUMPS

When using a conditional jump instruction the programmer can simply specify a
program label or a full 16-bit address for the conditional jump instruction’s
destination

Eg:

JZ LABEL_1 ; Jump to LABEL_1 if accumulator is equal to zero

JNZ LABEL_X ; Jump to LABEL_X if accumulator is not equal to zero

JNC LABEL_Y ; Jump to LABEL_Y if the carry flag is not set

DJNZ R2, LABEL ; Decrement R2 and jump to LABEL if the resulting value of
R2 is not zero.

CJNE R1, #55h , LABEL_2 ; Compare the magnitude of R1 and the number 55h
and jump to LABEL_2 if the magnitudes are not equal.

ASSEMBLER DIRECTIVES

• Assembler directives tell the assembler to do something other than creating

the machine code for an instruction.
• Do not generate any code that is machine executable
• In assembly language programming, the assembler directives instruct the
assembler to
1. Process subsequent assembly language instructions
2. Define program constants

3. Reserve space for variables

The following are the widely used 8051 assembler directives.

1.ORG (origin)

• The ORG directive is used to indicate the starting address

• The number that comes after ORG can be either in hex or in decimal.
Eg: ORG 0000H ;Set PC to 0000.
2.EQU
• Assigns numerical value to a symbol or name(when that symbol or name
used multiple times in program)
• Eg: pi EQU 22/7(pi=22/7)
3.END

• It indicates the end of the program to the assembler.

• Any text in the assembly file that appears after the END directive is ignored.
• If the END statement is missing, the assembler will generate an error
message.

TIME DELAY GENARATION AND CALCULATION

Machine cycle:

The CPU takes a certain number of clock cycles to execute an instruction. These
clock cycles are referred to as machine cycles.

The length of the machine cycle depends on the frequency of the crystal oscillator
connected to the 8051 system.

In the 8051, one machine cycle lasts 12 oscillator periods

Time period for one machine cycle=12/(f crystal)

Eg:For fcrystal=11.0592 MHZ

1 machine cycle =12/(11.0592*10^6)=1.085 u seconds.

Software Delay sub Routines
The delay can can be generated by Timers and software delay sub routines

For getting on millisecond delay we requires at least 1000 machine cycles (since 1
cycle is 1 micro second)

Time delay of any magnitude can be generated by looping suitable instructions a

required number of times

software delay is not very accurate because we cannot exactly predict how much
time its takes for executing a single instruction

Delay generated by Timers used for critical applications and Software delay used
for simple applications

Program to delay 1mS.

DELAY: MOV R6,#250D -(1 machine cycle)

MOV R7,#250D -(1 machine cycle)
LABEL1: DJNZ R6,LABEL1 -(2 machine cycle)
LABEL2: DJNZ R7,LABEL2 -(2 machine cycle)
RET -(1 machine cycle)
Explanation:

• The instruction DJNZ Rx,LABEL is a two cycle instruction and it will take
2µS to execute
• So repeating this instruction 500 times will generate a delay of 500 x 2µS =
1mS
• First Registers R6 and R7 are loaded by 250d
• Then DJNZ R6,LABEL1 is executed until R6 becomes zero and then DJNZ
R7,LABEL2 is executed until R7 is zero
• This creates a loop of DJNZ Rx(RX- means R7 and R6
here)LABEL repeating 500 times and the result will be a 1mS delay

DJNZ R6,LABEL1:(decrement R6 and if it is nonzero then jump to LABEL1)

Program to delay 1 second

 • In this program subroutine for delaying 1mS (DELAY) is called 4 times
back to back and the entire cycle is repeated 250 times.

• As result, a delay of 4 x 1mS x 250 = 1000mS = 1 second is produced

DELAY1: MOV R5,#250D

LABEL: ACALL DELAY

ACALL DELAY

ACALL DELAY

ACALL DELAY

DJNZ R5,LABEL

RET

DELAY: MOV R6,#250D

MOV R7,#250D

LOOP1: DJNZ R6,LOOP1

LOOP2: DJNZ R7,LOOP1

RET
8-bit TIMER OPERATION

• 12MHZ clock frequency internally divided by 12

• So 1 MHZ frequency reaches timer/counter input

• An eight bit timer can produce a delay of 255 microseconds.

• The eight bit counter will count events, up to 255 events

• timer will count internal time pulses and counter will count external pulses,

HOW DO WE PROGRAM THE 8-BIT TIMER/COUNTER

1. Configure the Timer/Counter as a TIMER or as a COUNTER(C/T bit in TMOD register)

2. Load the TMOD value register indicating which timer (timer 0 or timer 1) is to be used
and which timer mode (0 or 1) is selected
3. Load registers TL and TH with initial count value
4. Start the timer(TR0/TR1 set to high)
5. Keep monitoring the timer flag (TF1/TF0) with the JNB TFx,target instruction to see if it
is raised ƒ Get out of the loop when TF becomes high
6. Stop the timer(Clear TR0/TR1)
7. Clear the TF1/TF0 flag for the next round
Eg:

To run in TIMER mode using 8-bit operation(mode 2), the TMOD register is initialised as
Follows

MOV TMOD, #00100000b ; assume timer 1 considered

PROGRAMMING
1)Write a program to add the values of locations 50H and 51H and store the result
in locations in 52h and 53H.

PGM

ORG 0000H ; Set program counter 0000H(Starting address of program)

MOV A,50H ; Load the contents of Memory location 50H into A
ADD A,51H ; Add the contents of memory 51H with contents A
MOV 52H,A ; Save the 8 bits of the result in 52H
MOV A, #00 ; Load 00H into A
ADDC A, #00 ; Add the immediate data and carry to A
MOV 53H,A ; Save the MS byte of the result in location 53h
END

OR

ORG 0000H ; Set program counter 0000H(Starting address of program)

MOV A,50H ; Load the contents of Memory location 50H into A
ADD A,51H ; Add the contents of memory 51H with contents A
MOV 52H,A ; Save the 8 bits of the result in 52H
MOV R0,#00H; Move 00 to R0 register
JNC Label 1;Jump to Label 1 address if carry is 0
INC R0
Label1:MOV 53H,R0;Move contents of R0 to 53H
END

2)Write a program to add two 8 bit numbers stored in memory location 2400H and
2401H.Store the result in 2402H and 2403H.

PGM

ORG 0000H
MOV DPTR,#2400H;16 bit Address location 2400 H loaded in DPTR
MOVX A,@DPTR; Move contents of address location 2400H to accumulator
MOV R0,A;Move the contents of accumulator to R0
INC DPTR; Increment The value in DPTR(now DPTR-2401H)
MOVX A,@DPTR; Move contents of address pointed by DPTR(2401H) to A
ADD A,R0;Add contents of R0 and A ,store the 8 bit result in A
INC DPTR; Increment The value in DPTR(now DPTR-2402H)
MOVX @DPTR,A;Move contents of A to address pointed by DPTR(2402H)
INC DPTR; Increment The value in DPTR(now DPTR-2403H)
MOV R1,#00H;Move the value 00H to R1 register
JNC LABEL1;Jump to LABEL1 if carry=0
INC R1;Increment the value in R1(now R1=01H)
LABEL1:MOV A,R1;Move contents of R1 to A
MOVX @DPTR,A; Move contents of A to address pointed by DPTR(2403H)
END
3)

PGM

ORG 0000H
MOV DPTR,#2400H;16 bit Address location 2400 H loaded in DPTR
MOVX A,@DPTR; Move contents of address location 2400H to accumulator
MOV R0,A;Move contents of A to register R0
INC DPTR; Increment DPTR(Now DPTR=2401)
MOVX A,@DPTR; Move contents of address (2401H) pointed by DPTR to A
CLR C; Clear Carry flag(borrow for subtraction)
SUBB A,R0;Subtract R0 and carry(borrow if any)from A ,and store result in A
INC DPTR; Increment DPTR(now DPTR=2402)
MOVX @DPTR,A; Move contents of address pointed by DPTR(2402H) to A
INC DPTR; Increment DPTR(now DPTR=2403 H)
MOV R1,#00H; Move the value 00H to R1 register
JNC LABEL1; Jump to LABEL1 if carry=0
INC R1;Increment the value in R1(Now R1-01H)
INC DPTR; Increment DPTR(Now DPTR-2404H)
LABEL 1:MOV A,R1;Move contents of R1 to A
MOVX @DPTR,A; contents of A to address pointed by DPTR(2404H)
END

4)Write a program to find the smallest number of an array of 8 bit numbers. Let the
length of array is stored in the location 2400H and the array begins from the
location 2401H.Store the result in the location 2450H.

ORG 0000H ;Set origin address

MOV DPTR,#2400H;Load the value 2400H to DPTR
MOVX A,@DPTR; Move the contents of location pointed by DPTR(2400H )to A
MOV R0,A;Move contents of A to R0.
INC DPTR; Increment DPTR(2401H)
DEC R0;Decrement R0
MOVX A,@DPTR; Move the contents of location pointed by DPTR(2401H )to A
MOV R1,A; Move contents of A to R1.
LABEL 2:INC DPTR; Increment DPTR(2402H)
MOVX A,@DPTR; Move the contents of location pointed by DPTR(2402H )to A
MOV R2,A; Move contents of A to R2.
CLR C; Clear Carry flag
SUBB A,R1;Subtract R1,Carry from A and store the result in A
JNC LABEL1;jump to LABEL 1 if carry =0
MOV A,R2;Move contents of R2 to A.
MOV R1,A;Move contents of A to R1.
LABEL1:DJNZ R0,LABEL 2;Decrement R0 ,and jump to LABEL 2 if R0 is not 0
MOV A,R1:Move contents of R1 to A
MOV DPTR,#2450H;Load the value 2450H to DPTR.
MOVX @DPTR,A; contents of A to address pointed by DPTR
END

PGM
ORG 0000H;
MOV A,#08H;
CLR C;
SUBB A,#06H;
MOV 0F0H,#02H;
MUL A,B;
DIV A,B;
ADD A,R0
MOV DPTR,#8200H;
MOVX @DPTR,A;
END

ORG 0000H
MOV R0,#05;
MOV R2,08H;
MOV R1,R2;
DEC R0;
K1:INC R1;
MOV A,R2;
CLR C;
SUBB A,R1;
JNC K2;
MOV R2,R1;
K2:DJNZ R0,K1;
MOV A,R2;
MOV DPTR,#8500H;
MOVX @DPTR,A;
END

1 st instruction Carry=1
2 nd instruction dptr=8200h
3rd instruction a=3Fh(data in location 8200h)
4th instruction a=(cy+a+08h)=(1+3F+08)=48H(bynary-01001000)
5th instruction rotate left accumulator,Bit 7 rotates to the bit 0 position
a=01001000 changes to a=10010000(90h)