UNIT 1

8051Microcontroller
Assembly language
Programming

Dr.L.Suganthi
 Introduction
• An instruction is an order or command given to a
processor by a computer program.
• All commands are known as instruction set and
set of instructions is known as program.
• As the 8051 family of Microcontrollers are 8-bit
processors, the 8051 Microcontroller Instruction
Set is optimized for 8-bit control applications.
• As a typical 8-bit processor, the 8051
Microcontroller instructions have 8-bit Opcodes.
As a result, the 8051 Microcontroller instruction
set can have up to 28 = 256 Instructions.
• 8051 have in total 111 instructions, i.e. 111
different words available for program writing.
 Instruction Format

• Where first part describes WHAT should be

done, while other explains HOW to do it.

• The latter part can be a data (binary

number) or the address at which the data
is stored.

• Depending upon the number of bytes

required to represent 1 instruction
completely.
 Types of Instructions
• Instructions are divided into 3 types;

1. One/single byte instruction.

2. Two/double byte instruction.

3. Three/triple byte instruction.

 Types of Instructions
1. One/single byte instructions :

• If operand is not given in the instruction or

there is no digits present with instruction, the
instructions can be completely represented in
one byte opcode.

• OPCODE 8 bit

• Eg: CLC
 Types of Instructions

2. Two/double byte instruction:

• If 8 bit number is given as operand in the

instruction, the such instructions can be
completed represented in two bytes.

• First byte OPCODE

• Second byte 8 bit data or I/O port
Eg: Mov R2,#50h
 Types of Instructions

3. Three/triple byte instruction:

• If 16 bit number is given as operand in the

instructions than such instructions can be
completely represented in three bytes 16 bit
number specified may be data or address.
• Eg: Mov DPTR,#9800h
 Types of Instructions

1. First byte will be instruction code.

2. Second byte will be 8 LSB’s of 16 bit number.
3. Third byte will be 8 MSB’s of 16 bit number.

• First byte OPCODE.

• Second byte 8 LSB’s of data/address.
• Third byte 8 MSB’S of data/address.
 Addressing Modes
• Addressing modes specifies where the data
(operand) is. They specify the source or
destination of data (operand) in several different
ways, depending upon the situation.

• Addressing modes are used to know where the

operand located is.
 Immediate Addressing Mode
• In immediate addressing mode, the data is given
with the instruction itself.

• In this case; the data to be stored in memory

immediately follows the opcode.
 Immediate Addressing Mode
• In Immediate Addressing mode, the operand, which follows the
Opcode, is a constant data of either 8 or 16 bits. The name
Immediate Addressing came from the fact that the constant
data to be stored in the memory immediately follows the
Opcode.

• The constant value to be stored is specified in the instruction

itself rather than taking from a register. The destination register
to which the constant data must be copied should be the same
size as the operand mentioned in the instruction.

Example: MOV A, #030H

• Here, the Accumulator is loaded with 30 (hexadecimal). The #
in the operand indicates that it is a data and not the address of
a Register.
• Immediate Addressing is very fast as the data to be loaded is
given in the instruction itself.
 Immediate Addressing Mode -
Examples
Immediate Mode – specify data by its value

mov A, #0 ;put 0 in the accumulator

;A = 00000000
mov R4, #11h ;put 11hex in the R4 register
;R4 = 00010001
mov B, #11 ;put 11 decimal in b register
;B = 00001011
mov DPTR,#7521h ;put 7521 hex in DPTR
;DPTR = 0111010100100001
 8051 Instruction Format

• immediate addressing

Op code Immediate data

add a,#3dh ;machine code=243d
 Register Addressing Mode
• In register addressing mode; the source and/or
destination is a register.

• In this case; data is placed in any of the 8

registers(R0-R7); in instructions it is specified
with letter Rn (where N indicates 0 to 7).
 Register Addressing Mode
• In the 8051 Microcontroller Memory Organization,
we have seen the organization of RAM and four
banks of Working Registers with eight Registers in
each bank.
• In Register Addressing mode, one of the eight
registers (R0 – R7) is specified as Operand in the
Instruction.
• It is important to select the appropriate Bank with
the help of PSW Register. Let us see a example of
Register Addressing assuming that Bank 0 is
selected.
Example: MOV A, R5
• Here, the 8-bit content of the Register R5 of Bank 0
is moved to the Accumulator.
 Register Addressing Mode
• For example;

1. ADD A, Rn (This is general instruction).

2. ADD A, R5 (This instruction will add the contents

of register R5 with the accumulator contents).
 Register Addressing Mode -
Examples
Register Addressing – either source or destination is
one of CPU register
MOV R0,A
MOV A,R7
ADD A,R4
ADD A,R7
MOV DPTR,#25F5H
MOV R5,DPL
MOV R,DPH

Note that MOV R4,R7 is incorrect

 Register addressing
Instruction Format
Op code n n n
070D E8 mov a,r0 ;E8 = 1110 1000
070E E9 mov a,r1 ;E9 = 1110 1001
070F EA mov a,r2 ;EA = 1110 1010
0710 ED mov a,r5 ;ED = 1110 1101
0711 EF mov a,r7 ;Ef = 1110 1111
0712 2F add a,r7
0713 F8 mov r0,a
0714 F9 mov r1,a
0715 FA mov r2,a
0716 FD mov r5,a
0717 FD mov r5,a
 Direct Addressing Mode
• In direct addressing mode; the address of
memory location containing data to be read is
specified in instruction.
• In this case; address of the data is given with the
instruction itself.
• In Direct Addressing Mode, the address of the
data is specified as the Operand in the instruction.
Using Direct Addressing Mode, we can access any
register or on-chip variable. This includes general
purpose RAM, SFRs, I/O Ports, Control registers.
• Example: MOV A, 47H
• Here, the data in the RAM location 47H is moved
to the Accumulator.
 Direct Addressing Mode -
Examples
Direct Mode – specify data by its 8-bit address
Usually for 30h-7Fh of RAM
Mov a, 70h ; copy contents of RAM at 70h to a
Mov R0,40h ; copy contents of RAM at 70h to a
Mov 56h,a ; put contents of a at 56h to a
Mov 0D0h,a ; put contents of a into PSW

Play with R0-R7 by direct address

MOV A,4  MOV A,R4
MOV A,7  MOV A,R7
MOV 7,2  MOV R7,R6

MOV R2,#5 ;Put 5 in R2

MOV R2,5 ;Put content of RAM at 5 in R2
 Direct addressing
Instruction Format

mov r3,0E8h ;machine code=ABE8

Op code Direct address

 Register Indirect Addressing
Mode
• In register indirect addressing mode; the contents
of the designated register are used as a pointer to
memory.

• In this case; data is placed in memory, but

address of memory location is not given directly
with instruction.
 Register Indirect Addressing

Example: MOV A, @R1

• The @ symbol indicates that the addressing mode
is indirect. If the contents of R1 is 56H, for
example, then the operand is in the internal RAM
location 56H. If the contents of the RAM location
56H is 24H, then 24H is moved into accumulator.
• Only R0 and R1 are allowed in Indirect Addressing
Mode. These register in the indirect addressing
mode are called as Pointer registers.
 Register Indirect Addressing-
Examples
Register Indirect – the address of the source or
destination is specified in registers
Uses registers R0 or R1 for 8-bit address:
mov psw, #0 ; use register bank 0
mov r0, #0x3C
mov @r0, #3 ; memory at 3C gets #3
; M[3C]  3
Uses DPTR register for 16-bit addresses:
mov dptr, #0x9000 ; dptr  9000h
movx a, @dptr ; a  M[9000]

Note that 9000 is an address in external memory

Register Indirect Addressing
Mode
Write a program to copy the value 55H into RAM
memory locations 40H to 41H using (a) direct
addressing mode, (b) register indirect addressing
mode without a loop, and (c) with a loop.

28
 Register Indirect Addressing
Mode
• The advantage is that it makes accessing data dynamic
rather than static as in direct addressing mode.
• Looping is not possible in direct addressing
mode.
Write a program to clear 16 RAM locations starting
at RAM address 60H.

29
Register indirect addressing
Instruction Format
Op code i

mov a, @Ri ; i = 0 or 1

070D E7 mov a,@r1

070D 93 movc a,@a+dptr
070E 83 movc a,@a+pc
070F E0 movx a,@dptr
0710 F0 movx @dptr,a
0711 F2 movx @r0,a
0712 E3 movx a,@r1
 Index Addressing Mode
• With Indexed Addressing Mode, the effective address of
the Operand is the sum of a base register and an offset
register
• In this case; this mode is made for reading tables in the
program memory. Indexed Addressing Mode
• The Base Register can be either Data Pointer (DPTR) or
Program Counter (PC) while the Offset register is the
Accumulator (A).
• In Indexed Addressing Mode, only MOVC and JMP
instructions can be used. Indexed Addressing Mode is
useful when retrieving data from look-up tables.

• Example: MOVC A, @A+DPTR

• Here, the address for the operand is the sum of contents
of DPTR and Accumulator.
Index Addressing Mode-Example
 Relative Addressing

• This mode of addressing is used with some type of

jump instructions, like SJMP (short jump) and
conditional jumps like JNZ

• These instructions transfer control from one part

of a program to another

• The destination address must be within -128 and

+127 bytes from the current instruction address
because an 8-bit offset is used (28 = 256).
 Relative Addressing
• The Relative Addressing mode is used with some
type of jump instructions like SJMP (short jump)
and conditional jumps like JNZ. This instruction
transfers control from one part of a program to
another
• Example:
 Absolute Addressing

• Two instructions associated with this mode of

addressing are ACALL and AJMP instructions

• These are 2-byte instructions where the 11-bit

absolute address is specified as the operand

• The upper 5 bits of the 16-bit PC address are not

modified. The lower 11 bits are loaded from this
instruction. So, the branch address must be within
the current 2K byte page of program memory
(211 = 2048)
 Absolute Addressing

In Absolute Addressing mode, the absolute address,

to which the control is transferred, is specified by a
label. Two instructions associated with this mode of
addressing are ACALL and AJMP instructions.
These are 2-byte instructions.

Example:
 Long Addressing
• This mode of addressing is used with the LCALL
and LJMP instructions
• It is a 3-byte instruction and the last 2 bytes
specify a 16-bit destination location where the
program branches
• It allows use of the full 64 K code space
• The program will always branch to the same
location no matter where the program was
previously
• This mode of addressing is used with the LCALL
and LJMP instructions. It is a 3-byte instruction
and the last 2 bytes specify a 16-bit destination
location where the program branches to. It allows
use of the full 64K code space
 Long Addressing

• This mode of addressing is used with the LCALL

and LJMP instructions.
• It is a 3-byte instruction and the last 2 bytes
specify a 16-bit destination location where the
program branches to.
• It allows use of the full 64K code space

Example:
 Acc Register Address
• A register can be accessed by direct and register
mode

• This 3 instruction has same function with different

code
0703 E500 mov a,00h
0705 8500E0 mov acc,00h
0708 8500E0 mov 0e0h,00h

• Also this 3 instruction

070B E9 mov a,r1
070C 89E0 mov acc,r1
070E 89E0 mov 0e0h,r1
 SFRs Address
• B – always direct mode - except in MUL & DIV
0703 8500F0 mov b,00h
0706 8500F0 mov 0f0h,00h
0709 8CF0 mov b,r4
070B 8CF0 mov 0f0h,r4

• P0~P3 – are direct address

0704 F580 mov p0,a
0706 F580 mov 80h,a
0708 859080 mov p0,p1

• Also other SFRs (pcon, tmod, psw,….)

 SFRs Address

All SFRs such as

(ACC, B, PCON, TMOD, PSW, P0~P3, …)
are accessible by name and direct
address But both of them
Must be coded as direct address.
 Types of Instructions
Depending on operation they
perform

1. Data transfer instructions.

2. Arithmetic instructions.
3. Logical instructions.
4. Logical instructions with bits.
5. Branch instructions.
Types of Instructions
 Data Transfer Instructions
• MOV dest, source dest  source

• Stack instructions
PUSH byte ;increment stack pointer,
;move byte on stack
POP byte ;move from stack to byte,
;decrement stack pointer

• Exchange instructions
XCH a, byte ;exchange accumulator and byte
XCHD a, byte ;exchange low nibbles of
;accumulator and byte
 Data Transfer Instructions
 MOV <destination>, <source>: allows data to be
transferred between any two internal RAM or SFR
locations
Data Transfer Instructions
-MOV
Data Transfer Instructions
-MOV
 Data Transfer Instructions
 Instruction XCH A, <source> causes the
accumulator and the address byte to exchange
data
 Instruction XCHD A, @Ri causes the low-order
nibbles to be exchanged.

 Example: if A contains F3H, R1 contains 40H, and

internal RAM address 40H contains 5BH,
instruction XCHD A, @R1 leaves A containing
FBH and internal RAM location 40H containing
53H.
 Data Transfer Instructions
-Stack
 Stack operations (pushing and popping data) are also
internal data transfer instructions
 Pushing increments SP before writing the data
 Popping from the stack reads the data and decrements
the SP
 8051 stack is kept in the internal RAM
Example: stack pointer contains 07H and A contains 55H and B
contains 4AH. What internal RAM locations are altered and
what are their new values after the following instructions?
PUSH ACC PUSH F0H
Answer: address 08H will have 55H, address 09H will have
4AH and address 81H (SP) will have 09H.
Data Transfer Instructions
-Stack

pop
push

stack pointer

stack

Go do the stack exercise…..

 Data Transfer Instructions
-Stack
• Stack-oriented data transfer
– Only one operand (direct addressing)
– SP is other operand – register indirect - implied
• Direct addressing mode must be used in Push and
Pop

mov sp, #0x40 ; Initialize SP

push 0x55 ; SP  SP+1, M[SP]  M[55]
; M[41]  M[55]
pop b ; b  M[55]

Note: can only specify RAM or SFRs (direct mode) to

push or pop. Therefore, to push/pop the accumulator,
must use acc, not a
 Data Transfer Instructions
-Stack
• Therefore
(push,pop)
Push a ;is invalid
Push r0 ;is invalid
Push r1 ;is invalid
push acc ;is correct
Push psw ;is correct
Push b ;is correct
Push 13h
Push 0
Push 1
Pop 7
Pop 8
Push 0e0h ;acc
Pop 0f0h ;b
Pushing onto Stack
Pushing onto Stack
Popping from Stack

55
 Exchange Instructions

Two way data transfer

XCH a, 30h ; a  M[30]
XCH a, R0 ; a  R0
XCH a, @R0 ; a  M[R0]

XCHD a, R0 ; exchange “digit”

a[7..4] a[3..0] R0[7..4] R0[3..0]

Only 4 bits exchanged

 Bit-Oriented Data Transfer
• Transfers between individual bits.
• Carry flag (C) (bit 7 in the PSW) is used as a
single-bit accumulator
• RAM bits in addresses 20-2F are bit addressable
mov C, P0.0
mov C, 67h
mov C, 2ch.7
Data Processing Instructions

Arithmetic Instructions
Logic Instructions
 Arithmetic Instructions

• Add
• Subtract
• Increment
• Decrement
• Multiply
• Divide
• Decimal adjust
 Arithmetic Instructions
Mnemonic Description
ADD A, byte add A to byte, put result in A
ADDC A, byte add with carry
SUBB A, byte subtract with borrow
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte
MUL AB multiply accumulator by b register
DIV AB divide accumulator by b register
DA A decimal adjust the accumulator
 ADD Instructions

add a, byte ; a  a + byte

addc a, byte ; a  a + byte + C

These instructions affect 3 bits in PSW:

C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not from bit 6,
or visa versa.
Instructions that Affect PSW
bits
 ADD Examples

mov a, #3Fh • What is the value of

add a, #D3h the C, AC, OV flags
after the second
instruction is
0011 1111 executed?
1101 0011
0001 0010
C = 1
AC = 1
OV = 0
 Addition Examples
; Computes Z = X + Y
; Adds values at locations 78h and 79h and puts them in 7Ah
;------------------------------------------------------------------
X equ 78h
Y equ 79h
Z equ 7Ah
;-----------------------------------------------------------------
org 00h
ljmp Main
;-----------------------------------------------------------------
org 100h
Main:
mov a, X
add a, Y
mov Z, a
end
ADD Instruction and PSW

65
The 16-bit ADD example
BCD Number System
BCD Number System
DA Instruction
DA Instruction
 Subtract Instruction

SUBB A, byte subtract with borrow

Example:
SUBB A, #0x4F ;A  A – 4F – C

Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.

Example:
Clr c
SUBB A, #0x4F ;A  A – 4F
Subtract Instruction
Subtract Instruction
 Increment and Decrement
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte

• The increment and decrement instructions do NOT affect

the C flag.
• Notice we can only INCREMENT the data pointer, not
decrement.
 Multiplication of Unsigned
Numbers
MUL AB ; A  B, place 16-bit result in B and A

MOV A,#25H ;load 25H to reg. A

MOV B,#65H ;load 65H in reg. B
MUL AB ;25H * 65H = E99 where B = 0EH and A =
99H
Table :Unsigned Multiplication Summary (MUL AB)

Multiplication Operand 1 Operand 2 Result

byte  byte A B A=low byte,

B=high byte

75
 Multiplication of Unsigned
Numbers
When multiplying two 8-bit numbers, the size of the
maximum product is 16-bits

FF x FF = FE01
(255 x 255 = 65025)
 Division of Unsigned Numbers
DIV AB ; divide A by B
• MOV A,#95H ;load 95 into A
• MOV B,#10H ;load 10 into B
• DIV AB ;now A = 09 (quotient) and B = 05
(remainder)
Table :Unsigned Division Summary (DIV AB)
Division Numerator Denominator Quotient Remainder
byte / byte A B A B

OV - used to indicate a divide by

zero condition.
C – set to zero
77
 Logic Instructions

 Bitwise logic operations

 (AND, OR, XOR, NOT)
 Clear
 Rotate
 Swap

Logic instructions do NOT affect the flags in PSW

 Bitwise Logic

Examples:
ANL  AND 00001111
ORL  OR ANL 10101100
00001100
XRL  XOR
CPL  Complement 00001111
ORL 10101100
10101111

00001111
XRL 10101100
10100011

CPL 10101100
01010011
 Uses of Logic Instructions

• Force individual bits low, without affecting other

bits.
anl PSW, #0xE7 ;PSW AND 11100111

• Force individual bits high.

orl PSW, #0x18 ;PSW OR 00011000

• Complement individual bits

xrl P1, #0x40 ;P1 XRL 01000000
 Other Logic Instructions

CLR - clear
RL – rotate left
RLC – rotate left through Carry
RR – rotate right
RRC – rotate right through Carry
SWAP – swap accumulator nibbles
 CLR ( Set all bits to 0)

CLR A
CLR byte (direct mode)
CLR Ri (register mode)
CLR @Ri (register indirect mode)
 Rotate
• Rotate instructions operate only on a

RL a

Mov a,#0xF0 ; a 11110000

RR a ; a 11100001

RR a

Mov a,#0xF0 ; a 11110000

RR a ; a 01111000
 Rotate through Carry
C
RRC a

mov a, #0A9h ; a  A9
add a, #14h ; a  BD (10111101), C0
rrc a ; a  01011110, C1

RLC a
C

mov a, #3ch ; a  3ch(00111100)

setb c ; c  1
rlc a ; a  01111001, C1
 Rotate and
Multiplication/Division
• Note that a shift left is the same as multiplying by
2, shift right is divide by 2

mov a, #3 ; A 00000011 (3)

clr C ; C 0
rlc a ; A 00000110 (6)
rlc a ; A 00001100 (12)
rrc a ; A 00000110 (6)
 Swap Instruction

SWAP a

mov a, #72h; a  72h

swap a ; a  27h
Example-Swap Instruction
 Bit Logic Operations

• Some logic operations can be used with single bit

operands

ANL C, bit
ORL C, bit
CLR C
CLR bit
CPL C
CPL bit
SETB C
SETB bit

• “bit” can be any of the bit-addressable RAM

locations or SFRs.
 Registers
Bit Addressability Example
Example- Registers
Bit Addressability
 Program Flow Control
Controlling the flow of the program is one of the important
aspects of program development. This is achieved by
conditional and unconditional branching instructions

• Unconditional jumps (“go to”)

• Conditional jumps

• Call and return

 Unconditional Jump
Instructions
• All conditional jumps are short jumps
– Target address within -128 to +127 of PC
• LJMP (long jump): 3-byte instruction
– 2-byte target address: 0000 to FFFFH
– Original 8051 has only 4KB on-chip ROM

• SJMP (short jump): 2-byte instruction

– 1-byte relative address: -128 to +127

• AJMP (Absolute jump): 2-byte instruction

– AJMP’s domain is limited within the current 2K page limit
as indicated by the PC
– 2-byte target address: 0000 to 07FFH

92
 Unconditional Jumps

• SJMP <rel addr> ; Short jump, relative address is 8-

bit 2’s complement number, so jump can be up to 127
locations forward, or 128 locations back.

• LJMP <address 16> ; Long jump

• AJMP <address 11> ; Absolute jump to anywhere within

2K block of program memory

• JMP @A + DPTR ; Long indexed jump

Calculating Short Jump
Address
Calculating Short Jump Address
 Infinite Loops

Start: mov C, p3.7

mov p1.6, C
sjmp Start

Microcontroller application programs are

almost always infinite loops!
 Re-locatable Code
Memory specific NOT
Re-locatable
(machine code) Re-locatable
org 8000h (machine code)
Start: mov C, p1.6 org 8000h
mov p3.7, Start: mov C, p1.6
C mov p3.7,
ljmp Start C
end sjmp
Start
end
 Conditional Jump
• These instructions cause a jump to occur
only if a condition is true. Otherwise,
program execution continues with the
next instruction.

loop: mov a, P1
jz loop ; if a=0, goto loop,
; else goto next
instruction
mov b, a
• There is no zero flag (z)
• Content of A checked for zero on time
 Conditional jumps
Mnemonic Description
JZ <rel addr> Jump if a = 0
JNZ <rel addr> Jump if a != 0
JC <rel addr> Jump if C = 1
JNC <rel addr> Jump if C != 1
JB <bit>, <rel addr> Jump if bit = 1
JNB <bit>,<rel addr> Jump if bit != 1
JBC <bir>, <rel addr> Jump if bit =1, &clear
bit
CJNE A, direct, <rel Compare A and
addr> memory, jump if not
equal
 More Conditional Jumps
Mnemonic Description
CJNE A, #data <rel Compare A and data,
addr> jump if not equal
CJNE Rn, #data <rel Compare Rn and data,
addr> jump if not equal
CJNE @Rn, #data <rel Compare Rn and
addr> memory, jump if not
equal
DJNZ Rn, <rel addr> Decrement Rn and then
jump if not zero
DJNZ direct, <rel addr> Decrement memory and
then jump if not zero
Conditional Jump -JNB
Conditional Jump -JNB
Conditional Jump -JNB
JZ,JNZ Conditional Jump Instructions

104
JZ Conditional Jump Instructions
JNC- Conditional Jump Instructions
JNC- Conditional Jump Instructions
Looping instruction -DJNZ

109
Loop inside a Loop (Nested Loop)

110
Delay Calculation
Delay Calculation
Example - delay Calculation
Example - delay Calculation
Example - delay Calculation
 Example - delay Calculation

mov a,#0aah Delay2:

Back1:mov p0,a mov r6,#0ffh;1cycle
lcall delay1 back1: mov r7,#0ffh ;1cycle
cpl a Here: djnz r7,here ;2cycle
sjmp back1 djnz r6,back1;2cycle
Delay1:mov r0,#0ffh;1cycle
Here: djnz r0,here ;2cycle ret ;2cycle
end
ret ;2cycle
end Delay=1+(1+255*2+2)*255+2
=130818 machine cycle
Delay=1+n*2+2=500 cycle
Compare Instruction
Compare Instruction
Compare Instruction
 Call Instructions
• LCALL (long call): 3-byte instruction
– 2-byte address
– Target address within 64K-byte range

• ACALL (absolute call): 2-byte instruction

– 11-bit address
– Target address within 2K-byte range

Mr. P.8051
Intel Suresh
Programming 120
 Call and Return

• Call is similar to a jump, but

– Call pushes PC on stack before branching

acall <address ll> ; stack  PC

; PC  address 11 bit

lcall <address 16> ; stack  PC

; PC  address 16 bit
 Return

• Return is also similar to a jump, but

– Return instruction pops PC from stack to get address to
jump to

ret ; PC  stack
 Why Subroutines?

• Subroutines allow us to have "structured"

assembly language programs.
• This is useful for breaking a large design into
manageable parts.
• It saves code space when subroutines can be
called many times in the same program.
Subroutine
 Subroutines

Main: ... call to the subroutine

acall sublabel
...
...
sublabel: ...
... the subroutine
ret
LCALL -Instruction
CALL Instruction and Stack
Using PUSH/POP in Subroutine
Calling Subroutines
Difference between
ACALL,LCALL
Subroutine – Examples
 Subroutine – Examples
; Program to compute square root of value on Port 3
; (bits 3-0) and output on Port 1.
org 0
ljmp Main reset service
Main: mov P3, #0xFF ; Port 3 is an input
loop: mov a, P3
anl a, #0x0F ; Clear bits 7..4 of A
lcall sqrt main program
mov P1, a
sjmp loop

sqrt: inc a
movc a, @a + PC
subroutine
ret

Sqrs: db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3
data
end
 Subroutine – Examples
GREEN_LED: equ P1.6
org ooh reset service
ljmp Main

org 100h
Main: clr GREEN_LED
main program
Again: acall Delay
cpl GREEN_LED
sjmp Again

Delay: mov R7, #02

Loop1: mov R6, #00h
Loop0: mov R5, #00h subroutine
djnz R5, $

djnz R6, Loop0

djnz R7, Loop1

 Subroutine – Examples
; duty cycle 50%
back: cpl p1.2
acall delay
sjmp back

back: setb p1.2

acall delay
Clr p1.2
acall delay
sjmp back
 Subroutine – Examples
; duty cycle 66%
back: setb p1.2
acall delay
acall delay
Clr p1.2
acall delay
sjmp back
 Interrupt Sources

• Original 8051 has 5 sources of interrupts

– Timer 0 overflow
– Timer 1 overflow
– External Interrupt 0
– External Interrupt 1
– Serial Port events (buffer full, buffer empty, etc)

• Enhanced version has 22 sources

– More timers, programmable counter array, ADC, more
external interrupts, another serial port (UART)
 Interrupts
…
mov a, #2
mov b, #16
mul ab
mov R0, a
Program Execution

mov R1, b interrupt

mov a, #12
mov b, #20 ISR: inc r7
mul ab mov a,r7
add a, R0 jnz NEXT
mov R0, a cpl P1.6
mov a, R1 NEXT: reti
addc a, b
mov R1, a return
end
 Interrupt Process

If interrupt event occurs AND interrupt flag for that

event is enabled, AND interrupts are enabled,
then:
1. Current PC is pushed on stack.
2. Program execution continues at the interrupt
vector address for that interrupt.
3. When a RETI instruction is encountered, the PC
is popped from the stack and program
execution resumes where it left off.
 Interrupt Priorities

• What if two interrupt sources interrupt at the

same time?
• The interrupt with the highest PRIORITY gets
serviced first.
• All interrupts have a default priority order.
• Priority can also be set to “high” or “low”.
 Interrupt SFRs

Interrupt enables for the 5 original 8051 interrupts:

Timer 2
Serial (UART0)
Timer 1
Global Interrupt Enable – External 1
must be set to 1 for any Timer 0
interrupt to be enabled 1 = Enable
External 0
0 = Disable
 Interrupt Vectors

Each interrupt has a specific place in code memory

where program execution (interrupt service routine)
begins.

External Interrupt 0: 0003h

Timer 0 overflow: 000Bh
External Interrupt 1: 0013h
Note: that there are
Timer 1 overflow: 001Bh
only 8 memory
Serial : 0023h locations between
Timer 2 overflow(8052+) 002bh vectors.
 Interrupt Vectors

To avoid overlapping Interrupt Service routines, it

is common to put JUMP instructions at the vector
address. This is similar to the reset vector.
org 009B ; at EX7 vector
ljmp EX7ISR
cseg at 0x100 ; at Main program
Main: ... ; Main program
...
EX7ISR:... ; Interrupt service routine
... ; Can go after main program
reti ; and subroutines.
 Example Interrupt Service
Routine
;EX7 ISR to blink the LED 5 times.
;Modifies R0, R5-R7, bank 3.
;----------------------------------------------------
ISRBLK: push PSW ;save state of status
word
mov PSW,#18h ;select register bank 3
mov R0, #10 ;initialize counter
Loop2: mov R7, #02h ;delay a while
Loop1: mov R6, #00h
Loop0: mov R5, #00h
djnz R5, $
djnz R6, Loop0
djnz R7, Loop1
cpl P1.6 ;complement LED value
djnz R0, Loop2 ;go on then off 10 times
pop PSW
reti