Microprocessor Lab Manual Final

Vidya Vikas College of Engineering and Technology
EXP. NO. TITLE:
01 (A) STUDY OF INTEL 8085 MICROPROCESSOR KIT
Date: _________
Aim : To study the working of Intel 8085 Microprocessor trainer kit.
Figure 1.1 Vimicros Micro-85 Microprocessor kit
1.1 INTRODUCTION
This section briefs the hardware and software facilities available in both the trainers Micro-85 EBl and Micro-85 EB2. Micro-85 EBl is a powerful Microprocessor Trainer with basic features such as 24 TTL lines using 8255, Hardware Single Stepping and Software Single Stepping of user programs. In addition to the above features, Micro-85 EB2 has RS232C compatible serial port, Bus Expansion for interfacing VBMB series of add-on cards and 24 TTL I/O lines. A separate switch is provided for learning more about hardware. interrupts. There is also provision to add multi output power supply for interfacing experiment boards. Most of the control signals are terminated .at test points for easy analysis on CRO or logic probe.
EC1307 Microprocessor & Application Lab - Manual
The differences in the specification of Micro-85 EBl and Micro-85 EB2 are highlighted in this manual. The users are therefore requested to go through the Hardware specification carefully.
1.2 SPECIFICATIONS 1.2.1 HARDWARE SPECIFICATIONS 1) PROCESSOR, CLOCK FREQUENCY: Intel 8085A at 6.144 MHz clock. . 2) MEMORY: Monitor EPROM EPROM- Expansion System RAM Monitor Data Area User RAM Area RAM- Expansion : 0000 - 1FFF : 2000 - 3FFF & COOO - FFFF : 4000 - 5FFF : 4000 - 40FF (Reserved) : 4100 - 5FFF : 6000 - BFFF
Note: The RAM area from 4000 - 40FF should not be accessed by the user since it is used as scratch pad by the Monitor program. 3) INPUT/OUTPUT: Parallel: 48 TTL :I/O lines using two number of 8255 (only 24 :I/O line. available in micro-85 EB1). Serial : One number of RS232C compatible Serial interface using 8251A - USART.
Timer : Three channel 16-bit Programmable Timer using 8253. - Channel 0 is used as baud rate clock generator for 8251A USART. - Channel 1 is used for in single stepping user programs. - Channel 2 is used for Hardware Single Stepping user programs.
4) DISPLAY: - 6 digit, 0.3", 7 Segment Red LED Display with filter. - 4 digits for address display and 2 digits for data display.
5) KEYBOARD : - 21 Keys soft keyboard including command keys and hexa-decimal keys.
6) AUDIO CASSETTE INTERFACE with file management.
7) BATTERY BACKUP: - Onboard Battery backup facility is provided for the available RAM.
8) HARDWARE SINGLE STEP: This facility allows the user to execute programs at machine cycle level using a separate switch.
9) SYSTEM POWER CONSUMPTION: Micro-85 EB2 + 5 V @ 1 Amp + 12 V@ 200 mA - 12 V @ l00 mA Micro-85 EBl +5V @ 500 mA
10) POWER SUPPLY SPECIFICATIONS: [External ] Micro-85 EB2 Input: 230 V AC @ 50, Hz Micro-85 EB1 230V AC @ 50 Hz + 5 V @ 600 mA
Output: + 5 V @ 1.5 A + 12 V @ 150 mA - 12 V @ 150 mA + 30 V @ 250 mA (Unregulated)
11) PHYSICAL CHARACTERISTICS: Micro-85 EB PCB : 230mm x 170mm [L x B] Weight : 1 Kg.
12) TEST POINTS: Test points provided for MR*, MW*, INTA*, IO/M*, IOR*, IOW*, S0, S1, INTA. This enables the user to study the hardware timing easily.
1.2.2 SOFTWARE SPECIFICATIONS Micro-S5 EB contains a high performance 8K bytes monitor program. It is designed to respond to user input, RS232C serial communications, tape interface etc. The following is a simple description of the key functions. Out of the 21 keys in the keyboard 16 are hexadecimal, command and register keys and the remaining are stand-alone keys.
KEY
FUNCTION SUMMARY
RES
This RES key allows you to terminate any present activity and to return your Micro-85 EB to an initialized state. When pressed, the ..85 signon message appears in the display for a few seconds and the monitor will display command prompt - in the left most digit.
Maskable interrupt connected to CPU's RST 7.5 interrupt.
INT
Decrement the address by one and display it contents (or) Display the previous register contents.
DEC
EXEC
Execute a particular program after selecting the address through GO command.
DEC
Increment address by one and display its contents (or) Display the next register content.
The 16 Hexa decimal keys have either a dual or a triple role to play. i) It functions as a Hex key entry when a address or data entry is required. ii) It functions as the Register key entry during Register command. iii) It functions as command key when pressed directly after command prompt.
NOTE: The Hex-key function summary below is in the order: i) Hex key. ii) Command key iii) Register key.
KEY
FUNCTION SUMMARY
i. 0 E SUB
Hex key entry "0"
ii. This key is for substituting memory contents When NEXT key is pressed immediate1y after this it takes the user to the start address for entering user programs, 4100 Hex (User RAM). iii. Register key "E"
1 D REG
i. Hex key entry "1" ii. Examine the 8085A registers and modify the same. iii. Register key "D"
2 C TW
i. Hex key entry "2" ii. Writes data from memory on to audiotape. iii. Register key "C"
3 B TR
i.
Hex key entry 3
ii. Retrieve data from an audiotape to memory. iii. Register key B
4 F BLOC
i.
Hex key entry 4.
ii. Block search for a byte. iii. Register key F.
5 A FILL
i.
Hex key entry 5.
ii. Fill a block of RAM memory with desired data. iii. Register key A.
6 L SER
i.
Hex key entry "6"
ii. Transmit/Receive data to/from the serial port. The TW/TR keys are used for sending/receiving respectively. iii. Register key L.
7 H F2
i.
Hex key entry "7"
ii. Register key "H"
8 I GO
i.
Hex key entry "8"
ii. Start running a particular program iii. Register key "I"
9 PL SNG
i.
Hex key entry "9"
ii. Single step a program instruction by instruction. iii. Register key PCL.
i A PH F3
Hex key entry "A"
ii. Function key F3 F3 [0] = Input a byte from a port P3 [1] = Output a byte to a port iii. Register key PCH" iv. Used with SNG key for hardware single stepping.
B SL BC
Hex key entry "B"
ii. Check a particular block for blank. iii. Register key "SPL"
C SH MOV
i. ii.
Hex key entry "C" Move block of memory to another block
iii. Register key SPH
D CMP
i.
Hex key entry "D"
ii. Compare two memory blocks.
E INS
i.
Hex key entry "E"
ii. Insert bytes into memory (RAM) .
F DEL
i. Hex key entry "F" ii. Delete bytes from memory (RAM).
EXP. NO. TITLE:
01 (B) STUDY OF INTEL 8086 MICROPROCESSOR
FEATURES: 1. 16-bit Data bus 2. Computes 16 bit / 32 bit data. 3. 20-bit address bus. 4. More memory addressing capability (220 = 1MB) 5. 16 bit Flag register with 9 Flags 6. Can be operated in Minimum mode and Maximum mode 7. Has two stage pipelined architecture 8. No internal clock generation 9. 40 pin DIP IC - HMOS technology 10. Operates on +5V supply voltage 11. Has more powerful instruction set
Memory: Program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB KB. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see the "Registers" section below).
16-bit pointers and data are stored as: address address+1 : low-order byte : high-order byte
32-bit addresses are stored in "segment:offset" format as: address address+1 address+2 address+3 : low-order byte of segment : high-order byte of segment : low-order byte of offset : high-order byte of offset
Physical memory address pointed by SEGMENT:OFFSET pair is calculated as: Physical address = (<Segment Addr> * 16) + <Offset Addr>
Program memory - program can be located anywhere in memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction. Data memory - the processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB (if all four segments point to different 64 KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by default may use the ES or SS segments instead of DS segment). Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. Stack memory can be placed anywhere in memory. The stack can be located at odd memory addresses, but it is not recommended for performance reasons (see "Data Memory" above). Reserved locations: 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format SEGMENT:OFFSET. FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address.
Interrupts: The processor has the following interrupts: INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction. When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return with the IRET instruction. NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority then the maskable interrupt. Software interrupts can be caused by: INT instruction - breakpoint interrupt. This is a type 3 interrupt. INT <interrupt number> instruction - any one interrupt from available 256 interrupts. INTO instruction - interrupt on overflow Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. Processor exceptions: divide error (type 0), unused opcode (type 6) and escape opcode (type 7). Software interrupt processing is the same as for the hardware interrupts.
I/O ports: 8086 can interface maximum of 65536 nos of 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.
Registers: Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix.
All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are: Accumulator (AX) register consists of 2 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations and string manipulation. Base (BX) register consists of 2 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.
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Count (CX) register consists of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Count register can be used as a counter in string manipulation and shift/rotate instructions. Data (DX) register consists of 2 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.
The following registers are both general and index registers: Stack Pointer (SP) is a 16-bit register pointing to program stack. Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: Instruction Pointer (IP) is a 16-bit register.
Flag Register is a 16-bit register containing 9 nos of one bit flags: Overflow Flag (OF) - set if the result is too large positive number, or is too small negative number to fit into destination operand. Direction Flag (DF) - if set then string manipulation instructions will autodecrement index registers. If cleared then the index registers will be autoincremented. Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts. Single-step Flag (TF) - if set then single-step interrupt will occur after the next instruction. Sign Flag (SF) - set if the most significant bit of the result is set. Zero Flag (ZF) - set if the result is zero.
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Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register. Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even. Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation.
Instruction Set: 8086 instruction set consists of the following instructions: Data moving instructions. Arithmetic - add, subtract, increment, decrement, convert byte/word and compare. Logic - AND, OR, exclusive OR, shift/rotate and test. String manipulation - load, store, move, compare and scan for byte/word. Control transfer - conditional, unconditional, call subroutine and return from subroutine. Input/Output instructions. Other - setting/clearing flag bits, stack operations, software interrupts, etc.
Addressing modes: Implied - the data value/data address is implicitly associated with the instruction. Register - references the data in a register or in a register pair. Immediate - the data is provided in the instruction. Direct - the instruction operand specifies the memory address where data is located. Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.
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Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides. Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides.
Result: The features of the Intel 8085 & 8086 microprocessors were studied and operations of the corresponding kits were understood.
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Fig.2.1 Flow chart for 8-bit Addition with carry
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EXP. NO. TITLE:
02 (A)
Date: _________
8-BIT ARITHMETIC OPERATIONS (8-BIT ADDITION)
AIM: To write an assembly language program for the addition of two 8-bit numbers.
APPARATUS REQUIRED: S.N o 1 2 Item Description 8085-microprocessor kit. Power supply unit Qty 1 1
THEORY: The two operands (i.e., 8-bit numbers) are loaded into two registers A & B, using immediate addressing mode instructions and then added using ADD instruction. The result is stored in the desired memory location. The overflow in addition is checked by verifying the status of Carry (Cy) flag and accordingly either 00 or 01 is stored in the location next to the result.
ALGORITHM: 1. Start the program 2. Initialize the C register as 00H. 3. Move the data1 and data2 to Accumulator and B register respectively. 4. Add B register to the content of accumulator 5. If there is no carry, go to step 6, else increment C register. 6. Store the content of accumulator to the memory location 4500H. 7. Move the content of C register to accumulator. 8. Store the content of accumulator to the memory location 4501H. 9. Stop the program.
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PROGRAM: Address 4100 4102 4104 4106 4107 410A 410B 410E 410F 4112 Opcode & Operand 0E, 00 3E, Data1 06, Data2 80 D2, 0B,41 0C 32,00,45 79 32,01,45 76 GO: Label Mnemonics MVI C, 00 MVI A, Data1 MVI B, Data2 ADD B JNC GO INR C STA 4500 MOV A,C STA 4501 HLT Comments Clear c register Move data1 to accumulator Move data2 to B Register Add B Reg to accumulator Jump on No carry to location GO Increment C Register Store the result Move carry to Acc Store the carry Stop the program
MANUAL CALCULATION:
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SAMPLE DATA:
Result of 8-bit addition without carry: INPUT Address 4103 4105 Data 05H 06H OUTPUT Address 4500 (Result) 4501 (Carry) Data 0BH 00H
Result of 8-bit addition with carry: INPUT Address 4103 4105 Data 51H EBH OUTPUT Address 4500 (Result) 4501 (Carry) Data 3CH 01H
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation.
INPUT Address 4103 4105 Data
OUTPUT Address 4500 (Result) 4501 (Carry) Data
RESULT: Thus the assembly language program for 8-bit addition is executed and the results are verified.
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Fig. 2.2 Flow chart for 8-bit subtraction
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EXP. NO. 02 (B) TITLE:
Date: _________
8-BIT ARITHMETIC OPERATION (8-BIT SUBTRACTION)
AIM: To write an assembly language program for the subtraction of two 8-bit numbers, using 8085.
THEORY: Out of the two operands for subtraction, the first operand is loaded into Accumulator and the second operand is subtracted directly from memory, using register indirect addressing mode instructions. The result is stored in desired memory location and the borrow in subtraction is checked by verifying the status of Carry (Cy) flag and accordingly either 00 or 01 is stored in the location next to result.
ALGORITHM: 1. Start the program. 2. Load the HL pair with 16-bit address of data location. 3. Move the content of memory address in HL to accumulator. 4. Increment the address in HL pair. 5. Subtract the content of memory from accumulator. 6. Jump on No-carry to step 8. 7. Increment the C-register. 8. Store the content of accumulator and C-register. 9. Stop the program.
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PROGRAM: Address 4100 4103 4104 4106 4107 4108 410B 410C 410F 4110 4113 Opcode & Operand 21, 50, 41 7E 0E, 00 23 96 D2, 0C, 41 0C 32, 52, 41 79 32, 53, 41 76 NEXT: Label Mnemonics LXI H,4150 MOV A, M MVI C, 00 INX H SUB M JNC NEXT INR C STA 4152 MOV A,C STA 4153 HLT Comments Load data to HL Register Move Data1 to Acc Clear C-register. Increment address. Subtract Data2 from Acc Jump on No-carry to the location NEXT. Increment C register Store the result Move carry to acc Store the carry Stop the program
MANUAL CALCULATION:
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SAMPLE DATA:
Result of 8 bit subtraction without carry: INPUT Address 4150 4151 Data 68H 54H OUTPUT Address 4152 (Result) 4153 (Borrow) Data 14H 00H
Result of 8 bit subtraction with carry: INPUT Address 4150 4151 Data 57H 66H OUTPUT Address 4152 (Result) 4153 (Borrow) Data F1H 01H
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation.
INPUT Address 4150 4151 Data
OUTPUT Address 4152 (Result) 4153 (Borrow) Data
RESULT: Thus the assembly language program for 8-bit subtraction is executed and the results are verified.
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Fig.2.3 Flow chart for 8-bit Multiplication
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EXP. NO. TITLE:
02 (C)
Date: _________
8-BIT ARITHMETIC OPERATION (8-BIT MULTIPLICATION)
AIM: To write an assembly language program for the multiplication of two 8-bit numbers, using 8085.
THEORY: Using the immediate addressing mode instructions, the two operands to be multiplied are loaded into two registers say, B and C. By the method of repeated addition, the multiplication operation is performed (i.e., first number is repeatedly added to accumulator as per the second number Eg. 03 x 04 => Acc + 03 (04 times) ). The overflow in multiplication is checked every time after each addition, by verifying the status of Carry (Cy) flag and accordingly a register, say D is incremented. The result in accumulator is stored in the desired memory location and the content of D register is stored in the location next to result.
ALGORITHM: 1. Start the program. 2. Clear the Accumulator and D Register. 3. Load the Data1 to B register and Data2 to C register. 4. Add the content of B to accumulator until C becomes zero. 5. If No-carry, go to step 6. 6. Increment the D-register. 7. Decrement the C register. 8. If C register is Non-zero, Jump to step 4. 9. Store the content of accumulator to 5000H. 10. Move the content of D-register to Accumulator. 11. Store the content of accumulator to 5001H. 12. Stop the program.
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PROGRAM: Address 4500 4502 4504 4506 4508 4509 450C 450D 450E 4511 4514 4515 4518 Opcode & Operand 3E, 00 06, Data1 0E, Data2 16,00 80 D2, 0D, 45 14 0D C2, 08,45 32,00,50 7A 32,01,50 76 LOOP1: LOOP2: Label Mnemonics MVI A,00 MVI B, Data1 MVI C, Data2 MVI D, 00 ADD B JNC LOOP1 INR D DCR C JNZ LOOP2 STA 5000 MOV A,D STA 5001 HLT Comments Move data to accumulator Move multiplicand to b register Move the multiplier to c register Clear D-reg for carry repetitive addition Jump on no carry to an location LOOP1 Increment the D-register, if carry occurs. Decrement C-register Jump on no zero to Location LOOP2 Store resultant product Move carry to accumulator Store the carry. Stop the program.
MANUAL CALCULATION
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SAMPLE DATA:
Result of 8 bit multiplication without carry: INPUT Address 4503 4505 Data 05H 05H OUTPUT Address 5000 (Result) 5001 (Carry) Data 19H 00H
Result of 8 bit multiplication with carry: INPUT Address 4503 4505 Data 41H 25H OUTPUT Address 5000 (Result) 5001 (Carry) Data 45H 01H
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 4503 4505 Data OUTPUT Address 5000 (Result) 5001 (Carry) Data
RESULT: Thus the assembly language program for 8-bit multiplication is executed and the results are verified.
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Fig. 2.4 Flow chart for 8-bit Division
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EXP. NO. 02 (D) TITLE: 8-BIT ARITHMETIC OPERATION (8-BIT DIVISION)
Date: _________
AIM: To write an assembly language program for the division of two 8 bit numbers, using 8085.
THEORY: Using the immediate addressing mode instructions, the Divisor and Dividend are loaded directly into Accumulator and B register. By the method of successive subtraction, the division is carried out (i.e., Divisor is repeatedly subtracted from Dividend, until the dividend becomes smaller than divisor Eg. 09 / 02 => 09 02 (4 times) => Remainder=01 and Quotient=04). The C register is incremented every time after each subtraction, to keep count of the quotient. The final content in accumulator will be remainder of the division and it is stored in the desired memory location and the content of C register containing the quotient is stored in the location next to result.
ALGORITHM: 1. Start the program. 2. Clear C Register. 3. Load the Divisor to Accumulator. 4. Load the Dividend to B-register. 5. Compare the B-register value with the accumulator. 6. If Accumulator content is smaller to B reg., then Jump to step 10. 7. Subtract B-register value with accumulator. 8. Increment the C-register. 9. Jump to step 4. 10. Store the contents of accumulator and C-register into memory. 11. Stop the program.
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PROGRAM: Address 4500 4502 4504 4506 4507 450A 450B 450C 450F 4512 4513 4516 Opcode & Operand 3E, Divisor 06, Dividend 0E, 00 B8 DA, 0F, 45 90 0C C3, 06,45 32,00,50 79 32,01,50 76 LOOP1: LOOP2: Label Mnemonics MVI A, Divisor MVI B, Dividend MVI C, 00 CMP B JC LOOP1 SUB B INR C JMP LOOP2 STA 5000 MOV A,C STA 5001 HLT Comments Move Divisor to Acc Move Dividend to B reg. Clear C register Compare Acc and B reg. Jump on Carry to location LOOP1 Repetitive subtraction for division Increment C register Jump to location LOOP2 Store the Remainder Move C reg. to Acc Store the Quotient. Stop the program.
MANUAL CALCULATION:
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SAMPLE DATA: Result of 8-bit Division without remainder: INPUT Address 4501 4503 Data 06H 03H OUTPUT Address 5000 (R) 5001 (Q) Data 00H 02H
Result of 8 bit division with remainder: INPUT Address 4501 4503 Data 25H 05H OUTPUT Address 5000 (R) 5001 (Q) Data 02H 07H
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 4501 4503 Data OUTPUT Address 5000 (R) 5001 (Q) Data
RESULT: Thus the assembly language program for 8-bit division is executed and the results are verified.
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Fig. 2.5 Flow chart for 16-bit Addition
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EXP. NO. 02 (E) TITLE:
Date: _________
8-BIT ARITHMETIC OPERATION (16-BIT ADDITION)
AIM: To write an assembly language program for the addition of two 16-bit numbers, using 8085.
THEORY: Using the direct addressing mode instructions, the two 16-bit numbers are loaded into HL and DE register pairs from memory. Using the double addition instruction (DAD rp), the contents of HL and DE are added together and the results are stored in the HL register pair again. The B register is used to check the overflow of the above addition, by verifying the carry flag. The result in the HL register pair is stored in the desired memory location and the content of B register is stored in the location next to result.
ALGORITHM: 1. Start the program. 2. Clear the B-register. 3. Load the Data1 to HL register pair. 4. Exchange the content of HL to the DE register pair. 5. Load the Data2 to HL pair register. 6. Add the content of HL and DE pair. 7. If no overflow in addition (no carry), go to step 9. 8. Increment the content of B-register. 9. Store the content of HL pair to the address 5504H. 10. Store the content of B-register to the address 5506H. 11. Stop the program.
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PROGRAM: Address 4500 4502 4505 4506 4509 450A 450D 450E 4511 4512 4515 Opcode & Operand 06,00 2A, 00,55 EB 2A, 02,55 19 D2, 0E, 45 04 22,04,55 78 32,06,55 76 LOOP Label Mnemonics MVI B,00 LHLD 5500 XCHG LHLD 5502 DAD D JNC LOOP INR B SHLD 5504 MOV A,B STA 5506 HLT Comments Clear B register Load Data1 to HL register Shift the data in HL to DE register Load the Data2 to HL pair Add the content of the HL and DE pair Jump on no carry to an address Increment the B register Store the result Move carry to B register. Store the carry. Stop the program.
MANUAL CALCULATION:
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SAMPLE DATA: Result of 16-bit Addition without carry: INPUT Address 5500, 01 5502, 03 Data 7167H 8685H OUTPUT Address 5504, 05 (Result) 5506 (Carry) Data F7ECH 00H
Result of 16-bit Addition with carry: INPUT Address 5500, 01 5502, 03 Data FF03H EF03H OUTPUT Address 5504, 05 (Result) 5506 (Carry) Data 06FEH 01H
Exercise: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 5500, 01 5502, 03 Data OUTPUT Address 5504, 05 (Result) 5506 (Carry) Data
RESULT: Thus the assembly language program for 16-bit addition is executed and the results are verified.
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Fig. 2.6 Flow chart for 16-bit Subtraction
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EXP. NO. TITLE:
02 (F)
Date: _________
8-BIT ARITHMETIC OPERATION (16-BIT SUBTRACTION)
AIM: To write an assembly language program for the subtraction of two 16-bit numbers, using 8085.
THEORY: Using the direct addressing mode instructions, the two 16-bit numbers are loaded into HL and DE register pairs. The lower bytes of the two numbers are subtracted first using SUB instruction and the higher bytes of the same two numbers are subtracted along with borrow using SBB instruction. The result in the accumulator after each subtraction is stored in the two subsequent desired memory locations.
ALGORITHM: 1. Start the program. 2. Load the Data2 to HL register pair. 3. Exchange the content of HL to the DE register pair. 4. Load the Data1 to HL register pair. 5. Move the content of L register to Accumulator. 6. Subtract the content of E register from the Accumulator. 7. Store the result in accumulator to the memory location, 5100H. 8. Move the content of H register to Accumulator. 9. Subtract the content of D register from the Accumulator, along with borrow. 10. Store the result in Accumulator to the memory location, 5101H. 11. Stop the program.
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PROGRAM: Address 4500 4503 4504 4507 4508 4509 450C 450D 450E 4511 Opcode & Operand 2A, 00,55 EB 2A, 02,55 7D 93 32,00,51 7C 9A 32,01,51 76 Label Mnemonics LHLD 5500 XCHG LHLD 5002 MOV A,L SUB E STA 5100 MOV A,H SBB D STA 5101 HLT Comments Load the Data2 to HL register. Transfer the content of HL to DE register pair. Load the Data2 to HL pair register. Move the content of L register to accumulator Subtract E register and accumulator Store the result Move H register to accumulator Subtract D register and accumulator Store the result. Stop the program.
MANUAL CALCULATION:
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SAMPLE DATA: Result of 16-bit Subtraction: INPUT Address 5500, 01 (Data2) 5502, 03 (Data1) Data 6677H 7788H OUTPUT Address 5100 (Result) Data 1111H -
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 5500, 01 (Data2) 5502, 03 (Data1) Data OUTPUT Address 5100 (Result) Data
RESULT: Thus the assembly language program for 16-bit subtraction is executed and the results are verified.
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Fig. 3.1a Flow chart for Sorting in Ascending order
40
EXP. NO. TITLE :
03 (A) SORTING AND SEARCHING USING 8085 -
Date: _________ SORTING PROGRAM
AIM: To write an assembly language program for arrange an array of 8-bit numbers in ascending and descending order, using 8085.
THEORY: This program uses the register indirect addressing mode instructions, to access the data during sorting. The Bubble-Sort technique is used to sort the numbers in either ascending order or descending order. The numbers to be sorted is stored in the memory as a array with the first location containing the count of the data in the array. The sorted numbers are stored back again in the same source location of the array.
(I) ALGORITHM : ASENDING ORDER: 1. Start the program 2. Load the data address to HL register pair and Initialize B register with 00 3. Move the array size count into C-register, then decrement the C-register by 1 and increment HL register pair by 1. 4. Load the first data in the memory to Accumulator. 5. Compare the subsequent memory with Accumulator. 6. Jump on Carry, when M is greater A and go to Step 9. 7. Move the memory M to D register 8. Decrement the address of HL pair and move the D register content to M and increment the value by HL by 1. 9. Move 01 to B register and decrement the C-register. 10. If C is Non-zero, Jump to comparison of next data. 11. If B becomes zero after decrement, go to step1. 11. Stop the program.
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PROGRAM: Address 4100 4102 4105 4106 4107 4108 4109 410A 410B 410E 410F 4110 4111 4112 4113 4115 4116 4119 411A 411D Opcode & Operand 06,00 21,50,41 4E 0D 23 7E 23 BE DA, 15,41 56 77 2B 72 23 06,01 0D C2, 08,41 05 CA, 00,41 76 LOOP1: LOOP2: Label AHEAD: Mnemonics MVI B,00 LXI H, 4150 MOV C,M DCR C INX H MOV A,M INX H CMP M JC LOOP1 MOV D,M MOV M,A DCX H MOV M,D INX H MVI B,01 DCR C JNZ LOOP2 DCR B JZ AHEAD HLT Comments Clear the counter Load Data addr to HL pair. Move Array size to C-reg Decrement C reg Increment addr in HL Move data-I in HL to A Increment addr in HL Compare data-II of Memory (HL) with A Jump on cy to add Move the data in HL to D reg Move content of acc to HL. Decrement address in HL register. Move content of D to M reg Increment address of HL register Move data to B reg Decrement C reg Jump on no zero Decrement B reg Jump on zero to ahead Stop the program
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SAMPLE DATA:
Result of the Sorting in Ascending Order INPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 Data 05H 78H A6H 42H 25H 37H OUTPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 Data 05H 25H 37H 42H 78H A6H
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 4156 4157 Data OUTPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 4156 4157 Data
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Fig. 3.1b Flow chart for Sorting in Descending order
44
(II) ALGORITHM: DESENDING ORDER: 1. Start the program 2. Load the data address to HL and initialize B register with 00 3. Move the Array size count into C-register then decrement the C-register by 1 and increment HL by 1. 4. Load the data-I in the memory to A. 5. Compare the subsequent memory content with A. 6. Jump on No-carry (when M is greater A), go to Step 9. 7. Move the memory M to D register 8. Decrement the value of HL pair and move the D register content to M and increment the value by HL by 1. 9. Move B register and decrement the C-register. 10. Jump on Non-Zero to the next comparison. If zero, then decrement B and go to step1. 11. Stop the program.
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PROGRAM: Address 4100 4102 4105 4106 4107 4108 4109 410A 410B 410E 410F 4110 4111 4112 4113 4115 4116 4119 411A 411D Opcode & Operand 06, 00 21, 50, 41 4E 0D 23 7E 23 BE D2, 15, 41 56 77 2B 72 23 06, 01 0D C2, 08, 41 05 CA, 00,41 76 LOOP1: LOOP2: Label AHEAD: Mnemonics MVI B,00 LXI H,4150 MOV C,M DCR C INX H MOV A,M INX H CMP M JNC LOOP1 MOV D,M MOV M,A DCX H MOV M,D INX H MVI B,01 DCR C JNZ LOOP2 DCR B JZ AHEAD HLT Comments Clear the counter Load Data addr to HL pair. Move Array size to C-reg Decrement C reg Increment addr in HL Move data-I in HL to A Increment addr in HL Compare data-II of Memory (HL) with A Jump on No-Carry to Loop1 Move the data in M to D reg Move content of A to M. Decrement address in HL reg. Move content of D reg. to M Increment Addr in HL reg Move data to B reg Decrement C reg Jump on Non-zero to LOOP2 Decrement B reg Jump on Zero to AHEAD Stop the program
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SAMPLE DATA:
Result of the Sorting in Descending order: INPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 Data 05H 78H A6H 42H 25H 37H OUTPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 Data 05H A6H 78H 42H 37H 25H
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 4156 4157 Data OUTPUT Address 4150 (Array Size) 4151 4152 4153 4154 4155 4156 4157 Data
RESULT: Thus the assembly language program for sorting Ascending & Descending order is executed and the results are verified.
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Fig. 3.2 Flow Chart for Searching
48
EXP. NO. TITLE :
03 (B) SORTING AND SEARCHING USING 8085 -
Date: __________ SEARCHING PROGRAM
AIM: To write an assembly language program to search the given data in an array. APPARATUS REQUIRED: S.N o 1 2 Item Description 8085-microprocessor kit. Power supply unit Qty 1 1
THEORY: This program uses the register indirect addressing mode instructions, to access the data for searching a number from the array stored in the memory. The numbers to be searched is loaded into the Accumulator and compared with the numbers of the given array. Here again, the array has the data count stored in its first location. At the end of searching, this program provides the information about the number of times the given number is found in the array. The result is stored in the desired memory location.
ALGORITHM: 1. Start the program. 2. Load the data address to the HL register pair. 3. Load the data to be searched in Accumulator. 4. Load the data count of array in the C register. 5. Initialize the B register with 00. 6. Compare the memory content addressed by HL pair with Accumulator. 7. If not equal (zero flag is set); go to step 9. 8. Increment the B register. 9. Increment the HL register pair. 10. Decrement the C register by 1 and if not zero, go to step 6. 11. Store the content of B register in memory. 12. Stop the program.
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PROGRAM: Address 4100 4103 4106 4108 4109 410A 410B 410E 410F 4110 4113 4114 4117 Opcode & Operand 3A, 50, 42 21, 51, 42 06, 00 4E 23 BE C2, 0F, 41 04 0D C2, 09, 41 78 32, 00, 42 76 NEXT: LOOP: Label Mnemonics LDA 4250H LXI H, 4251H MVI B,00H MOV C, M INX H CMP M JNZ NEXT INR B DCR C JNZ LOOP MOV A, B STA 4200 HLT Comments Load data to be searched into Acc from memory Set pointer for data array Clear B register Load data count to C reg. Increment HL reg. pair Compare Acc & memory If Not equal, go to location NEXT Increment B register Decrement C register If not zero, go to location LOOP Move the data from B to Acc Store the result Stop the program
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SAMPLE DATA:
Result of the Searching: INPUT Address 4250 (Data to be searched) 4251 (Array size) 4252 4253 4254 4255 4256 4257 Data 75H 06H 23H 75H C1H A7H 75H 12H The result shows the number of times, the given number that was found in the array. OUTPUT Address 4200 (Result) Data 02H
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 4250 (Data to be searched) 4251 (Array size) 4252 4253 4254 4255 4256 The result shows the number of times, the given number that was found in the array. Data OUTPUT Address 4200 (Result) Data
RESULT: Thus the assembly language program for searching the given data from an array is executed and the result is verified.
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Fig. 3.3a Flow chart for Sorting in Ascending order on 8086.
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EXP. NO. TITLE:
03 (C) SORTING AND SEARCHING USING 8086 -
Date: _________ SORTING PROGRAM
AIM: To write an assembly language program for the sorting in ascending and Descending order, using 8086.
THEORY: The Bubble-Sort technique is used to sort the numbers in either ascending order or descending order. The numbers to be sorted is stored in the memory as a array with the first location containing the count of the data in the array. The sorted numbers are stored back again in the same source location of the array.
(I) ALGORITHM: ASCENDING ORDER: 1. Start the program 2. Move data to CX register and move CX data to DI register 3. Move 1200 to the BX register and move the content of 1200 to memory of AX 4. Compare the content of AX with 1202 5. Jump on borrow to rep 6. Move the data in memory to AX and move Data from AX to AI 7. Add Data to BX register and go to loop2 8. Perform no operation and move data & DI to CX 9. Go to the loop 10. Stop the program
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PROGRAM: Address 1000 1003 1005 1008 100A 100D 100F 1012 101A 1017 1019 101A 101C 101E Opcode & Operand B9, 07, 00 89 CF BB, 00, 12 8B, 07 3B, 47, 02 72, 05 87, 47, 02 89, 07 83, C3, 02 F2, EF 90 89, F9 E2, E5 F4 REP: LOOP2: LOOP1: Label Mnemonics MOV CX,07 MOV DI,CX MOV BX,1200 MOV AX,AI[BX] CMP AX,AI[BX+2] JB REP XCHG AX,AI[BX+2] MOV AI[BX],AX ADD BX,02 LOOP LOOP2 NOP MOV CX,DI LOOP LOOP1 HLT Comments Move data to CX reg Move CX data to DI Move 1200 to the BX reg Move the content of 1200 to memory of AX Compare the content of AX with 1202H Jump on borrow to rep Move the data in memory to AX Move data from AX to AI Add data to BX register Go to loop2 No operation Move data of DI to CX Go to loop1 Stop the process
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SAMPLE DATA: Result of Sorting in Ascending order: INPUT Address 1100 1102 1104 1106 1108 110A 110C 110E Data 00FFH 0100H 1101H 00FEH 00CCH CDEFH ABCDH 1234H OUTPUT Address 1100 1102 1104 1106 1108 110A 110C 110E Data 00CCH 00FEH 00FFH 0100H 1101H 1234H ABCDH CDEFH
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 1100 1102 1104 1106 1108 110A 110C 110E Data OUTPUT Address 1100 1102 1104 1106 1108 110A 110C 110E Data
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Fig. 3.3b Flow chart for Sorting in Descending order on 8086.
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(II) ALGORITHM : DESCENDING ORDER 1. Start the program. 2. Move the data to CX register and move CX content to D1 register. 3. Move the address to BX register and move the count of 1200 to AX. 4. Compare the content of AX with 1202. 5. Jump on no borrow to REP. 6. Exchange AX and A1 register and move AX register to BX. 7. Add BX register to 2 and continue the loop up to CX is zero. 8. Perform no operation and move D1 register to CX register and continue the loop up to CX is zero. 9. Stop the program.
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PROGRAM: Address 1000 1003 1005 1008 100A 100D 100F 1012 101A 1017 1019 101A 101C 101E Opcode & Operand B9, 07, 00 89 CF BB, 00, 12 8B, 07 3B, 47, 02 72, 05 87, 47, 02 89, 07 83, C3, 02 F2, EF 90 89, F9 E2, E5 F4 REP: LOOP2: LOOP1: Label Mnemonics MOV CX,07 MOV DI,CX MOV BX,1200 MOV AX,AI[BX] CMP AX,AI[BX+2] JNB REP XCHG AX,AI[BX+2] MOV AI[BX],AX ADD BX,02 LOOP LOOP2 NOP MOV CX,DI LOOP LOOP1 HLT Comments Move data to CX reg Move CX data to DI Move 1200 to the BX reg Move the content of 1200 to memory of AX Compare the content of AX with 1202H Jump on No-borrow to REP Move the data in memory to AX Move data from AX to AI Add data to BX register Go to LOOP2 No operation Move data of DI to CX Go to LOOP1 Stop the process
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SAMPLE DATA: Result of Sorting in Descending order: INPUT Address 1100 1102 1104 1106 1108 110A 110C 110E Data 00FFH 0100H 1101H 00FEH 00CCH CDEFH ABCDH 1234H OUTPUT Address 1100 1102 1104 1106 1108 110A 110C 110E Data CDEFH ABCDH 1234H 1101H 0100H 00FFH 00FEH 00CCH
EXERCISE: Execute the program with your own data and observe the results. Check the result with your manual calculation. INPUT Address 1100 1102 1104 1106 1108 110A 110C 110E Data 1100 1102 1104 1106 1108 110A 110C 110E OUTPUT Address Data
RESULT: Thus the assembly language programs for sorting- ascending & descending order was executed are verified.
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Fig. 4 Flow chart for String Manipulation
60
EXP. NO. TITLE:
04 STRING MANIPULATION USING 8086
Date: _________
AIM: To write an assembly language program to move a byte of string of length FF from a source to a destination.
THEORY: A group of similar data stored in consecutive memory locations, representing a variable can be celled as a String. Various operations can be performed on the string data like, string copy, string compare, string store, string load, etc. The following program helps to copy a string data from a source location to a destination location.
ALGORITHM: 1. Start the program. 2. Set the SI to point the source array and DI at destination location. 3. Move the string size to CX register. 4. Direction Flag is cleared so that SI & DI will auto increment after each loop. 5. Move the bytes of the string using MOVSB instruction. 6. Stop the program.
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PROGRAM: Address 1000 1003 1006 1009 100A 100B 100D Opcode & Operand BE, 00, 11 BF, 00, 12 B9, FF, 00 FC A4 E2, FD F4 NEXT: Label Mnemonics MOV SI, Source MOV DI, Destination MOV CX, 00FFH CLD MOV SB LOOP NEXT HLT Comments Load offset address of Source to SI register Load offset address of destination to DI register Number of array elements in CX register Clear Direction Flag (D) Move string byte Decrement CX and Check for Zero. If not zero, go to location NEXT Stop the program
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SAMPLE DATA: Result of String manipulation: INPUT (Source) Address 1100 To 11FF Data xx xx xx OUTPUT (Destination) Address 1200 To 12FF Data xx xx xx
As CX Register is loaded with string size FF 256 bytes of data at source location (starting from 1100H) will be copied to destination location (at address 1200H) EXERCISE: Result of String manipulation: INPUT (Source) Address 1100 1101 1102 1103 1104 1105 1106 1107 1108 Data OUTPUT (Destination) Address 1200 1201 1202 1203 1204 1205 1206 1207 1208 Data
Execute the program with following modifications. a) Move smaller sized string data, by changing the string size stored in CX register. b) Change the auto-increment of SI & DI registers to auto-decrement by setting the direction flag to 1. Also store the last address of the string in SI & DI register instead of starting address of the string.
RESULT: Thus the string was moved from source to destination using the assembly language of 8086.
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Fig. 5.1 Block diagram of ADC conversion
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EXP. NO. TITLE:
05 INTERFACING ADC AND DAC USING 8085
Date: _________
AIM: To write an assembly language program to interface ADC and DAC with 8085 microprocessor kit.
APPARATUS REQUIRED: S.N o 1 2 3 4 Item Description 8085-microprocessor kit. CRO ADC & DAC interface board Flat ribbon Cable Qty 1 1 1 1
THEORY: In a real time applications, processing of input data, conversion of data from digital to analog and vice versa, are indispensable. The following program initiates the analog to digital conversion process, checks the EOC pin of ADC 0809 as to whether the conversion is over and then inputs the data to the processor. It also instructs the processor to store the converted digital data in the memory.
ADC: HARDWARE DETAILS: ADC 0809 is a monolithic CMOS device, with an 8-bit analog-to-digital converter, 8 channel multiplexer and microprocessor compatible control logic. Selected Analog Channel IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 Address Lines in the Multiplexer of ADC 0809 Addr C Addr B Addr A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
A particular input channel is selected by using address decoding. The conversion begins at the falling edge of the SOC pulse. The conversion will complete before 8th clock pulse from the rising edge of SOC pulse.
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PROGRAM FOR ADC: Address 4100 4102 4104 4106 4108 410A 410C 410D 410E 410F 4111 4113 4115 4117 4119 411C 411E 4121 Opcode & Operand 3E, 10 D3, C8 3E, 18 D3, C8 3E, 01 D3, D0 AF AF AF 3E, 00 D3, D0 DB, D8 E6, 01 FE, 01 C2, 13, 41 DB, C0 32, 50, 41 76 LOOP: Label START: Mnemonics MVI A,10H OUT C8H MVI A, 18H OUT C8H MVI A, 01H OUT D0H XRA A XRA A XRA A MVI A, 00H OUT D0H IN D8H ANI 01H Check for EOC signal CPI 01H JNZ LOOP IN C0H STA 4150 HLT Input the digital data from ADC interface Store the data in memory Stop the program Send LOW in SOC signal of ADC Waste time to make A/D conversion to complete Send HIGH in SOC signal of ADC Select the input channel Comments
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ALGORITHM: 1. Start the program. 2. Give start of conversion pulse and set the data. 3. Check for the end of the pulse. 4. Store the digital data in the memory. 5. Stop the program.
OBSERVATION:
Execute this program and compare the data displayed at the LEDs with that of the stored data at location 4150H.
Vin Analog Voltage Set at input of ADC
Digital Output seen in LED
Digital Output Stored in memory location 4150
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Fig. 5.2 Block diagram of the DAC interface with 8085 Kit.
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DAC: HARDWARE DETAILS: Digital to analog converter can be classified as current output, voltage output, multiplexing type. The electronic circuit that translates a digital to analog signal is called as DAC. VBMB 002 contains two D/A converter using DAC 0800.
The basic microprocessor board VBMB 002 incorporates two 8-bit DAC0800. DAC0800 is a monolithic high-speed current output type. Its unique features are
1. Typical setting of time loop 2. Complementary current o/p 3. Differential o/p voltage of 20 vpp with simple resistor loads 4. Two quadrant diode range multiplexing data 5. To decoding 6. D/A conversion circuit
SOFTWARE DETAILS: ALGORITHM FOR GENERATION OF SQUARE WAVEFORM: 1. Load the data 00h to Acc and send it to DAC to produce analog output of -5v. 2. Call time delay routine 3. Load the data FFh to Acc and send it to DAC to produce analog output of +5v. 4. Time delay routine is called again 5. A square wave of amplitude 10v (p-p) is produced, when steps 1 to 4 is repeated continuously.
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PROGRAM FOR DAC: Address 4100 4102 4104 4107 4109 410B 410E Opcode & Operand 3E, 00 D3, C8 CD, 11, 41 3E, FF D3, C8 CD, 11, 41 C3, 00, 41 Label START: Mnemonics MVI A,00H OUT C8H CALL DELAY MVI A,FFH OUT C8H CALL DELAY JMP START Time delay is introduced Repeat from START again Comments Output the data to DAC to produce -5v Time delay is introduced Output of DAC to produce 5v
Delay Program 4111 4113 4115 4116 4119 411A 410D 06, 01 0E, FF 0D C2, 15, 41 05 C2, 13, 41 C9 DELAY: L1: L2: MVI B,05H MVI C,FFH DCR C JNZ L2 DCR B JNZ L1 RET Return to Main program
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SAMPLE DATA:
Result observed in CRO for DAC The amplitude and time period of Square wave form generated using DAC are DESCRIPTION Amplitude (VP-P) Time Period (ms) OBSERVED OUTPUT 10 17
EXERCISE: Execute the program with different time delay and different input to DAC and observe the results. Check the result with your manual calculation.
The amplitude and time period of Square wave form generated using DAC are DESCRIPTION Amplitude (VP-P) Time Period (ms) OBSERVED OUTPUT
RESULT: Thus the interfacing of ADC and DAC are performed using 8085 microprocessor kit.
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Fig. 6 Flow chart for Digital clock
72
EXP. NO. TITLE:
06 DIGITAL CLOCK USING 8085
Date: _________
AIM: To write an assembly language program to simulate digital clock using 8085.
THEORY: The hours, minutes and seconds are entered at the memory location 4250, 4251 and 4252 in decimal form. The entered data is converted into Hex format from decimal using a sub-routine. A delay of exactly 1 Sec is generated and after each delay, the seconds, minutes and hours information is updated. The processing of data is done in hex form and converted back into decimal before displaying.
ALGORITHM: 1. Start the program 2. Load seconds, minutes and hours info in the memory 3. Display hours, minutes and seconds 4. Convert time information into Hex format from decimal 5. Call delay routine (1Sec) 6. Increment seconds 7. if seconds is greater than 60, reset seconds to 00 and increment minutes 8. if minutes is greater than 60, reset minutes to 00 and increment hours 9. if hours is greater than 24, reset seconds, minutes and hours to 00 10. Convert time information back into Decimal format 11. Go to step 3 12. Stop the program
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PROGRAM: Address Opcode & Operand Label Mnemonics Comments
Main Program 4100 4102 4105 4106 4109 410B 410D 410E 410F 4110 4111 4112 4113 4114 4115 4118 4119 411C 411E 411F 4120 4121 4122 4125 4127 4129 412C 412E 4130 4131 06, 03 21, 50, 42 7E 32, 00, 43 0E, 0A E6, F0 07 07 07 07 57 97 82 0D C2, 13, 41 57 3A, 00, 43 E6, 0F 82 77 23 05 C2, 05, 41 3E, 90 D3, 01 21, 50, 42 06, 03 0E, 18 7E CD, 47, 41 L3: START: L1: L2: MVI B, 03 LXI H, 4250 MOV A, M STA 4300 MVI C, 0A ANI F0 RLC RLC RLC RLC MOV D, A SUB A ADD D DCR C JNZ L1 MOV D, A LDA 4300 ANI 0F ADD D MOV M, A INX H DCR B JNZ L2 MVI A, 90 OUT 01 LXI H, 4250 MVI B, 03 MVI C, 18 MOV A, M CALL C1
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Address 4134 4137 413A 413B 413D 413F 4140 4141 4144
Opcode & Operand CD, 4C, 41 CD, 67, 41 23 3E, 18 C6, 24 4F 05 C2, 30, 41 C3, 85, 41
Label
Mnemonics CALL CONVERT CALL DISPLAY INX H MVI A, 18 ADI 24 MOV C, A DCR B JNZ L3 JMP DELAY
Comments
Compare Hours, Minutes and Seconds 4147 4148 4149 414A 414B B9 C0 91 77 C9 C1: CMP C RNZ SUB C MOV M, A RET
Routine to convert data for Display 414C 414E 4150 4153 4154 4157 4159 415C 415D 415E 415F 4160 4161 4162 4165 4166 16, 00 D6, 0A DA, 57, 41 14 C3, 4E, 41 C6, 0A 32, 00, 43 7A 0F 0F 0F 0F 57 3A, 00, 43 82 C9 L02:
CONVERT:
MVI D, 00 SUI 0A JC LO2 INR D JMP LO1 ADI 0A STA 4300 MOV A, D RRC RRC RRC RRC MOV D, A LDA 4300 ADD D RET
L01:
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Address
Opcode & Operand
Label
Mnemonics
Comments
Display Routine 4167 416A 416C 416D 416E 416F 4170 4173 4176 4178 417B 417C 417F 4180 4181 4182 4184 32, 00, 43 E6, F0 07 07 07 07 CD, 7C, 41 3A, 00, 43 E6, 0F CD, 7C, 41 C9 11, C8, 41 83 5F 1A D3, 00 C9 D1: DISPLAY: STA 4300 ANI F0 RLC RLC RLC RLC CALL D1 LDA 4300 ANI 0F CALL D1 RET LX1 D, 41C8 ADD E MOV E, A LDAX D OUT 00 RET
Delay Routine (1Sec) 4185 4187 4189 418B 418D 418F 4191 4193 4195 4197 4199 419A 419C 0E, 02 3E, 30 D3, 0B 3E, 90 D3, 08 3E, 80 D3, 08 3E, 00 D3, 0B DB, 08 5F DB, 08 B3 L03: L04: DELAY: MVI C, 02 MVI, 30 OUT 0B MVI A, 90 OUT 08 MVI A, 80 OUT 08 MVI A, 00 OUT 0B IN 08 MOV E, A IN 08 ORA E
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Address 419D 41A0 41A1
Opcode & Operand C2, 93, 41 0D C2, 8B, 41
Label
Mnemonics JNZ L03 DCR C JNZ L04
Comments
Check for Seconds 41A4 41A5 41A6 41A7 41A9 41AC 41AE 2B 34 7E FE, 3C C2, 25, 41 D6, 3C 77 DCX H INR M MOV A, M CPI 3C JNZ START SUI 3C MOV M, A
Check for Minutes 41AF 41B0 41B1 41B2 41B4 41B7 41B9 2B 34 7E FE, 3C C2, 25, 41 D6, 3C 77 DCX H INR M MOV A, M CPI 3C JNZ START SUI 3C MOV M, A
Check for Hours 41BA 41BB 41BC 41BD 41BF 41C2 41C4 41C5 2B 34 7E FE, 18 C2, 25, 41 D6, 18 77 C3, 25, 41 DCX H INR M MOV A, M CPI 18 JNZ START SUI 18 MOV M, A JMP START
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Address
Opcode & Operand
Label
Mnemonics
Comments
Look Table (Codes) for display from 0 to F 41C8 41CC 41D0 41D4 0A, 9F, 49, 0D 9C, 2C, 28, 8F 08, 8C, 88, 38 6A, 19, 68, E8 DB DB DB DB
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OUTPUT:
Enter the Time information (hours, minutes and seconds) at 4250, 4251 and 4252 respectively. Execute the program and look for digital clock being displayed at the 7segment display of the microprocessor kit.
RESULT: Thus, the program for simulating digital clock in the 8085 microprocessor kit is executed and the display was verified.
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PIN DIAGRAM (8279):
CIRCUIT DIAGRAM (Keyboard and Display Interface)
80
EXP. NO. TITLE :
07 KEYBOARD AND DISPLAY INTERFACE 8279
Date: _________
AIM: To write a program to study 8279 Keyboard and display controller and also initialize 8279 for rolling message in the display.
APPARATUS REQUIRED: S.N o 1 2 3 Item Description 8085-microprocessor kit. 8279 Keyboard and display controller board Flat ribbon Cable Qty 1 1 1
THEORY: Intel 8279 is responsible for key debouncing, coding of the keyboard matrix and refreshing of the display elements in the microprocessor based system. Its main functions are:
Simultaneous Keyboard and Display operation. 3 Input modes (Scanned Keyboard mode, Scanned sensor mode and Strobed input entry mode.)
2 Output modes (8 character or 16 character display with left / right entry) Clock Pre-scaler Programmable scan timing 2-Key Lockout / N-Key Rollover mode selection Auto increment facility for easy programming.
DESCRIPTION: In the 8279 Keyboard and display interfacing, we adopt the mode in which we want to operate the keyboard and display by initializing it. The clear display command is executed to clear all the rows of the display RAM. The data to be
displayed is fetched from Display RAM and displayed at first digit of display. A counter is initialized and its value is decremented until all the values are displayed. A delay is set such that the display is made for a period. The write display RAM Command word is used it set the auto increment flag. The various command words of 8279 are:
81
KEYBOARD AND DISPLAY MODE SET: 0 0 0 D D K K K
Where, DD is the display mode and KKK is the keyboard mode.
DD: 0 0 1 1 KKK: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Encoded scan keyboard-2 key lockout. Decoded scan keyboard-2 key lockout. Encoded scan keyboard-N key lockout. Decoded scan keyboard-N key lockout. Encoded scan sensor matrix. Decoded scan sensor matrix. Strobed input encoded scan display. Strobed output decoded scan display. 0 1 0 1 8 character display-left entry. 16 character display-left entry. 8 character display-right entry. 16 character display-left entry.
CLEAR HISTORY: 1 1 0 CD CD CD CF CA
CD
CD 0 0 1 1
CD x 0 0 1
A0-3 A0-3 A0-3 A0-3
B0-3 B0-3 B0-3 B0-3
= = = =
00 (0000 0000) 00 (0000 0000) 20 (0010 0000) FF (1111 1111)
Enables clear display when CD=1, the rows of display are cleared by the code set by lower two CD bits CF-> If CF=1, FIFO status is cleared, interrupt O/P line is reset sensor RAM pointer is set to row 0.
CA-> Clear all bits has the combined effect of CD and CF. If uses the CD clearing mode on display RAM and clears FIFO status. It also resynchronizes the internal timing chain.
82
WRITE DISPLAY RAM: 1 0 0 AI A A A A
AI-> Auto Increment flag, If the AI is 1; then row address selected will be incremented after each read and write to the display RAM. AAAA-> To select, 1 of the 16 rows of display RAM.
READ FIFO STATUS DU S/E O U F N N N
NNN -> Number of characters in the FIFO. F U O S/E DU -> FIFO full. -> Error under run (occurs when CPU read empty FIFO). -> Error overrun (occurs when char try to enter the full FIFO). -> Sensor closure/Error flag for multiple closures -> Display unavailable.
READ FIFO/SENSOR RAM: 0 1 0 AI X A A A
X -> dont care. AI -> Auto increment flag irrelevant 16 scanned key mode. For the sensor matrix mode. If AI=1 then each successive read will be from subsequent row of sensor. AAA->In the scanned Keyboard mode irrelevant in sensor matrix mode if select one of the rows of sensor RAM.
83
SCANNED KEYBOARD SPECIAL ERROR MODE: 1 1 1 E X X X X
X=dont care If during a single debounced cycle, two keys are found pressed, this is considered as simultaneous multiple depression and sets error flag. This flag prevent any further writing into FIFO and set interrupt. This error flag is rest by sending the normal clear command CF=1.
PROGRAM CLOCK: 0 0 1 P P P P P
All timing and multiplexing signals for the 8279 are generated by an internal Prescaler. This Prescaler divides the external clock (pin 3) by a programmable integer. Bits PPPPP determine the value of this integer which ranges from 2 to 31. Choosing a divisor that yield 100KHZ will give the specified scan and debounce times. For instance if pin 3 of the 8279 is being cluched by 2MHZ signal, PPPPP should be set to 10100 to divide the clock by 20 to yield the proper 100KHZ operating frequency.
READ DISPLAY RAM: 0 1 1 AI A A A A
The CPU sets up the 8279 for a read of the display RAM by the first writing this command. The address bits AAAA select one the 16 rows of the display RAM. If the AI flag is set this row address will be incremented after each of the following read and write operation of display RAM. Since the same counter is used for both reading and writing this command sets the next read or write address and the sense of the auto increment mode for both operations.
DISPLAY WRITE INHIBIT/BLANKING: 1 0 1 X 1W 1W BL BL
The 1W bits can be used to mask nibble A and nibble B in applications requiring separate 4-bit display.
84
Segment Definition for 7-Segment Display:
8279 Output Data Bus Segments
A3 D7 d
A2 D6 c
A1 D5 b
A0 D4 a
B3 D3 dp
B2 D2 g
B1 D1 f
B0 D0 e
Note: It must be noted that, 0 in segment makes it glow and 1 makes it blank.
PROGRAM:
TO ACCEPT A KEY AND DISPLAY IT:
The below program accepts the key pressed in the interface board which is connected to the kit and displays the same in the display in the interface board.
ALGORITHM: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Initialize 8279 by selecting display & keyboard mode Send the command word for clearing display Send command word to select row of display ram Clear display Check for key pressing Send read FIFO ram command Input the data from FIFO ram Get display code from lookup table Display character on LED display Go to step 5
85
PROGRAM: Address 4100 4102 4104 4106 4108 410A 410C 410E 4110 4112 4113 4116 4118 411A 411D 411F 4121 4123 4125 4126 4128 4129 412B 4200 to 420F Opcode & Operand 06, 08 3E, 00 D3, C2 3E, CC D3, C2 3E, 90 D3, C2 3E, FF D3, C0 05 C2, 10, 41 DB, C2 E6, 07 CA, 16, 41 3E, 40 D3, C2 DB, C0 E6, 0F 6F 26, 42 7E D3, C0 C3, 16, 41 0C, 9F, 4A, 0B, 99, 29, 28, 8F, 08, 09, 88, 38, 6C, 1A, 68, E8. LOOP: BACK: Label Mnemonics MVI B, 08H MVI A, 00H OUT C2 MVI A, CC OUT C2 MVI A, 90 OUT C2 MVI A,FF OUT C0 DCR B JNZ BACK IN C2 ANI 07 JZ LOOP MVI A, 40 Set to send FIFO RAM OUT C2 IN C0 ANI 0F MOV L, A MVI H,42 MOV A, M OUT C0 JMP LOOP Frame memory pointer by joining 42 and Key no., from FIFO RAM Retrieve data from lookup table in memory Display data in 8279 Interface Repeat same for next key Read FIFO RAM Look for pressing of a key Clears 8 Characters of the Display Write display (select a row in display RAM) Load data to clear display Clear display RAM Comments Load count for no. of char. Mode and display set
LOOK UP TABLE for the 7-segment display code corresponding to each number starting from 0 to F in HEX.
86
RESULT: Thus the Program of Interfacing 8279 Keyboard and Display is executed and verified.
87
Fig. 8 Pin Diagram & Architecture of 8259 (PIC)
88
EXP. NO: TITLE :
08 8259 - PROGRAMMABLE INTERRUPT CONTROLLER
Date: _________
AIM: To write an assembly program to study the Characteristics of 8259 Programmable Interrupt Controller.
APPARATUS REQUIRED: S.N o 1 2 3 Item Description 8085-Microprocessor kit. 8259Programmable interrupt controller board Flat ribbon Cable Qty 1 1 1
HARDWARE DESCRIPTION: The 8259 interface board comprises of the programmable Interrupt Controller, Intel 8259. The 8259 serves as an interface between interrupt request sent from multiple I/O devices and the 8085 processor which is connected to INTR interrupt pin. Thus, it functions as a overall manager in an interrupt driven system environment.
The special features of 8259 are
Eight
level
priority
controller,
expandable
to
64
levels
and
programmable Interrupt modes. Individual request mask capability is there. The 8259 are designed to minimize the software and real time overhead in handling multilevel priority interrupts. It has several modes permitting optimization for a variety of S/M requirements. The 8259 consist of the following parts - Interrupt Mask Register (IMR), Interrupt Request Register (IRR) - Interrupt Service Register (ISR) - Priority Resolver (PR) - Data Bus Buffer - R/W Control Logic The 8259 can be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels.
89
ICW1 (Initialization Command Word One) D7 A7 D6 A6 D5 A5 D4 1 D3 LTIM D2 ADI D1 SNGL D0 IC4
D0: D1: D2:
IC4: 0=no ICW4, 1=ICW4 required SNGL: 1=Single PIC, 0=Cascaded PIC ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204, etc) 0=ISR's are 8 bytes apart (0200, 0208, etc) LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered
D3:
D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower byte is A7 A6 A5 A4 A3 A2 A1 A0
ICW2 (Initialization Command Word Two) Higher byte of ISR address (8085), or 8 bit vector address (8086). D7 A15 D6 A14 D5 A13 D4 A12 D3 A11 D2 A10 D1 A9 D0 A8
ICW3 (Initialization Command Word Three) D7 Master Slave S7 0 D6 S6 0 D5 S5 0 D4 S4 0 D3 S3 0 D2 S2 ID3 D1 S1 ID2 D0 S0 ID1
Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct interrupt
Slave mode: ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000 0100)
90
ICW4 (Initialization Command Word Four) D7 0 D6 0 D5 0 D4 SFNM D3 BUF D2 M/S D1 AEOI D0 Mode
SFNM: 1=Special Fully Nested Mode, 0=FNM M/S: 1=Master, 0=Slave
AEOI: 1=Auto End of Interrupt, 0=Normal Mode: 0=8085, 1=8086
OCW1 (Operational Command Word One) D7 M7 D6 M6 D5 M5 D4 M4 D3 M3 D2 M2 D1 M1 D0 M0
IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)
OCW2 (Operational Command Word Two) D7 R D6 SL D5 EOI D4 0 D3 0 D2 L3 D1 L2 D0 L1
Details
R 0
SL 0 1 0 0 0 1 1 1
EOI 1 1 1 0 0 1 0 0
Action Non specific EOI (L3L2L1=000) Specific EOI command (Interrupt to clear given by L3L2L1) Rotate priorities on non-specific EOI Rotate priorities in auto EOI mode set Rotate priorities in auto EOI mode clear Rotate priority on specific EOI command (resets current ISR bit) Set priority (does not reset current ISR bit) No operation
EOI
0 1
Auto rotation of priorities (L3L2L1=000)
1 0 1
Specific rotation of priorities (Lowest priority ISR=L3L2L1)
1 0
91
OCW3 (Operational Command Word Three) D7 D7 ESMM SMM 0 1 1 X 0 1 D6 ESMM D5 SMM Effect No effect Reset special mask Set special mask D4 0 D3 1 D2 MODE D1 RIR D0 RIS
92
THEORY: When one or more the Interrupt requests are received from I/O devices through the interrupt Request lines (IR0-IR7), the corresponding (IRR bits) are set in IRR register. The 8259 evaluates these requests and send an Interrupt signal to the CPU through INTR. The CPU upon receiving the Interrupt request from 8259, it responds back with an Interrupt Acknowledge signal through INTA. Upon receiving an INTA from the CPU, the highest priority bit is set in Interrupt Service Register (ISR) and the corresponding IRR bit is reset and 8259 also releases a CALL Instruction code (1100 1101) onto the 8 bit data bus through its D7-D0 pins. On receiving the opcode for CALL instruction from 8259, the processor (8085) initiates two more INTA signals to the 8259. These two INTA signals allow the 8259 to release its preprogrammed interrupt subroutine (ISR) address on to the data bus. The lower 8-bit address is released at the first INTA signal and the higher 8-bit address is released at the second INTR signal. In the AEOI (Automatic End of Interrupt) mode, the ISR bit is reset of the end of the third INTA signal otherwise the ISR bit remains set until an appropriate EOI command is issued at the end of interrupt sequence.
ALGORITHM: 1. Start the program. 2. Initialize 8259 with the following specifications a) ICW4 needed b) Single 8259 c) Address Interval of 4 bytes d) Edge triggered mode e) A7, A6, A5 = 0 0 0 f) Set Interrupt Service Address for selected as 5000H
g) 8085 mode h) Normal End of Interrupt (EOI) i) j) Non-buffered Mode (since we dont use buffers) No special fully nested mode
k) Mask all interrupts except desired interrupt (say IR0) 3. Press the selected interrupt in interface board 4. Execute ISR corresponding to selected interrupt at 5000H 5. stop the program
93
PROGRAM: Address 4100 4102 4104 4106 4108 410A 410C 410E 4110 Opcode & Operand 3E, 17 D3, C0 3E, 50 D3, C2 3E, 00 D3, C2 3E, FE D3, C2 76 Label Mnemonics MVI A, 17H OUT C0H MVI A, 50H OUT C2H MVI A, 00 OUT C2H MVI A, FE OUT C2H HLT Load value in Acc for selecting one of the eight interrupts in 8259 interface Stop the program Initialize 8259 as per the set configuration Comments
Program for ISR at 5000H 5000 5002 5004 3E, 20 D3, C0 CF MV1 A, 20H OUT C0H RST1
94
OBSERVATION:
If you press the switch IR0 (when Acc is loaded with data FE), the CPU jumps to the location 5000H. The 8259 will not accept any more interrupt at IR0, since AEOI is not set. The end of interrupt (EOI) should be given through OCW2 in ISR program at 5000H.
Upon pressing the IR0 switch in the 8259 interface board, the ISR program at 5000H automatically makes the 8085 trainer kit to get resetted.
The value loaded into Acc for selecting the interrupt request switch in 8259 interface board can be changed. Upon executing of the main program again, we can see the kit getting resetted on pressing of selected interrupt switch at the 8259 interface board.
RESULT: Thus the 8259 Interface board is connected with 8085 and its operation is understood.
95
CONTROL FORMAT: SC1 SC0 RL1 RL0 M2 M1 M0 BCD
96
EX NO: TITLE:
09 PROGRAMMABLE INTERVAL TIMER - 8253
Date: _________
AIM:
To write a program to study 8253 Timer and verify its modes of operation.
APPARATUS REQUIRED: S.N o 1 2 3 4 Item Description 8085Microprocessor kit. 8253Programmable interval timer interface board Flat ribbon Cable CRO Qty 1 1 1
Hardware Description: The 8253 is a Programmable interval timer/counter. The 8253 includes three identical 16-bit counters that can operate independently in any of the six modes. It is PQC based in a 24 pin o/p and required a single +5v Power Supply. The 8254 is an upgraded version of the 8253 and the pins are compatible.
The six different modes are:
MODE 0 - Interrupt on Terminal Count When this mode is set, the output will be low. Loading the count register with a value will cause the output to remain low and the counter will start counting down. When the counter reaches 0 the output will go high and remain high until the counter is reprogrammed. The counter will continue to count down after terminal count is reached. Writing a value to the count register during counting will stop the counter, writing a second byte starts the new count.
MODE 1 - Programmable One-Shot The output will go low, once the counter has been loaded, and will go high once terminal count has been reached. Once terminal count has been reached it can be triggered again.
97
MODE 2 - Rate Generator It is a standard divide-by-N counter. The output will be low for one period of the input clock then it will remain high for the time in the counter. This cycle will keep repeating.
MODE 3 - Square Wave Rate Generator Similar to mode 2, except the output will remain high until one half of the count has been completed and then low for the other half.
MODE 4 - Software Triggered Strobe After the mode is set the output will be high. Once the count is loaded it will start counting, and will go low once terminal count is reached.
MODE 5 - Hardware Triggered Strobe Hardware triggered strobe. Similar to mode 5, but it waits for a hardware trigger signal before starting to count. Modes 1 and 5 require the 8253 gate pin to go high in order to start counting.
----------------------------------------------------------------------------------------------MODE 0 - Interrupt on Terminal Count
Set the Channel 0 in Mode 0. Connect CLK0 to the debounce circuit and execute the following program.
Address 4100 4102 4104 4106 4108 410A 410C
Opcode & Operand 3E, 30 D3, CE 3E, 05 D3, C8 3E, 00 D3, C8 76
Label
Mnemonics MVI A,30H
Comments Set Channel-0 in Mode-0
OUT CEH MVI A,05H OUT C8H MVI A,00H OUT C8H HLT Load Lower byte of COUNT to Counter Load Higher byte of COUNT to Counter Stop the Program
Using a CRO, observe the output of Channel 0 is initially low. After giving six clock pulses, we may notice that the output goes high.
98
Mode-1 Programmable One Shot: After loading the counter, the output will remain low following the rising edge of the gate input. The output would go high on the terminal count. It is retriggered hence the output will remain low for the full count after any rising edge of gate input.
Initialize channels of 8253 in mode 1 and also initiates triggering of gate-0 and 0 goes low clock pulse after triggering the gate and goes back to high level after file clock pulses.
Address 4100 4102 4104 4106 4108 410A 41OC 410E
Opcode & Operand 3E, 32 D3, CE 3E, 05 D3, C8 3E, 00 D3, C8 D3, D0 76
Label START
Mnemonics MVI A, 32H
OUT CEH MVI A, 05H OUT C8H MVI A, 00H OUT C8H OUT D0H HLT Load LSB of Count into Counter Load MSB of Count into Counter Triggers gate0 Stop the program
Execute the grogram, give clock pulses through the denounce logic and verify using a CRO.
99
Mode-2: Rate Generator: It is a simple divide by N counter. The output will be low for one period of the input clock. The period from one output pulse to the next, equals the number of input
counts in the count register. If the count register is reloaded between output pulses, the present period will not be affected, but subsequent period will reflect the new value.
Using mode 2, let us divide the clock pulse of the channel 1 by 10. Connect the CLK1 to PCLK.
Address 4100 4102 4104 4106 4108 410A 410C
Opcode & Operand 3E, 36 D3, CE 3E, 0A D3, CA 3E, 00 D3, CA 76
Label START
Mnemonics MVI A, 36H
OUT CEH MVI A, 0AH OUT CAH MVI A, 00H OUT CAH HLT Load Lower Byte of Count To Counter Load Higher byte of Count To Counter Stop the program
In a CRO, observe continuously the Input clock to Channel-1 and output at OUT-1
100
OUTPUT:
Mode 0:
Input: 05 Clock pulse Output: Goes HIGH, after 5 clock pulses.
Mode 1:
Input: 05 Clock pulse Output: Shifted after 5 clock pulse and again shifted after 5 counts.
Mode 2:
Input: 05 Clock pulse, Clock 4th Pin, grounded 10th Pin. Output: Toggled after 5th clock pulse and this is repeated.
INPUT CLOCK Amplitude Time Period
TIMER OUTPUT Amplitude Time Period
RESULT: Thus the program for interface of programmable timer was executed and the outputs were verified.
101
Fig. 10 Pin Diagram & Internal Block diagram of 8251
102
EXP. NO: 10 TITLE:
Date: _________
8251 USART INTERFACE WITH 8085 FOR SERIAL COMM.
AIM: To establish the communication between two microprocessor systems using RS232C.
APPARATUS REQUIRED: S.N o 1 2 3 4 Item Description 8085Microprocessor kit. 8251USART Interface board Flat ribbon Cable RS-232C Cable Qty 2 2 2 1
HARDWARE DESCRIPTION: IC 8251 USART (Universal Synchronous / Asynchronous Receiver Transmitter)
The
8251
provides
an
interface
between
microprocessor
and
serial
communication device. The 8251 converts the parallel data from the processor into serial before serial transmission to external device and it converts the serially received data into parallel before sending them to the processor. The 8251 receives and transmits data in a variety of configurations including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2 stop bits. The transmitter and receiver can be designed for synchronous or asynchronous operation.
Main Features of 8251 are 1) Both Synchronous and Asynchronous operation 2) False start bit detection 3) Automatic break detect and handling 4) Clock rate 1, 16, or 64 time band rate 4) Error detection - parity, overrun and framing errors. 5) Break characters generation
The control pins with which the 8251 A communicates with the CPU are the RESET, CLK WR, RD, CS, and D0-D7
103
MODE WORD FORMAT:
COMMAND WORD FORMAT: EH IR RTS ER SBRK RXE DTR TXEN
EH IR RTS ER SBRK RE DTR TXEN
-> Enable hunt mode -> Internal reset -> Request to send -> Error reset -> Send break character -> Receive enables -> Data transmit ready -> Transmit enable
1-enable 1-Reset 1-enable RTS. 1-Reset error flag. 1-Force Txd low & 0-Normal operation. 1-Enable & 0-Disable. 1-Enable 1-Enable
104
STATUS WORD FORMAT: DST SYNDET FE OE PE TXEN RDY RXRDY TXRRDY
DSR -> It indicates that DSR is Zero. FE -> Framing Error sets when a valid stop bit is not detected and reset by ER Command. OE in Command word. PE -> Parity error, 1-Enable parity error reset by ER bit of command word. -> Overrun error reads the character before it is available. It is reset by ER bit
RS 232 C STANDARD DEFINITION: The RS 232 C specifies 9 signal pins and it specifies that DTE connecter should be a male and the demodulator should be a female the signal is divided into 4 groups. Data signals, control signals, timing signals and ground. For data lines, the voltage level +3 to 15V is defined as logic 1 and 12V corresponds to logic 0.
CONTROL SIGNAL 8251A: Obviously a USART such as the 8251 A is not directory compatible with RS 232C signal levels we can interface TTL signals of the 8251A to RS 232C signals If the Jumper in this interface and removed and the jumpers in the jumper table under CRT are inserted then this circuit will produce and accept RS232C signals.
The 8251A is used as the serial port on SDIC-86 boards. It is also used on the IBM PC synchronous communication board and on many other boards. The D0-D7 act as data bus the chip select is input is connected to an address decoder so the device is enabled when addressed.
C/D means control or data is to be write read. RD read data command. WR write data or Control command. The TXC is the transmit shift register clock input RXC is the receive shift register input when connected with another system for several communication the signals. With connect with CTS, RTS, TXD and RXD signals of that system CTS: Clear to send: Enable 8251 to transmit several data RTS: Request to send: When low, indicates that 8251 can receive serial data TXD: Transmit serial data RXD: Receive serial data.
105
MASTER PROGRAM: Address 4100 4102 4104 4106 4108 410A 410C 410E 4110 4112 4114 4116 4118 411B 411D 411F Opcode & Operand 3E, 36 D3, CE 3E, 0A D3, C8 3E, 00 D3, C8 3E, 4E D3, C2 3E, 37 D3, C2 DB, C2 E6, 04 CA, 14, 41 3E, 41 D3, C0 CF LOOP Label START Mnemonics MVI A, 36 Mode set from 8253 OUT CEH MVI A, 0A OUT C8H Timer initialization MVI A, 00 OUT C8H MVI A, 4EH Mode set for 8251 OUT C2H MVI A, 37H Command word to 8251 OUT C2H IN C2H ANI 04 JZ LOOP MVI A, 41H OUT C0H RST 1 Load the data to be transmitted serially Data is transmitted. Check for Transmitter Empty Comments
106
The two microprocessor trainer kits are connected serially via RS232 standard cable. The Master program is stored in memory location 4100H of first trainer kit (TxTransmitter End) and Slave program is stored in the memory location 4200H of second trainer kit (Rx-Receiver End).
Here Polling technique is used to send and receive the serial data.
MASTER PROGRAM ALGORITHM: 1. Start the program 2. Initialize the 8253 for clock signal generation. 3. Initialize the 8251 for mode of serial communication 4. Get the status to check whether transmitter is empty. 5. if not, Jump to step 3. 6. Transmit the loaded data & Stop the program
SLAVE PROGRAM ALGORITHM: 1. Start the program. 2. Initialize the 8253 for clock signal generation. 3. Initialize the 8251 for mode of serial communication 4. Get the status word of 8251. 5. Check whether the receiver is ready. 6. if not, Jump to step 4. 7. Receive the data in Acc and stored it in memory location 4150H. 8. Stop the program.
107
SLAVE PROGRAM: Address 4200 4202 4204 4206 4208 420A 420C 420E 4210 4212 4214 4216 4219 421B 421D 4220 Opcode & Operand 3E, 36 D3, CE 3E, 0A D3, C8 3E, 00 D3, C8 3E, 4E D3, C2 3E, 37 D3, C2 DB, C2 E6, 02 CA, 14, 42 DB, C0 32, 50, 41 CF LOOP1 Label START Mnemonics MVI A, 36 Mode set for 8253 OUT CEH MVI A, 0A OUT C8H Timer initialization MVI A, 00 OUT C8H MVI A, 4E Mode word to 8251 OUT C2H MVI A, 37 Command word to 8251. OUT C2H IN C2H ANI 02H JZ LOOP1 IN C0H STA 4150H RST 1 Store received DATA (at Acc) in the Memory Check receiver is ready Comments
Remember to first make the receiver program is executed and receiver end is kept ready for reception of the serially transmitted data.
108
OUTPUT: MICROPROCESSOR KITS Master (Tx) Slave (Rx) Transmitted data Received data stored at location 4150H DATA 41H 41H
RESULT: Thus the serial interface program for communication between two microprocessor kits using RS-232C was executed and the results are verified.
109
110
EXP. NO: 11 TITLE:
Date: _________
8255 PPI INTERFACE WITH 8085 FOR PARALLEL COMM.
AIM: To establish the parallel communication between two microprocessor kits using 8255 PPI interface.
APPARATUS REQUIRED: S.No. 1 2 3 Item Description 8085Microprocessor kit. 8255PPI Interface board Flat ribbon Cable Qty 2 2 3
HARDWARE DESCRIPTION: The Intel 8255A is a general purpose programmable I/O device which is designed for parallel communication between microprocessors and peripheral devices. It provides 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.
The 8255 allows the following three operating modes (Modes 0, 1 and 2): Mode 0 - Simple I/O mode: Ports A and B operate as either inputs or outputs and Port C is divided into two 4-bit groups either of which can be operated as inputs or outputs. Mode 1 Handshake I/O Mode: Same as Mode 0 but Port C is used for handshaking and control. Mode 2 Bidirectional I/O: Port A is bidirectional (both input and output) and Port C is used for handshaking. Port B is not used.
In the given program, Port A is used for transmission and reception of parallel data between the two microprocessor kits. Port A of 8255 interface in Tx end is selected in Mode 0 Output mode and Port A of 8255 interface in Rx end is selected in Mode 0 Input mode.
111
CONTROL WORD for I/O MODE:
BSR MODE:
112
The two microprocessor trainer kits are connected parallel through 8255 interface. The Master program is stored in memory location 4100H of first trainer kit (TxTransmitter End) and Slave program is stored in the memory location 4100H of second trainer kit (Rx-Receiver End).
Here Polling technique is used to send and receive the parallel data.
MASTER PROGRAM ALGORITHM: 1. Start the program 2. Initialize the mode format of 8255 3. Get the status to check whether transmitter is empty. 4. if not, Jump to step 3 5. Transmit the data stored in memory 6. Call delay routine 7. Check whether all data is transmitted. If not, jump to step 5 8. Stop the program
SLAVE PROGRAM ALGORITHM: 1. Start the program 2. Set the mode for 8255 3. Check whether the receiver is ready 4. Receive the data and store it in memory 5. Call delay routine 6. Check whether all data is received. If not, jump to step 4. 7. Stop the program.
113
MASTER PROGRAM (Tx): Address 4100 4102 4104 4106 4108 410A 410C 410F 4111 4114 4115 4117 411A 411B 411C 411F Opcode & Operand 3E, 82 D3, 0F 3E, 3F D3, 0C DB, 0D D6, 3F C2, 08, 41 0E, 08 21, 00, 45 7E D3, 0C CD, 50, 41 23 0D C2, 14, 41 CF TRANS: LOOP: Label Mnemonics MVI A, 82H OUT 0FH MVI A, 3FH OUT 0CH IN 0DH SUI 3FH JNZ LOOP MVI C, 08H LXI H, 4500H MOV A, M OUT 0CH CALL DELAY INX H DCR C JNZ TRANS RST1 Comments
DELAY Routine 4150 4152 4154 4155 4158 4159 415C 06, 05 1E, FF 1D C2, 54, 41 05 C2, 52, 41 C9 LOOP2: LOOP1: MVI B, 05H MVI E, FFH DCR E JNZ LOOP1 DCR B JNZ LOOP2 RET
114
PROCEDURE: 1. Load the master program in the transmitting end microprocessor kit. 2. Load the slave program in the receiver end microprocessor kit. 3. Load the block of data at memory location 4500H in the transmitting end kit. 4. Execute the slave program in the receiving end kit first. 5. Execute the master program in the transmitting end kit. 6. Check for the transfer of parallel data from Tx kit to Rx kit, by verifying the data at location 4400H in the Rx kit.
OUTPUT: MICROPROCESSOR KITS Transmitter End (Tx) Address 4500 4501 4502 4503 4504 4505 4506 4507 Data Receiver End (Rx) Address 4400 4401 4402 4403 4404 4405 4406 4407 Data
115
SLAVE PROGRAM (Rx): Address 4100 4102 4104 4106 4108 410A 410C 410F 4111 4114 4117 4119 411A 411D 411E 411F 4122 Opcode & Operand 3E, 90 D3, 0F DB, 0C D6, 3F C2, 04, 41 3E, 3F D3, 0D 0E, 08 CD, 50, 41 21, 00, 44 DB, 0C 77 CD, 50, 41 23 0D C2, 17, 41 CF RECV: CHECK: Label Mnemonics MVI A, 90H OUT 0FH IN 0CH SUI 3FH JNZ CHECK MVI A, 3FH OUT 0DH MVI C, 08H CALL DELAY LXI H, 4400H IN 0CH MOV M, A CALL DELAY INX H DCR C JNZ RECV RST1 Comments
DELAY Routine: 4150 4152 4154 4155 4158 4159 415C 06, 05 1E, FF 1D C2, 54, 41 05 C2, 52, 41 C9 LOOP2: LOOP1: MVI B, 05H MVI E, FFH DCR E JNZ LOOP1 DCR B JNZ LOOP2 RET
Note: Remember to make the program in Rx end to get executed first and receiver end is kept ready for reception of the parallel transmitted data.
116
RESULT: Thus the program for parallel communication between two microprocessor kits using 8055 was executed and the results were verified.
117
Fig. 12.1 movement of rotor for current in different windings
Fig. 12.2 Bock diagram for stepper motor interface with 8085 kit
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EXP. NO: 12 TITLE:
Date: __________
INTERFACING AND PROGRAMMING OF STEPPER MOTOR (8085)
AIM: To write a program to interface and program of stepper motor with 805.
APPARATUS REQUIRED: S.N o 1 2 3 Item Description 8085Microprocessor kit. Stepper Motor Flat ribbon Cable Qty 1 1 1
THEORY:
Stepper Motor: A DC motor, in which the rotor makes only discrete angular movements in steps, is called a Stepper Motor. The Stepper motor controlled by a microprocessor has variety of applications in control system area and in process automations like, machine tools, robotics, CNC lathes, etc.
Construction of stepper motor: There are four windings in the Stator, named as A1, B1, A2, B2 and the Rotor has three permanent magnets in it. The arrangement of stator and rotor can be seen in figure 12.1. The movement occurs in the rotor in a stepwise manner, from one equilibrium to the next.
Step size =
360__ Nr x Ns
Where, Nr is no. of pairs of poles in rotor and Ns is the no. of poles in stator Note: With Ns=4 and Nr=3; Step size in the stepper motor will be 30
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To make stepwise movement in the rotor of stepper motor, the coil windings in the stator have to be energized appropriately.
The three different schemes for step movements in rotor of a stepper motor are, a) b) c) Wave scheme 2-phase scheme Half or Mixed scheme
A. Wave Scheme: In this scheme, the coil windings (A1, B2, A2, B1) of the stator of stepper motor are cyclically excited with a DC current, to make clockwise movement in steps and in reverse order for anti-clockwise movements.
Anti Clockwise Step A1 A2 B1 1 1 0 0 2 0 0 0 3 0 1 0 4 0 0 1
B2 0 1 0 0
Step 1 2 3 4
Clockwise A1 A2 B1 0 0 1 0 1 0 0 0 0 1 0 0
B2 0 0 1 0
B. 2-Phase Scheme: In this scheme, the two adjacent coil windings (A1-B2, B2-A2, A2-B1, B1-A1) of the stator of stepper motor are cyclically excited with a DC current, to make clockwise movement in steps and in reverse order for anti-clockwise movements. Anti Clockwise Step A1 A2 B1 1 1 0 0 2 0 1 0 3 0 1 1 4 1 0 1 Clockwise A1 A2 B1 1 0 1 0 1 1 0 1 0 1 0 0
B2 1 1 0 0
Step 1 2 3 4
B2 0 0 1 1
C. Half Scheme: In this scheme, we obtain the movement of rotor in half of the original step size, by interleaving these two schemes. Note: 1 in the table indicates the supply of DC current to the stator coil winding.
120
Format of Data storage (in Lookup table) for DC current to the stator coil windings, are as follows.
D7 0
D6 0
D5 0
D4 0
D3 A1
D2 A2
D2 B1
D1 B2
Example: Data for step-1 in the 2-phase scheme (clockwise rotation) is 09
ALGORITHM: 1. Start the program. 2. Load the data (no. of steps) into B register 3. Load the address of the LOOKUP table memory to HL pair. 4. Load the data (containing current info in step-1) to Acc. 5. Send the data to Stepper motor interface. 6. Call a Delay routine. 7. Increment pointer to LOOKUP table (Address in HL pair). 8. Check whether all data have been taken from LOOKUP table 9. If not, Jump to step 4. Otherwise, Jump to step 2. 10. Stop the program.
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PROGRAM:
Address 4100 4103 4105 4106 4108 410B 410C 410D 410E 410F 4112 4113 4114 4117
Opcode & Operand 21, 50, 41 06, 04 7E D3, C0 11, 03, 03 00 1B 7B B2 C2, 0B, 41 23 05 C2, 05, 41 C3, 00, 41
Label START:
Mnemonics LXI H, 4150 MVI B, 04H
Comments Load Lookup table addr to HL Move no. of steps data to B Move data-I from Memory to Acc and send it out
REPEAT:
MOV A, M OUT C0H LXI D, 0303H
DELAY:
NOP DCX D MOV A, E ORA D JNZ DELAY INX H DCR B JNZ REPEAT JMP START Increment Data pointer Check whether all 4 steps in Lookup table is taken. If not, Jump to Repeat. If Yes, Jump to Start. Delay Program
LOOKUP Table 4150 09, 05, 06, 0A -
122
OUTPUT: Execute the program and observe the movement of stepper motor.
Note: 1. To reverse the direction of rotation in stepper motor, Change the order of stored data in LOOKUP table in reverse order. 2. To vary the speed of rotation, change the delay time in the program.
RESULT: Thus the stepper motor is interfaced with 8085 processor and program for the control of stepper motor is executed to verify the direction of rotation in both forward and reverse direction and change in speed of rotation.
123
Fig. 13 Block diagram of DC motor control
124
EXP. NO: TITLE:
13 DC MOTOR SPEED CONTROL USING 8085.
Date: _________
AIM: To write an assembly program to control the speed of DC motor using 8085 kit.
APPARATUS REQUIRED: S.N o 1 2 3 Item Description 8085Microprocessor kit. DC Motor interface card with DC motor Flat ribbon Cable Qty 1 1 1
THEORY: The measurement of speed plays a vital role in an instrumentation process control system.
Principal of Operation: The speed of the motor varies with input supply power. Hence, by varying the input voltage to the motor, the speed of DC motor can be varied. The speed measurement is based on the principle that the motor rotation is converted into pulses using optical pickup sensor and the pulses are used to decrement a counter for a known time. This count value can be calibrated to RPM, which is the standard unit for speed measurement.
This program illustrates the concept of setting the speed of DC motor and read the count value from channel-0 of the counter. To make up this functions, the following procedures to be adapted. 1. Set the DC motor speed. 2. Set the control word and initialize counter. 3. Enable the counter gate. 4. Apply 1 sec delay. (RPS) 5. Disable the counter 6. Read the counter. 7. Stop the program.
125
PROGRAM: Address 4100 4102 4104 4106 4108 410B 410D 410F 4111 4113 4115 4117 4119 411C 411E 4120 4122 4125 4127 412A Opcode & Operand 3E, FF D3, C0 3E, 00 D3, D8 CD, 2B, 41 3E, 30 D3, CE 3E, FF D3, C8 D3, C8 3E, 00 D3, D0 CD, 2B, 41 3E, 00 D3, D8 DB, C8 32, 00, 45 3E, 00 32, 01, 45 76 Label Mnemonics MVI A, 0FFH OUT C0H MVI A, 00H OUT D8H CALL DELAY MVI A, 30H OUT CEH MVI A, FFH OUT C8H OUT C8H MVI A, 00H OUT D0H CALL DELAY MVI A, 00H OUT D8H IN C8H STA 4500H MVI A, 00H STA 4501H HLT Comments Move data FFH to C reg DAC OUT port Clear acc Initialize gates as low Call delay for stable running Initialize mode as interruption terminal count Time control port Maximum data Initialize Timer port CH0 (LSB) Initialize Timer port CH0 (MSB) Clear acc Make gate high Call delay for 1 sec Clear acc Make gate low Data in from CH0 Store data in memory Clear acc Clear buffer Stop the program
1 Second DELAY Routine 412B 412D 4130 4131 4132 4133 4136 4137 413A 0E, 03 21, C3, A3 2B 7D B4 C2, 30, 41 0D C2, 2D, 41 C9 DELAY LOOP1 LOOP MVI C, 03H LXI H, A3C3H DCX H MOV A, L ORA H JNZ LOOP DCR C JNZ LOOP1 RET Move 03H to C reg Load data in HL pair Decrement HL pair addr Move L reg content to acc OR Acc content with H reg content Jump on no zero to LOOP Decrement C reg Jump on no zero Return to main program
126
OUTPUT: The determined counter value representing the speed is stored in memory location as shown below.
OUTPUT Memory Location 4500 4501 Determined counter Value
RESULT: Thus the speed of DC motor was controlled with 1 sec time delay using 8085 microprocessor kit.
127
128
129
Flow Chart:
PROGRAM (16-bit Addition): Address 4100 4101 4103 4105 4108 4109 410A 410C 410E 410F Opcode & Operand C3 74, Data1L 24, Data2L 90, 41, 50 F0 A3 74, Data1H 34, Data2H F0 80, FE HERE: Label Mnemonics CLR C MOV A, #DATA1 ADD A, #DATA2 MOV DPTR, #4150h MOVX @DPTR, A INC DPTR MOV A, #DATA1 ADDC A, #DATA2 MOVX @DPTR, A SJMP HERE Comments Clear carry Move Data1L to Acc Add Data2L with Acc Move content in 4500 to DPTR. Move data to DPTR location Increment DPTR Move Data1H to Acc Add Acc with Data2H & Carry Move from Acc to DPTR location End
130
EXP. NO: TITLE:
14 PROGRAMMING ARITHMETIC, LOGICAL AND BIT MANIPULATION USING 8051
Date: _________
AIM: To write an assembly language program for the arithmetic, logical and bit manipulation using 8051.
APPARATUS REQUIRED: S.N o 1 2 Item Description 8051Micro Controller kit. Power Supply unit Qty 1 1
(A) ARITHMETIC OPERATION:
(I) 16 BIT ADDITION: ALGORITHM: 1. Start the program. 2. Get the LSB of 1st and 2nd operands. 3. Add the LSB of the two operands and store it in memory. 4. Get the MSB of 1st and 2nd operands. 5. Add the MSB and store the result in memory 6. Stop the program.
OUTPUT OF 16-BIT ADDITION:
INPUT Address 4102 4104 410B 410D Data
OUTPUT Address 4500 4501 Data
131
Flow Chart:
PROGRAM (8-bit Subtraction): Address 4100 4101 4103 4105 4108 4109 Opcode & Operand C3 74, Data1 94, Data2 90, 45, 00 FO 80, FE HERE: Label Mnemonics CLR C MOV A, #DATA1 SUBB A, #DATA2 MOV DPTR, #4500h MOVX @DPTR, A SJMP HERE Comments Clear carry Move data1 to acc Add data2 with acc Move 4500 to DPTR. Move Acc value to DPTR location End
132
(II) 8- BIT SUBTRACTION: ALGORITHM: 1. Start the program. 2. Clear the carry flag and load the first operand in accumulator. 3. Get the 2nd operand and subtract it from accumulator. 4. Store the result in memory. 5. Stop the program.
OUTPUT OF 8-BIT Subtraction without Carry:
INPUT Address 4102 4104 Data 4500 -
OUTPUT Address Data
133
Flow Chart:
PROGRAM (8-bit Multiplication): Address 4100 4102 4105 4106 4109 410A 410B 410D 410E Opcode & Operand 74, Data1 75, F0, Data2 A4 90, 45, 00 FO A3 E5, F0 FO 80, FE HERE: Label Mnemonics MOV A, #DATA1 MOV B, #DATA2 MUL AB MOV DPTR, #4500h MOVX @DPTR, A INC DPTR MOV A, B MOVX @DPTR, A SJMP HERE Comments Move Data1 to Acc Move Data2 to Acc Multiply Acc and B Move 4500 to DPTR. Move Acc value to DPTR location INC DPTR Move B register value to Acc Move Acc value to DPTR location End
134
(III) 8-BIT MULTIPLICATION: ALGORITHM: 1. Start the program. 2. Load the 1st operand in A and 2nd operand in B. 3. Multiply A and B contents using MUL instruction. 4. Store the result in memory. 5. Stop the program.
OUTPUT OF 8-BIT Multiplication:
INPUT Address 4101 4104 Data 4500 4501
OUTPUT Address Data
135
Flow Chart:
PROGRAM (8-Bit Division): Address 4100 4102 4105 4106 4109 410A 410B 410D 410E Opcode & Operand 74, Data1 75, F0, Data2 84 90, 45, 00 FO A3 E5, F0 FO 80, FE HERE: Label Mnemonics MOV A, #DATA1 MOV B, #DATA1 DIV AB MOV DPTR, #4500h MOVX @DPTR, A INC DPTR MOV A, B MOVX @DPTR, A SJMP HERE Comments Move Dividend to Acc Move Divisor to B Divide A by B Move 4500 to DPTR. Move Acc value to DPTR location Increment DPTR Move B-reg. value to Acc Store the result End
136
(IV) 8 BIT DIVISION: ALGORITHM: 1. Start the program. 2. Get 1st operand in A and 2nd in B. 3. Divide A by B contents using division instruction. 4. Store the result in memory. 5. Stop the program.
OUTPUT OF 8-BIT Division: INPUT Address 4101 4104 Data OUTPUT Address 4500 (Quotient) 4501 (Remainder) Data
137
Flow Chart:
PROGRAM (OR): Address 4100 4102 4104 4107 4108 Opcode & Operand 74, Data1 44, Data2 90, 45, 00 FO 80, FE HERE Label Mnemonics MOV A, #DATA1 ORL A, #DATA2 MOV DPTR, #4500H MOVX @DPTR, A SJMP HERE Comments Move Data1 to Acc OR Acc and Data2 Move 4500 to DPTR. Store the result End
138
(B) LOGICAL OPERATION:
(I) OR OPERATION: ALGORITHM: 1. Start the program. 2. Load 1st operand in Accumulator. 3. Get 2nd operand and perform OR between Acc and 2nd Operand. 4. Store the result in memory. 5. Stop the program.
OUTPUT OF OR Operation: INPUT Address 4101 4103 Data OUTPUT Address 4500 Data
139
Flow Chart:
PROGRAM (AND): Address 4100 4102 4104 4107 4108 Opcode & Operand 74, Data1 54, Data2 90, 45, 00 FO 80, FE HERE: Label Mnemonics MOV A, #DATA1 ADL A, #DATA2 MOV DPTR, #4500H MOVX @DPTR, A SJMP HERE Comments Move Data1 to Acc AND Acc and Data2 Move 4500 to DPTR. Store the result End
140
(II) AND OPERATION: ALGORITHM: 1. Start the program. 2. Get 1st operand in Accumulator. 3. Get 2nd operand and perform AND accumulator content & 2nd operand 4. Store the result in memory. 5. Stop the program.
OUTPUT OF AND Operation: INPUT Address 4101 4103 Data 4500 OUTPUT Address Data
RESULT: Thus the programs involving arithmetic, logical and bit manipulation using 8051 are executed and its results are verified.
141
142
EXP NO: TITLE:
15
Date: _________
COMMUNICATION BETWEEN 8051 MICROCONTROLLER KIT AND PC
Aim: To communicate microcontroller kit and PC using the stepper motor in both forward and reverse direction with delay program.
APPARATUS REQUIRED: S.N o 1 2 3 4 Item Description 8051Micro Controller kit. Stepper Motor PC with Cross assembler software Flat Ribbon Cable & RS232C Cable Qty 1 1 1 1 Each
Theory:
The software which is used to compile (convert) the assembly language program into a machine suitable for a particular processor, is called Cross Assembler. This converted machine code is sent to the trainer kit through the serial cable (RS232) and executed in the trainer kit.
CROSS ASSEMBLER: You may use any text editor such as Notepad in Windows to edit your 8051 program. Then you can assemble and link your program so as to make it loadable to the 8051 trainer kit for its execution. ASSEMBLING: Suppose your program is ready and is now stored in the working directory where the 8051 cross assembler and the 8051 linker are in, Run X8051.exe to activate the cross assembler.
143
Figure C1 shows the user interface of the cross-assembler. In the interface, the cross assembler will prompt for inputting listing destination, input filename and output filename. You have to specify the input filename. As for others, you can skip them by just entering ENTER key. If no error is detected by the cross-assembler, an object file with extension .obj will be generated.
LINKING:
Run Link.exe to activate the linker. Figure C2 shows the user interface of the linker. The linker will prompt for inputting parameters. All you need to do is to specify the input filename. It should be an object file with extension .obj. As an example, Figure C2 shows the case that the input file is Stepper.obj. You can skip all other prompts by just entering ENTER key. If no error is detected, a binary file with extension .hex will be generated.
The assembled program will be loaded into external memory of the 8051 trainer kit through serial communication interface with PC and the same can be executed from the trainer kit.
144
Algorithm: 1. Activate the assembler program. 2. Select the COM port for serial connection and Set the baud rate. 3. Open the stepper.asm program. 4. Assemble and link the opened assembly language program. 5. Initiate the transfer of generated Hex file to the trainer kit. 6. Execute the loaded program from trainer kit. 7. Observe the movement of stepper motor in desired direction & speed. 8. Stop the program.
145
PROGRAM (To be typed in TEXT editor for Assembling): Address 4100 4100 4103 4105 4106 4108 410A 410D 410F 4111 4113 4115 4117 4119 411A 411C 411E 411F 4121 4123 4500 DB 09, 05, 06, 0A TABLE 90, 45, 00 78, 04 E0 C0, 83 C0, 82 90, FF, C0 7A, 01 79, 22 7B, FF DB, FE D9, FC DA, FA FO DO, 82 D0, 83 A3 D8, E4 80, DD DLY1: DLY2: DLY3: REPEAT: START: Opcode & Operand Label Mnemonics ORG 4100H MOV DPTR, #4500H MOV R0, #04H MOVX A, @DPTR PUSH DPH PUSH DPL MOV DPTR, #FFC0H MOV R1,#04H MOV R2, #FFH MOV R3, #FFH DJNZ R3, DLY3 DJNZ R2, DLY2 DJNZ R1, DLY1 MOVX @DPTR, A POP DPL POP DPH INC DPTR DJNZ R0, REPEAT SJMP START END Look up table Increment the DPTR Decrement R0 and Jump to REPEAT, until R0 = 00 Jump to Start Delay Program Load address to DPTR Move 04 to Ro reg Move Data from DPTR location to Acc Comments
146
Result: Thus the program for stepper mot or interface with 8051-microcontroller kit through PC was executed and its parameters like speed, direction was observed.
147
148
APPENDIX A
8085 OPCODE SHEET
149
150
8086 OPCODE SHEET
DATA TRANSFER: MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV AX, [a16] [a16], AX AX, DX AL, d8 AH, d8 [a16], AL [a16], AH AL, AH AH, AL BP, AX BX, d16 BL, d8 BH, d8 [BX], DX CX, d16 CL, d8 CH, d8 CX, DI A1, A3, 8B, B0, B4, A2, 88, 8A, 88, 8B, ___, ___ ___, ___ C2 ___ ___ ___, ___ 26, ___, ___ C4 C4 E8
BB, ___, ___ B3, ___ B7, ___ 89, 17 B9, B1, B5, 8B, ___, ___ ___ ___ CF
MOV [a16], DX MOV DX, [a16] MOV DX, d16 MOV SI, AX MOV SI, d16 MOV DI, d16
87, 16, ___, ___ 8B, 16, ___, ___ BA, ___, ___ 8B, F0 BE, ___, ___ BF, ___, ___
I/O: OUT a8, AL IN AL, a8 E6, a8 E4, a8
ARITHMETIC: ADD AL, d8 ADD AX, [a16] ADC AX, [a16] SUB AX, [a16] SBB AX, [a16] SUB AL, d8 MUL [a16] DIV [a16] DAA 04, ___ 03, 06, ___, ___ 13, 06, ___, ___ 2B, 06, ___, ___ 1B, 06, ___, ___ 2C, ___ F7, 26, ___, ___ F7, 36, ___, ___ 27
151
INC INC INC INC
BX AL SI DI
43 FE, C0 46 47 FE, CB FE, CD 49
DEC BL DEC CH DEC CX
LOGICAL: AND AL, d8 AND AX, d16 AND AH, BL OR AX, d16 OR BL, BH OR AL, AH XOR AL, AL NOT AX CMP AH, AL 24, ___ 25, ___, ___ 22, E3 0D, ___, ___ 0A, DF 0A, C4 30, C0 F7, A0 38, C4
STRING MANIPULATION MOVSB STOSB CLD STD CLI STI A4 AA FC FD FA FB
ITERATION CONTROL LOOP rel E2, rel_
EXT H/W SYNCHRONIZATION: NOP HLT BRANCHING: JMP rel JNC rel JNZ rel JZ rel CALL [a16] RET EB, 73, 75, 74, rel_ rel_ rel_ rel_ 90 F4
E8, ___, ___ C3
152
8051 OPCODE SHEET
153
154
Note:
Data Addr refers to 8-bit (direct) address of Internal RAM memory location / SFR Code Addr refers to 8-bit relative addressing from the current location
155
156
APPENDIX B
PROGRAMMING STEPS in Microprocessor Kit:
A. To Store program / Data: <Res> <Sub> <...16-bit address...>
Starting address of memory where data / Program is to be stored
<Next> <...Enter the 8-bit data / opcode...> <Next> Keep repeating the last two steps until entire data / Program is stored.
B. To Execute the stored program: <Res> <Go> <...16-bit address...> Starting address of memory where data / Program is stored <Exec> A display of letter E in the trainer kit indicates the successful execution of the program in the kit.
C. To view the Opcode / Data / Result: <Res> <Sub> <...16-bit address...> Address of memory where data is stored <Next>
Keep pressing <Next> key to view data in subsequent locations.
157

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Vidya Vikas College of Engineering and Technology

EXP. NO. TITLE:

01 (A) STUDY OF INTEL 8085 MICROPROCESSOR KIT

Aim : To study the working of Intel 8085 Microprocessor trainer kit.

Figure 1.1 Vimicros Micro-85 Microprocessor kit

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

6) AUDIO CASSETTE INTERFACE with file management.

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

Output: + 5 V @ 1.5 A + 12 V @ 150 mA - 12 V @ 150 mA + 30 V @ 250 mA (Unregulated)

11) PHYSICAL CHARACTERISTICS: Micro-85 EB PCB : 230mm x 170mm [L x B] Weight : 1 Kg.

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

Maskable interrupt connected to CPU's RST 7.5 interrupt.

Execute a particular program after selecting the address through GO command.

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

Hex key entry "0"

Hex key entry 3

ii. Retrieve data from an audiotape to memory. iii. Register key B

Hex key entry 4.

ii. Block search for a byte. iii. Register key F.

Hex key entry 5.

Hex key entry "6"

Hex key entry "7"

ii. Register key "H"

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

Hex key entry "8"

ii. Start running a particular program iii. Register key "I"

Hex key entry "9"

Hex key entry "A"

Hex key entry "B"

Hex key entry "C" Move block of memory to another block

iii. Register key SPH

Hex key entry "D"

ii. Compare two memory blocks.

Hex key entry "E"

ii. Insert bytes into memory (RAM) .

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EXP. NO. TITLE:

01 (B) STUDY OF INTEL 8086 MICROPROCESSOR

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

EC1307 Microprocessor & Application Lab - Manual

Vidya Vikas College of Engineering and Technology

Fig.2.1 Flow chart for 8-bit Addition with carry

EC1307 Microprocessor & Application Lab - Manual