The 8085 Instruction Set As I promised, in an earlier lesson, I am going to go through an in-depth explai nation of ALL the 8085

instructions.

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Intel

88888 8 8 88888 8 8 88888 8 8 8 8 0 0

000 0 0 0 8 8

88888 8 8 88888 8 8 88888 8 8

5555555 5 5 555555 5 5 555555 A

A A A A

0 0 0 0 0 0 000 0 0

AAAAAAA A A A A A A

8085A MICROPROCESSOR Instruction Set Summary

_________ _ --> X1 _ 1 _ --> X2 _ 2 _ <-- RESET OUT _ 3 _ \__/

_________ _ 40 _ Vcc (+5V) _ 39 _ HOLD <-_ 38 _ HLDA --> _

<-- SOD _ 4 _ --> SID _ 5 _ --> TRAP _ 6 _ --> RST 7.5 _ 7 _ --> RST 6.5 _ 8 _ --> RST 5.5 _ 9 _ --> INTR _ 10 ____ _ <-- INTA _ 11 _ <--> AD0 _ 12 _ <--> AD1 _ 13 _ <--> AD2 _ 14 _ <--> AD3 _ 15 _ <--> AD4 _ 16 _ <--> AD5 _ 17 _ <--> AD6 _ 18 _ 8085A

37 _ CLK (OUT) --> _ ________ 36 _ RESET IN <-_ 35 _ READY <-_ _

34 _ IO/M --> _ 33 _ S1 --> _ __ 32 _ RD --> _ __ 31 _ WR --> _ 30 _ ALE --> _ 29 _ S0 --> _ 28 _ A15 --> _ 27 _ A14 --> _ 26 _ A13 --> _ 25 _ A12 --> _ 24 _ A11 --> _ 23 _ A10 --> _

<--> AD7 _ 19 _ (Gnd) Vss _ 20

22 _ A9 --> _ 21 _ A8 -->

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Copyright (C) J.P.Bowen 1985

Instructions can be categorized according to their method of addressing the hard ware registers and/or memory.

Implied Addressing: The addressing mode of certain instructions is implied by the instruction s functi on. For example, the STC (set carry flag) instruction deals only with the carry flag, the DAA (decimal adjust accumulator) instruction deals with the accumulato r.

Register Addressing: Quite a large set of instructions call for register addressing. With these instr uctions, you must specify one of the registers A through E, H or L as well as th e operation code. With these instructions, the accumulator is implied as a secon d operand. For example, the instruction CMP E may be interpreted as 'compare the contents of the E register with the contents of the accumulator.

Most of the instructions that use register addressing deal with 8-bit values. However, a few of these instructions deal with 16-bit register pai rs. For example, the PCHL instruction exchanges the contents of the program cou nter with the contents of the H and L registers.

Immediate Addressing: Instructions that use immediate addressing have data assembled as a part of the instruction itself. For example, the instruction CPI 'C' may be interpreted as co mpare the contents of the accumulator with the letter C. When assembled, this in struction has the hexadecimal value FE43. Hexadecimal 43 is the internal represe ntation for the letter C. When this instruction is executed, the processor fetch es the first instruction byte and determines that it must fetch one more byte. T he processor fetches the next byte into one of its internal registers and then p

erforms the compare operation.

Notice that the names of the immediate instructions indicate that they use immed iate data. Thus, the name of an add instruction is ADD; the name of an add immed iate instruction is ADI.

All but two of the immediate instructions uses the accumulator as an implied ope rand, as in the CPI instruction shown previously. The MVI (move immediate) instr uction can move its immediate data to any of the working registers including the accumulator or to memory. Thus, the instruction MVI D, OFFH moves the hexadecim al value FF to the D register.

The LXI instruction (load register pair immediate) is even more unusual in that its immediate data is a 16-bit value. This instruction is commonly used to load addresses into a register pair. As mentioned previously, your program must initi alize the stack pointer; LXI is the instruction most commonly used for this purp ose. For example, the instruction LXI SP,3OFFH loads the stack pointer with the hexadecimal value 30FF.

Direct Addressing: Jump instructions include a 16-bit address as part of the instruction. For examp le, the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by r eplacing the current contents of the program counter with the new value 1000H.

Instructions that include a direct address require three bytes of storage: one f or the instruction code, and two for the 16-bit address

Register Indirect Addressing: Register indirect instructions reference nstruction MOV M,C moves the contents of stored in the H and L register pair. The r with the byte of data specified by the memory via a register pair. Thus, the i the C register into the memory address instruction LDAX B loads the accumulato address in the B and C register pair.

Combined Addressing Modes: Some instructions use a combination of addressing modes. A CALL instruction, for example, combines direct addressing and register indirect addressing. The direc t address in a CALL instruction specifies the address of the desired subroutine; the register indirect address is the stack pointer. The CALL instruction pushes the current contents of the program counter into the memory location specified

by the stack pointer.

Timing Effects of Addressing Modes: Addressing modes affect both the amount of time required for executing an instru ction and the amount of memory required for its storage. For example, instructio ns that use implied or register addressing, execute very quickly since they deal directly with the processor s hardware or with data already present in hardware r egisters. Most important, however is that the entire instruction can be fetched with a single memory access. The number of memory accesses required is the singl e greatest factor in determining execution timing. More memory accesses therefor e require more execution time. A CALL instruction for example, requires five mem ory accesses: three to access the entire instruction and two more to push the co ntents of the program counter onto the stack.

The processor can access memory once during each processor cycle. Each cycle com prises a variable number of states. (See below and the appendix of USING THE SDK85 MICROPROCESSOR TRAINER ). The length of a state depends on the clock frequency specified for your system, and may range from 480 nanoseconds to 2 microseconds. Thus, the timing for a four state instruction may range from 1.920 microseconds through 8 microseconds. (The 8085 have a maximum clock frequency of 5 MHz and t herefore a minimum state length of 200 nanoseconds.)

Instruction Naming Conventions: The mnemonics assigned to the instructions are designed to indicate the function of the instruction. The instructions fall into the following functional categori es:

Data Transfer Croup: The data transfer instructions move data between registers or between memory and registers.

MOV MVI LDA STA LHLD SHLD

Move Move Immediate Load Accumulator Directly from Memory Store Accumulator Directly in Memory Load H & L Registers Directly from Memory Store H & L Registers Directly in Memory

An 'X' in the name of a data transfer instruction implies that it deals with a r egister pair (16-bits);

LXI LDAX STAX XCHG XTHL

Load Register Pair with Immediate data Load Accumulator from Address in Register Pair Store Accumulator in Address in Register Pair Exchange H & L with D & E Exchange Top of Stack with H & L

Arithmetic Group: The arithmetic instructions add, subtract, increment, or decrement data in regis ters or memory.

ADD ADI ADC ACI SUB SUI SBB SBI INR DCR INX DCX DAD

Add to Accumulator Add Immediate Data to Accumulator Add to Accumulator Using Carry Flag Add Immediate data to Accumulator Using Carry Subtract from Accumulator Subtract Immediate Data from Accumulator Subtract from Accumulator Using Borrow (Carry) Flag Subtract Immediate from Accumulator Using Borrow (Carry) Flag Increment Specified Byte by One Decrement Specified Byte by One Increment Register Pair by One Decrement Register Pair by One Double Register Add; Add Content of Register Pair to H & L Register Pair

Logical Group: This group performs logical (Boolean) operations on data in registers and memory and on condition flags.

The logical AND, OR, and Exclusive OR instructions enable you to set specific bi

ts in the accumulator ON or OFF.

ANA ANI ORA OR XRA XRI

Logical AND with Accumulator Logical AND with Accumulator Using Immediate Data Logical OR with Accumulator Logical OR with Accumulator Using Immediate Data Exclusive Logical OR with Accumulator Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of the accumulator;

CMP CPI

Compare Compare Using Immediate Data

The rotate instructions shift the contents of the accumulator one bit position t o the left or right:

RLC RRC RAL RAR

Rotate Accumulator Left Rotate Accumulator Right Rotate Left Through Carry Rotate Right Through Carry

Complement and carry flag instructions:

CMA CMC STC

Complement Accumulator Complement Carry Flag Set Carry Flag

Branch Group: The branching instructions alter normal sequential program flow, either uncondit ionally or conditionally. The unconditional branching instructions are as follow

s:

JMP CALL RET

Jump Call Return

Conditional branching instructions examine the status of one of four condition f lags to determine whether the specified branch is to be executed. The conditions that may be specified are as follows:

NZ Z NC C PO PE P M

Not Zero (Z = 0) Zero (Z = 1) No Carry (C = 0) Carry (C = 1) Parity Odd (P = 0) Parity Even (P Plus (S = 0) Minus (S = 1) = 1)

Thus, the conditional branching instructions are specified as follows:

Jumps C INC JZ JNZ JP JM JPE JP0

Calls CC CNC CZ CNZ CP CM CPE CPO

Returns RC RNC RZ RNZ RP RM RPE RPO (Carry) (No Carry) (Zero) (Not Zero) (Plus) (Minus) (Parity Even) (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the prog ram counter:

PCHL RST

Move H & L to Program Counter Special Restart Instruction Used with Interrupts

Stack I/O, and Machine Control Instructions: The following instructions affect the Stack and/or Stack Pointer:

PUSH POP XTHL SPHL

Push Two bytes of Data onto the Stack Pop Two Bytes of Data off the Stack Exchange Top of Stack with H & L Move content of H & L to Stack Pointer

The I/0 instructions are as follows:

IN OUT

Initiate Input Operation Initiate Output Operation

The Machine Control instructions are as follows: EI DI HLT NOP Enable Interrupt System Disable Interrupt System Halt No Operation

---------------------------------------------------------------Mnemonic Op SZAPC ~s Description Notes

---------+--+-----+--+--------------------------+------------ACI n ADC r CE ***** 7 Add with Carry Immediate 8F ***** 4 Add with Carry A=A+n+CY A=A+r+CY(21X)

ADC M ADD r ADD M ADI n ANA r ANA M ANI n CALL a CC a CM a CMA CMC CMP r CMP M CNC a CNZ a CP a CPE a CPI n CPO a CZ a DAA DAD B DAD D DAD H DAD SP DCR r DCR M DCX B DCX D

8E ***** 7 Add with Carry to Memory 87 ***** 4 Add 86 ***** 7 Add to Memory C6 ***** 7 Add Immediate A7 ****0 4 AND Accumulator

A=A+[HL]+CY A=A+r A=A+[HL] A=A+n A=A&r (24X) (20X)

A6 ****0 7 AND Accumulator and Memory A=A&[HL] E6 **0*0 7 AND Immediate CD ----- 18 Call unconditional DC ----- 9 Call on Carry FC ----- 9 Call on Minus 2F ----- 4 Complement Accumulator 3F ----* 4 Complement Carry BF ***** 4 Compare BF ***** 7 Compare with Memory D4 ----- 9 Call on No Carry C4 ----- 9 Call on No Zero F4 ----- 9 Call on Plus EC ----- 9 Call on Parity Even FE ***** 7 Compare Immediate E4 ----- 9 Call on Parity Odd CC ----- 9 Call on Zero A=A&n -[SP]=PC,PC=a If CY=1(18~s) If S=1 (18~s) A=~A CY=~CY A-r A-[HL] If CY=0(18~s) If Z=0 (18~s) If S=0 (18~s) If P=1 (18~s) A-n If P=0 (18~s) If Z=1 (18~s) (27X)

27 ***** 4 Decimal Adjust Accumulator A=BCD format 09 ----* 10 Double Add BC to HL 19 ----* 10 Double Add DE to HL 29 ----* 10 Double Add HL to HL 39 ----* 10 Double Add SP to HL 3D ****- 4 Decrement 35 ****- 10 Decrement Memory 0B ----- 6 Decrement BC 1B ----- 6 Decrement DE HL=HL+BC HL=HL+DE HL=HL+HL HL=HL+SP r=r-1 (0X5)

[HL]=[HL]-1 BC=BC-1 DE=DE-1

DCX H DCX SP DI EI HLT IN p INR r INR M INX B INX D INX H INX SP JMP a JC a JM a JNC a JNZ a JP a JPE a JPO a JZ a LDA a LDAX B LDAX D LHLD a

2B ----- 6 Decrement HL 3B ----- 6 Decrement Stack Pointer F3 ----- 4 Disable Interrupts FB ----- 4 Enable Interrupts 76 ----- 5 Halt DB ----- 10 Input 3C ****- 4 Increment 3C ****- 10 Increment Memory 03 ----- 6 Increment BC 13 ----- 6 Increment DE 23 ----- 6 Increment HL 33 ----- 6 Increment Stack Pointer C3 ----- 7 Jump unconditional DA ----- 7 Jump on Carry FA ----- 7 Jump on Minus D2 ----- 7 Jump on No Carry C2 ----- 7 Jump on No Zero F2 ----- 7 Jump on Plus EA ----- 7 Jump on Parity Even E2 ----- 7 Jump on Parity Odd CA ----- 7 Jump on Zero 3A ----- 13 Load Accumulator direct

HL=HL-1 SP=SP-1

A=[p] r=r+1 (0X4)

[HL]=[HL]+1 BC=BC+1 DE=DE+1 HL=HL+1 SP=SP+1 PC=a If CY=1(10~s) If S=1 (10~s) If CY=0(10~s) If Z=0 (10~s) If S=0 (10~s) If P=1 (10~s) If P=0 (10~s) If Z=1 (10~s) A=[a]

0A ----- 7 Load Accumulator indirect A=[BC] 1A ----- 7 Load Accumulator indirect A=[DE] 2A ----- 16 Load HL Direct HL=[a] BC=nn DE=nn HL=nn SP=nn (1XX)

LXI B,nn 01 ----- 10 Load Immediate BC LXI D,nn 11 ----- 10 Load Immediate DE LXI H,nn 21 ----- 10 Load Immediate HL LXI SP,nn 31 ----- 10 Load Immediate Stack Ptr

MOV r1,r2 7F ----- 4 Move register to register r1=r2

MOV M,r MOV r,M MVI r,n MVI M,n NOP ORA r ORA M ORI n OUT p PCHL POP B POP D POP H POP PSW

77 ----- 7 Move register to Memory 7E ----- 7 Move Memory to register 3E ----- 7 Move Immediate 36 ----- 10 Move Immediate to Memory 00 ----- 4 No Operation B7 **0*0 4 Inclusive OR Accumulator B6 **0*0 7 Inclusive OR Accumulator F6 **0*0 7 Inclusive OR Immediate D3 ----- 10 Output E9 ----- 6 Jump HL indirect C1 ----- 10 Pop BC D1 ----- 10 Pop DE E1 ----- 10 Pop HL

[HL]=r (16X) r=[HL] (1X6) r=n [HL]=n (0X6)

A=Avr A=Av[HL] A=Avn [p]=A PC=[HL] BC=[SP]+ DE=[SP]+ HL=[SP]+

(26X)

F1 ----- 10 Pop Processor Status Word {PSW,A}=[SP]+

------------------------------------------------------------------------------------------------------------------------------Mnemonic Op SZAPC ~s Description Notes

---------+--+-----+--+--------------------------+------------PUSH B PUSH D PUSH H C5 ----- 12 Push BC D5 ----- 12 Push DE E5 ----- 12 Push HL -[SP]=BC -[SP]=DE -[SP]=HL

PUSH PSW F5 ----- 12 Push Processor Status Word -[SP]={PSW,A} RAL RAR RET RC RIM RM RNC RNZ 17 ----* 4 Rotate Accumulator Left 1F ----* 4 Rotate Accumulator Righ C9 ----- 10 Return D8 ----- 6 Return on Carry 20 ----- 4 Read Interrupt Mask F8 ----- 6 Return on Minus D0 ----- 6 Return on No Carry C0 ----- 6 Return on No Zero A={CY,A}<A=->{CY,A} PC=[SP]+ If CY=1(12~s) A=mask If S=1 (12~s) If CY=0(12~s) If Z=0 (12~s)

RP RPE RPO RZ RLC RRC RST z SBB r SBB M SBI n SHLD a SIM SPHL STA a STAX B STAX D STC SUB r SUB M SUI n XCHG XRA r XRA M XRI n XTHL

F0 ----- 6 Return on Plus E8 ----- 6 Return on Parity Even E0 ----- 6 Return on Parity Odd C8 ----- 6 Return on Zero 07 ----* 4 Rotate Left Circular 0F ----* 4 Rotate Right Circular C7 ----- 12 Restart 9F ***** 4 Subtract with Borrow 9E ***** 7 Subtract with Borrow

If S=0 (12~s) If P=1 (12~s) If P=0 (12~s) If Z=1 (12~s) A=A<A=->A (3X7) -[SP]=PC,PC=z A=A-r-CY A=A-[HL]-CY

DE ***** 7 Subtract with Borrow Immed A=A-n-CY 22 ----- 16 Store HL Direct 30 ----- 4 Set Interrupt Mask F9 ----- 6 Move HL to SP 32 ----- 13 Store Accumulator [a]=HL mask=A SP=HL [a]=A

02 ----- 7 Store Accumulator indirect [BC]=A 12 ----- 7 Store Accumulator indirect [DE]=A 37 ----1 4 Set Carry 97 ***** 4 Subtract 96 ***** 7 Subtract Memory D6 ***** 7 Subtract Immediate EB ----- 4 Exchange HL with DE AF **0*0 4 Exclusive OR Accumulator AE **0*0 7 Exclusive OR Accumulator EE **0*0 7 Exclusive OR Immediate CY=1 A=A-r A=A-[HL] A=A-n HL<->DE A=Axr A=Ax[HL] A=Axn (25X) (22X)

E3 ----- 16 Exchange stack Top with HL [SP]<->HL

------------+-----+--+---------------------------------------PSW S Z AC -*01 S Z A Flag unaffected/affected/reset/set Sign (Bit 7) Zero (Bit 6) Auxilary Carry (Bit 4)

P CY

P C

Parity (Bit 2) Carry (Bit 0)

---------------------+---------------------------------------a p M z n nn r Direct addressing Register indirect addressing Immediate addressing Register addressing

---------------------+---------------------------------------DB n(,n) DB 'string' DS nn DW nn(,nn) Define Byte(s) Define Byte ASCII character string Define Storage Block Define Word(s)

---------------------+---------------------------------------A B C D E H L Registers (8-bit) BC DE HL PC PSW SP Register pairs (16-bit) Program Counter register (16-bit) Processor Status Word (8-bit) Stack Pointer register (16-bit)

---------------------+---------------------------------------a nn n p r z 16-bit address/data (0 to 65535) 8-bit data/port (0 to 255) Register (X=B,C,D,E,H,L,M,A) Vector (X=0H,8H,10H,18H,20H,28H,30H,38H)

---------------------+---------------------------------------+ & ~ v x <- -> <-> [ ] Arithmetic addition/subtraction Logical AND/NOT Logical inclusive/exclusive OR Rotate left/right Exchange Indirect addressing

[ ]+ -[ ] { } ( X ) If ( ~s)

Indirect address auto-inc/decrement Combination operands Octal op code where X is a 3-bit code Number of cycles if condition true

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