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    The document describes the design of an asynchronous pipeline cache system for use in an asynchronous MIPS R3000-compatible processor. Key aspects include: - The cache is designed as a distributed message passing system using full-custom quasi delay-insensitive circuits for timing robustness, low latency, and high throughput with minimal assumptions on signal delays. - Each cache is partitioned into 16 separately pipelined cells connected by a bus system that operates at twice the cell throughput, allowing consecutive accesses to different cells at the bus rate. - The design includes two 4kB direct mapped write-through instruction and data caches that have been fabricated and tested, occupying 46mm2 in a 0.6-micron C

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    The document describes the design of an asynchronous pipeline cache system for use in an asynchronous MIPS R3000-compatible processor. Key aspects include: - The cache is designed as a distributed message passing system using full-custom quasi delay-insensitive circuits for timing robustness, low latency, and high throughput with minimal assumptions on signal delays. - Each cache is partitioned into 16 separately pipelined cells connected by a bus system that operates at twice the cell throughput, allowing consecutive accesses to different cells at the bus rate. - The design includes two 4kB direct mapped write-through instruction and data caches that have been fabricated and tested, occupying 46mm2 in a 0.6-micron C

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    6 views2 pages

    Paper Cache

    Uploaded by

    rajeshchitikena
    The document describes the design of an asynchronous pipeline cache system for use in an asynchronous MIPS R3000-compatible processor. Key aspects include: - The cache is designed as a distributed message passing system using full-custom quasi delay-insensitive circuits for timing robustness, low latency, and high throughput with minimal assumptions on signal delays. - Each cache is partitioned into 16 separately pipelined cells connected by a bus system that operates at twice the cell throughput, allowing consecutive accesses to different cells at the bus rate. - The design includes two 4kB direct mapped write-through instruction and data caches that have been fabricated and tested, occupying 46mm2 in a 0.6-micron C

    Copyright:

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    PAPER ON

    A PIPELINE DESIGN ASYNCHRONOUS CACHE SYSTEM

    Submitted by

    G.V.Vinod, Asst prof M.Prakash babu, Asst prof J.Mallikharjun, Asst prof Mail id: mallikharjunj@gmail.com

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING GODAVARI INSTITUTE OF ENGINEERING AND TECHNOLOGY RAJAHMUNDRY

    ABSTRACT

    We present the design of a pipelined cache system for use in an asynchronous MIPS R3000-compatible processor. Al- though caches have been used in a few asynchronous processors (AMULET2e, TITAC-2), these rely on timing assumptions and delay matching or differ little from conventional synchronous designs. Our cache is designed as a

    distributed message passing system and implemented with full-custom quasi delayinsensitive circuits. This design achieves timing robustness, low latency, and high

    average-case throughput by making minimal assumptions on signal delays. Each cache is partitioned into 16 separately pipelined cells. These cells are connected via a bus system that operates at about twice the throughput of the cells. Consecutive accesses to diferent cells occur at the bus throughput, while consecutive accesses to the same cell are limited by the cell through- put. The cache architecture includes two 4-kB direct mapped

    write-through caches for instructions and data. The design has been fabricated (as part of Caltech's Mini MIPS asynchronous processor). Using a ten-transistor unit cell, the entire cache system requires around 1.5 million transistors and occupies approximately 46 mm 2 in HP's 0.6-m CMOS process. Simulations indicate an expected throughput of 320 million loads per second per cache at 25C and 3.3 V with about 2.1 W power per cache; the cache system has been tested at speeds up to 180 MHz at the nominal voltage.

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