8083 ln18CuuC1lCn

The Ieatures oI INTEL 8085 are :

It is an 8 bit processor.
It is a single chip N-MOS device with 40 pins.
It has multiplexed address and data bus.(AD0-AD7).
It works on 5 Volt dc power supply.
The maximum clock Irequency is 3 MHz while
minimum Irequency is 500kHz.
It provides 74 instructions with 5 diIIerent addressing
modes.
8083 ln18CuuC1lCn
lL provldes 16 address llnes so lL can access 216 64k byLes
of memory
lL generaLes 8 blL l/C address so lL can access 28236 lnpuL
porLs
lL provldes 3 hardware lnLerrupLs18A 8S1 33 8S1 63 8S1
73ln18
lL provldes Acc one flag reglsLer 6 general purpose reglsLers
and Lwo speclal purpose reglsLers(SC)
lL provldes serlal llnes Slu SCuSo serlal perlpherals can be
lnLerfaced wlLh 8083 dlrecLly
8083 ln ulAC8AM
8083 ln uLSC8l1lCn
Some lmporLanL plns are
Au0Au7 MulLlplexed Address and daLa llnes
A8A13 1rlsLaLed hlgher order address llnes
ALL Address laLch enable ls an ouLpuL slgnallL goes hlgh
when operaLlon ls sLarLed by processor
S0S1 1hese are Lhe sLaLus slgnals used Lo lndlcaLe Lype of
operaLlon
8u 8ead ls acLlve low lnpuL slgnal used Lo read daLa from l/C
devlce or memory
W8WrlLe ls an acLlve low ouLpuL slgnal used wrlLe daLa on
memory or an l/C devlce
8083 ln uLSC8l1lCn
8LAu?1hls an ouLpuL slgnal used Lo check Lhe sLaLus of
ouLpuL devlcelf lL ls low wlll WAl1 unLll lL ls hlgh
18AlL ls an Ldge Lrlggered hlghesL prlorlLy non mask
able lnLerrupL AfLer 18A resLarL occurs and execuLlon
sLarLs from address 0024P
8S13363731hese are maskable lnLerrupLs and have
low prlorlLy Lhan 18A
ln18ln1Aln18 ls a lnLerrupL requesL slgnal afLer whlch
generaLes ln1A or lnLerrupL acknowledge slgnal
lC/M1hls ls ouLpuL pln or slgnal used Lo lndlcaLe
wheLher 8083 ls worklng ln l/C mode(lC/M1) or
Memory mode(lC/M0 )
8083 ln uLSC8l1lCn
PCLuPLuAPCLu ls an lnpuL slgnal When recelves PCLu
slgnal lL compleLes currenL machlne cycle and sLops execuLlng
nexL lnsLrucLlonln response Lo PCLu generaLes PLuA LhaL
ls PCLu Acknowledge slgnal
8LSL1 ln1hls ls lnpuL slgnalWhen 8LSL1 ln ls low p
resLarLs and sLarLs execuLlng from locaLlon 0000P
Slu Serlal lnpuL daLa ls lnpuL pln used Lo accepL serlal 1 blL
daLa
x1x2 1hese are clock lnpuL slgnals and are connecLed Lo
exLernal LCor 8C clrculL1hese are dlvlde by Lwo so lf 6 MPz ls
connecLed Lo x1x2 Lhe operaLlng frequency becomes 3 MPz
vCCvSSower supply vCC+ 3volL vSSCnu reference
8083 A8CPl1LC1u8L
1lMlnC Anu S1A1L ulAC8AM
1he operaLes wlLh reference Lo clock slgnal1he rlse and
fall of Lhe pulse of Lhe clock glves one clock cycle
Lach clock cycle ls called a 1 sLaLe and a collecLlon of several 1
sLaLes glves a machlne cycle
lmporLanL machlne cycles are
1 Cpcode feLch
2 Memory read
3 Memory wrlLe
4 l/Cpread
3 l/C wrlLe
1lMlnC Anu S1A1L ulAC8AM
Cpcode leLchlL baslcally requlres 4 1 sLaLes from 1114
1he ALL pln goes hlgh aL flrsL 1 sLaLe always
Au0Au7 are used Lo feLch Ccode and sLore Lhe lower byLe
of rogram CounLer
A8A13 sLore Lhe hlgher byLe of Lhe rogram CounLer whlle
lC/M wlll be low slnce lL ls memory relaLed operaLlon
8u wlll only be low aL Lhe Cpcode feLchlng Llme
W8 wlll be aL PlCP level slnce no wrlLe operaLlon ls done
S01S11 for Cpcode feLch cycle
1lMlnC Anu S1A1L ulAC8AM
Cpcode feLch cycle
1lMlnC Anu S1A1L ulAC8AM
Memory 8ead Cycle lL baslcally requlres 31 sLaLes from 1113
1he ALL pln goes hlgh aL flrsL 1 sLaLe always
Au0Au7 are used Lo feLch daLa from memory and sLore Lhe
lower byLe of address
A8A13 sLore Lhe hlgher byLe of Lhe address whlle lC/M wlll
be low slnce lL ls memory relaLed operaLlon
8u wlll only be low aL Lhe daLa feLchlng Llme
W8 wlll be aL PlCP level slnce no wrlLe operaLlon ls done
S00S11 for Memory read cycle
1lMlnC Anu S1A1L ulAC8AM
Memory wrlLe Cycle lL baslcally requlres 31 sLaLes from 1113
1he ALL pln goes hlgh aL flrsL 1 sLaLe always
Au0Au7 are used Lo feLch daLa from Cu and sLore Lhe
lower byLe of address
A8A13 sLore Lhe hlgher byLe of Lhe address whlle lC/M wlll
be low slnce lL ls memory relaLed operaLlon
8u wlll be PlCP slnce no read operaLlon ls done
W8 wlll be aL LCW level only when daLa feLchlng ls done
S01S10 for Memory wrlLe cycle
Su88Cu1lnL
CalculaLlon of uelay uslng 8 blL counLer
Conslder followlng example
Mvl C counL(8 blL) P 7 1 sLaLes
u uC8 C 4 1 sLaLes
!nZ u 10/7 1
8L1 101
Pere loop u ls execuLed (n1) Llmes
1hus delay ls
1dM+(counL)x n) 3
Where M noof 1 sLaLes ouLslde loop
nnoof 1 sLaLes lnslde loop
Su88Cu1lnL
Pere value of M 17 n 14
1he maxlmum delay wlll occur lf counL ls 233 or ll P
1hus 1d max 17+233x143 3384 1 sLaLes
lor 03 sec delay for a 1 sLaLe we geL
1d max03 sec x 3384 1792 sec or 1792 m sec
8083 Memory lnLerfaclng
Generally P 8085 can address 64 kB oI memory .
Generally EPROMS are used as program memory and RAM as
data memory.
We can interIace Multiple RAMs and EPROMS to single P .
Memory interIacing includes 3 steps :
1. Select the chip.
2. IdentiIy register.
3. Enable appropriate buIIer.
8083 Memory lnLerfaclng
Lxample lnLerface 2kbyLes of Memory Lo 8083 wlLh sLarLlng
address 8000P
lnlLlally we reallze LhaL 2k memory requlres 11 address llnes
(2112048) So we use A0A10
WrlLe down A13 A0
A A15 15
14 14 13 13 12 12 11 11 10 10 99 88 77 66 5 5 4 4 3 3 2 2 1 1 0 0
1 1
1 1
00
00
00
00
00
00
00
00
00
11
00
11
00
11
00
11
00
11
0 0
1 1
0 0
1 1
0 0
1 1
0 0
1 1
0 0
1 1
0 0
1 1
ADD ADD
8000H 8000H
87FFH 87FFH
8083 Memory lnLerfaclng
Address llnes A0A10 are used Lo lnLerface memory whlle
A11A12A13A14A13 are glven Lo 38 uecoder Lo provlde an
ouLpuL slgnal used Lo selecL Lhe memory chlp CSor Chlp
selecL lnpuL
MLM8 and MLMWare glven Lo 8uand W8plns of Memory
chlp
uaLa llnes u0u7 are glven Lo u0u7 plns of Lhe memory chlp
ln Lhls way memory lnLerfaclng can be achleved
8083 Memory lnLerfaclng
1he dlagram of 2k lnLerfaclng ls shown below
A15-A8
Latch
AD7-AD0
D
7
- D
0
A
7
- A
0
8085
ALE
O/M RD WR
2K Byte
Memory
Chip
WR RD
CS
A10- A
0
A
15
- A
11
3:8DECODER
8083 Memory lnLerfaclng
In this example we saw that some address lines are used Ior
interIacing while others are Ior decoding.
It is called absolute decoding.
We sometimes don`t requires that many address lines.So
we ignore them.But this may lead to shadowing or multiple
address.
This type oI decoding is called linear decoding or partial
decoding.
In partial decoding wastage oI address takes place but it
requires less hardware and cost is also less as compared with
absolute one.
8233 ln ulAC8AM
PA0 PA0- -PA7 PA7 I/O I/O Port A Pins Port A Pins
PB0 PB0- -PB7 PB7 I/O I/O Port B Pins Port B Pins
PC0 PC0- -PC7 PC7 I/O I/O Port C Pins Port C Pins
D0 D0- -D7 D7 I/O I/O Data Pins Data Pins
RESET RESET I I Reset pin Reset pin
RD RD I I Read input Read input
WR WR I I Write input Write input
A0 A0- -A1 A1 I I Address pins Address pins
CS CS I I Chip select Chip select
Vcc , Gnd Vcc , Gnd I I 5volt supply 5volt supply
8233 8LCCk ulAC8AM
8233 8LCCk ulAC8AM
uaLa 8us 8uffer lL ls an 8 blL daLa buffer used Lo lnLerface
8233 wlLh 8083 lL ls connecLed Lo u0u7 blLs of 8233
8ead/wrlLe conLrol loglclL conslsLs of lnpuLs
8uW8A0A1CS
8uW8 are used for readlng and wrlLlng on Lo 8233 and
are connecLed Lo MLM8MLMW of 8083 respecLlvely
A0A1 are orL selecL slgnals used Lo selecL Lhe parLlcular
porL
CS ls used Lo selecL Lhe 8233 devlce
lL ls conLrolled by Lhe ouLpuL of Lhe 38 decoder used Lo
decode Lhe address llnes of 8083
8233 8LCCk ulAC8AM
A A11 A A00 Selected port Selected port
00 00
Port A Port A
00 11
Port B Port B
11 00
Port C Port C
11 11
Control Register Control Register
A0,A1 decide the port to be used in 8255.
8233 8LCCk ulAC8AM
Croup A and Croup 8 ConLrol
Croup A conLrol conslsLs of orL A and orL C upper
Croup 8 conLrol conslsLs of orL A and orL C lower
Lach group ls conLrolled Lhrough sofLware
1hey recelve commands from Lhe 8u W8 plns Lo
allow access Lo blL paLLern of 8083
1he blL paLLern conslsLs of
1 lnformaLlon abouL whlch group ls operaLed
2 lnformaLlon abouL mode of CperaLlon
8233 8LCCk ulAC8AM
C81 A81hese are bldlrecLlonal 8 blL porLs each and are
used Lo lnLerface 8233 wlLh Cu or perlpherals
orL A ls conLrolled by Croup A whlle orL 8 ls conLrolled by
Croup 8 ConLrol
C81 C 1hls ls a bldlrecLlonal 8 blL porL conLrolled parLlally
by Croup A conLrol and parLlally by Croup 8 conLrol
lL ls dlvlded lnLo Lwo parLs orL C upper and orL C lower
each of a nlbble
lL ls used malnly for conLrol slgnals and lnLerfaclng wlLh
perlpherals
8233 MCuLS
Mode 0 Slmple l/C
- Any of A 8 CL and CP can be programmed as lnpuL or ouLpuL
Mode 1 l/C wlLh Pandshake
- A and 8 can be used for l/C
- C provldes Lhe handshake slgnals
Mode 2 8ldlrecLlonal wlLh handshake
- A ls bldlrecLlonal wlLh C provldlng handshake slgnals
- 8 ls slmple l/C (mode0) or handshake l/C (mode1)
8S8 (8lL SeL 8eseL) Mode
- Cnly C ls avallable for blL mode access
- Allows slngle blL manlpulaLlon for conLrol appllcaLlons
ln1L8lAClnC 8083 8233
Pere 8233 ls lnLerfaced ln Memory Mapped l/C mode
lnlLlally we wrlLe down Lhe addresses and Lhen lnLerface lL
A15 A15 14 14 13 13 12 12 11 11 10 10 99 88 77 6 6 5 5 4 4 3 3 2 2 1 1 0 0 Port Port
11 00 00 00 00 X X X X X X X X X X X X X X X X X X 0 0 0 0 A A
11 00 00 00 00 X X X X X X X X X X X X X X X X X X 0 0 1 1 BB
11 00 00 00 00 X X X X X X X X X X X X X X X X X X 1 1 0 0 CC
11 00 00 00 00 X X X X X X X X X X X X X X X X X X 1 1 1 1 CW CW
ln1L8lAClnC 8083 8233
1hus we geL addresses conslderlng don'L cares Lo be zero as
orL A 8000P
orL 8 8001P
orL C 8002P
CW8 8003P
1henwe glve A11A12A13 plns Lo A8C lnpuLs of uecoder Lo
enable 8233 or Chlp SelecL
A13 ls loglc 1 so lL ls glven Lo acLlve PlCP C1 pln A14 lC/M are
glven Lo acLlve low C28 C2A plns
CuLpuL from LaLch ls glven as A0A1 plns Lo 8233 whlle u0u7 are
glven as daLa lnpuLs
ln1L8lAClnC 8083 8233
8255
8085
3:8 decoder
74373
(AD0-AD7)
D7-D0
A0-A7
/CS
A0
A1
O0
O1
O7
A13
A12
A11
ALE
#D
W#
#D
W#
G2A G2B G1
A15
A14
IO/M
A
B
C
PA
PB
PC
ln1L8lAClnC 8083 8233
Lxample1ake daLa from 8233 porL 8Add ll P CuLpuL resulL Lo
porL A
Mvl A82P lnlLlallze 8233
Cu1 83P
LuA 81P 1ake daLa from porL 8
Aul llP Add ll P Lo daLa
Cu1 80P Cu1 8esulL Lo porL A
8S11 S1C
ln1L8lAClnC S1LL8 MC1C8 wlLh
8233
SL8lAL CCMMunlCA1lCn
Serlal CommunlcaLlons sysLems are of Lhree Lypes
Slmplex 1hls ls a one way communlcaLlon
Cnly one parLy can speak
1he oLher parLy only hears Lo Lhe flrsL one buL canL
communlcaLe
SysLem A SysLem 8
unldlrecLlonal
Transmi Transmi
tter tter
Receiver Receiver
SL8lAL CCMMunlCA1lCn
SysLem A SysLem 8
C8
Transmi Transmi
tter/Rec tter/Rec
eiver eiver
Receiver Receiver
/Transm /Transm
itter itter
HalI Duplex: It is a two way communication between two ports
provided that only party can communicate at a time.
When one party stops transmitting the other starts transmitting.
The Iirst party now acts as a receiver.
SL8lAL CCMMunlCA1lCn
C8/Anu
lull uuplex lL ls a Lwo way communlcaLlon beLween Lwo porLs
and boLh parLles can communlcaLe aL same Llme
1hus here efflclenL communlcaLlon can be esLabllshed
Transmi Transmi
tter/Rec tter/Rec
eiver eiver
Receiver Receiver
/Transm /Transm
itter. itter.
18AnSMlSSlCn lC8MA1S
Asynchronous Asynchronous Synchronous Synchronous
1. 1. It transIers one character at a It transIers one character at a
time. time.
1. 1. It transIers group oI It transIers group oI
characters at a time. characters at a time.
2. Used Ior transIer data rates 2. Used Ior transIer data rates
20KBPS 20KBPS
2. Used Ior transIer data rates 2. Used Ior transIer data rates
~20KBPS ~20KBPS
3. Start and stop bit Ior each 3. Start and stop bit Ior each
character which Iorms a Irame. character which Iorms a Irame.
3. No start and stop bit Ior 3. No start and stop bit Ior
each character. each character.
4. Two Clocks are used Ior Tx 4. Two Clocks are used Ior Tx
and Rx and Rx
4. Single clock is used Ior both 4. Single clock is used Ior both
Tx and Rx. Tx and Rx.
ln1L88u1S ln 8083
lnLerrupL ls a process where an exLernal devlce can geL Lhe
aLLenLlon of Lhe mlcroprocessor
1he process sLarLs from Lhe l/C devlce
1he process ls asynchronous
ClasslflcaLlon of lnLerrupLs
lnLerrupLs can be classlfled lnLo Lwo Lypes
Maskable lnLerrupLs (Can be delayed or 8e[ecLed)
nonMaskable lnLerrupLs (Can noL be delayed or
8e[ecLed)
ln1L88u1S ln 8083
lnLerrupLs can also be classlfled lnLo
vecLored (Lhe address of Lhe servlce rouLlne ls hard
wlred)
nonvecLored (Lhe address of Lhe servlce rouLlne needs
Lo be supplled exLernally by Lhe devlce)
An lnLerrupL ls consldered Lo be an emergency slgnal LhaL may
be servlced
1he Mlcroprocessor may respond Lo lL as soon as
posslble
ln1L88u1S ln 8083
1he 8083 has 3 lnLerrupL lnpuLs
1he ln18 lnpuL
1he ln18 lnpuL ls Lhe only nonvecLored lnLerrupL
ln18 ls maskable uslng Lhe Ll/ul lnsLrucLlon palr
8S1 33 8S1 63 8S1 73 are all auLomaLlcally vecLored
8S1 33 8S1 63 and 8S1 73 are all maskable
18A ls Lhe only nonmaskable lnLerrupL ln Lhe 8083
18A ls also auLomaLlcally vecLored
ln1L88u1S ln 8083
non vecLored lnLerrupLs
1he 8083 recognlzes 8 8LS1A81 lnsLrucLlons 8S10 8S17
Lach of Lhese would send Lhe execuLlon Lo a
predeLermlned hardwlred memory
locaLlon
#estart #estart
Instruction Instruction
Equivalent to Equivalent to
RST0 RST0 CALL 0000H CALL 0000H
RST1 RST1 CALL 0008H CALL 0008H
RST2 RST2 CALL 0010H CALL 0010H
RST3 RST3 CALL 0018H CALL 0018H
RST4 RST4 CALL 0020H CALL 0020H
RST5 RST5 CALL 0028H CALL 0028H
RST6 RST6 CALL 0030H CALL 0030H
RST7 RST7 CALL 0038H CALL 0038H
ln1L88u1 8lC8l1?
nterrupt name nterrupt name Mask Mask- -able able Vectored Vectored
TRAP TRAP No No Yes Yes
RST 7.5 RST 7.5 Yes Yes Yes Yes
RST 6.5 RST 6.5 Yes Yes Yes Yes
RST 5.5 RST 5.5 Yes Yes Yes Yes
NTR NTR YES YES NO NO
SlM lnS18uC1lCn

S
O
D
S
D
E
X
X
X
R
7
.
5
M
S
E
M
7
.
5
M
6
.
5
M
5
.
5
0 1 2 3 4 5 6 7
RST5.5 Mask
RST6.5 Mask
RST7.5 Mask
}
0 - Available
1 - Masked
Mask Set Enable
0 - gnore bits 0-2
1 - Set the masks according
to bits 0-2
Force RST7.5 Flip Flop to reset
Not Used
Enable Serial Data
0 - gnore bit 7
1 - Send bit 7 to SOD pin
Serial Out Data
SIM Instruction helps activate a particular interrupt.
It can also mask a maskable interrupt.
SlM lnS18uC1lCn
Lxample SeL Lhe lnLerrupL masks so LhaL
8S133 ls enabled 8S163 ls masked and
8S173 ls enabled
llrsL deLermlne Lhe conLenLs of Lhe accumulaLor
- Enable 5.5 bit 0 = 0
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0
- Allow setting the masks bit 3 = 1
- Don't reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0
- Don't use serial data bit 6 = 0
- Serial data is ignored bit 7 = 0
S
D
O
S
D
E
X
X
X
R
7
.
5
M
S
E
M
7
.
5
M
6
.
5
M
5
.
5
0 1 0 0 0 0 0 1
E ; Enable interrupts including NTR
MV A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SM ; Apply the settings RST masks
8lM lnS18uC1lCn
Serial Data n
RST5.5 nterrupt Pending
RST6.5 nterrupt Pending
RST7.5 nterrupt Pending
0 - Available
1 - Masked
nterrupt Enable
Value of the nterrupt Enable
Flip Flop
S
D

P
7
.
5
P
6
.
5
P
5
.
5

E
M
7
.
5
M
6
.
5
M
5
.
5
0 1 2 3 4 5 6 7
RST5.5 Mask
RST6.5 Mask
RST7.5 Mask
}
Since the 8085 has Iive interrupt lines, interrupts may occur during an
ISR and remain pending.
Using the RIM instruction, it is possible to can read the status oI the
interrupt lines and Iind iI there are any pending interrupts.