ASYNCHRONOUS DOWN COUNTER :

module asyncdown(clk,rst, z);

input clk,rst;
output [3:0]z;
reg z0,z1,z2,z3;
always @(posedge clk or posedge rst)
begin
if(rst)
z0=1'b1;
else
z0=~z0;
end
always @(posedge z0 or posedge rst)
begin
if(rst)
z1=1'b1;
else
z1=~z1;
end
always @(posedge z1 or posedge rst)
begin
if(rst)
z2=1'b1;
else
z2=~z2;
end
always @(posedge z2 or posedge rst)
begin
if(rst)
z3=1'b1;
else
z3=~z3;
end
assign z={z3,z2,z1,z0};
endmodule
module asyncdown_tb();
reg clk,t_rst;
wire [3:0]t_z;
asyncdown mygate(.clk(clk),.z(t_z),.rst(t_rst));
initial
begin

$monitor (clk,t_rst,t_z);
t_rst=1'b1;
clk=0;
#25 t_rst=1'b0;
end
always
begin
#25 clk=~clk;
end
endmodule

ASYNCHRONOUS UP COUNTER:
module asyncup(clk,rst, z);
input clk,rst;
output [3:0]z;
reg z0,z1,z2,z3;
always @(posedge clk or posedge rst)
begin
if(rst)
z0=1'b0;
else
z0=~z0;
end
always @(negedge z0 or posedge rst)
begin
if(rst)
z1=1'b0;
else
z1=~z1;
end
always @(negedge z1 or posedge rst)
begin
if(rst)
z2=1'b0;
else
z2=~z2;
end
always @(negedge z2 or posedge rst)
begin
if(rst)
z3=1'b0;

else
z3=~z3;
end
assign z={z3,z2,z1,z0};
endmodule
module asyncup_tb();
reg clk,t_rst;
wire [3:0]t_z;
asyncup do(.clk(clk),.z(t_z),.rst(t_rst));
initial
begin
$monitor (clk,t_rst,t_z);
t_rst=1'b1;
clk=0;
#25 t_rst=1'b0;
end
always
begin
#25 clk=~clk;
end
endmodule

SYNCHRONOUS DOWN COUNTER :

module syncdown(clk,clr, q);
input clk,clr;
output [3:0]q;
reg [3:0]q;
initial
begin
q=4'b1111;
end
always@(posedge clk)
begin
if (clr==0)
begin
case(q)
4'd15:q=4'd14;
4'd14:q=4'd13;

4'd13:q=4'd12;
4'd12:q=4'd11;
4'd11:q=4'd10;
4'd10:q=4'd9;
4'd9:q=4'd8;
4'd8:q=4'd7;
4'd7:q=4'd6;
4'd6:q=4'd5;
4'd5:q=4'd4;
4'd4:q=4'd3;
4'd3:q=4'd2;
4'd2:q=4'd1;
4'd1:q=4'd0;
4'd0:q=4'd15;
endcase
end
end
endmodule
module syncdown_tb();
reg clk,t_clr;
wire [3:0]t_q;
syncdown do(.clk(clk),.clr(t_clr),.q(t_q));
initial
begin
$monitor (clk,t_clr,t_q);
t_clr=1;
clk=0;
#25 t_clr=0;
end
always
begin
#25 clk=~clk;
end

endmodule

SERIES ADDER :
module seradd(a,b,rst,clk, result);
input a,b,rst,clk;
output [3:0]result;
reg [3:0]result;
reg sum,carry;
integer count;
initial count=4;
always @(negedge clk)
begin
if(rst)
begin
count=0;carry=0;result=0;
end
else
begin
if(count<4)
begin
count=count+1;
sum=a^b^carry;
carry=((a&b)|(a&carry)|(b&carry));
result={sum,result[3:1]};
end
end
end
endmodule
module seradd_tb();
reg a,b,rst,clk;
wire [3:0]result;
seradd mygate(.a(a),.b(b),.rst(rst),.clk(clk),.result(result));
initial
begin
$monitor (a,b,clk,rst,result);
clk=1'b1;
a=1'b0;b=1'b0;
#5 rst=1'b1;
#5 rst=1'b0;
#10 a=1'b0;b=1'b0;
end
always #5 clk=~clk;
always #5 a=~a;

always #10 b=~b;

endmodule
PARALLEL ADDER :
module paradd(x,y, cin, cout, sum);
input [2:0]x,y;
input cin;
output cout;
output [2:0]sum;
wire c0,c1;
assign sum[0]=x[0]^y[0]^cin;
assign sum[1]=x[1]^y[1]^c0;
assign sum[2]=x[2]^y[2]^c1;
assign c0=(x[0]&y[0])|(x[0]&cin)|(y[0]&cin);
assign cout=(x[2]&y[2])|(x[0]&c1)|(y[2]&c1);
endmodule
module paradd_tb();
reg [2:0]x,y;
reg cin;
wire [2:0]sum;
wire cout;
paradd do(.x(x),.y(y),.cin(cin),.sum(sum),.cout(cout));
initial
begin
$monitor (x,y,cin,sum,cout);
x=3'b000;
y=3'b000;
cin=0;
#10 x=3'b000;y=3'b111;
#10 x=3'b011;y=3'b101;
#10 x=3'b001;y=3'b110;
end

endmodule
INVERTER :
module inv(a, b);
input a;
output b;

assign b=~a;
endmodule

module inv_tb();
reg t_a;
wire t_b;
inv do(.a(t_a),.b(t_b));
initial
begin
$monitor (t_a,t_b);
t_a=1'b0;
#25 t_a=1'b1;
#25 t_a=1'b0;
end
endmodule

OR GATE
module or2(a, b,c);
input a,b;
output c;
assign c=a|b;
endmodule

module or2_tb();
reg t_a,t_b;
wire t_c;
or2 do(.a(t_a),.b(t_b),.c(t_c));
initial
begin
$monitor (t_a,t_b,t_c);
t_a=1'b0;t_b=1'b0;
#25 t_a=1'b0;t_b=1'b0;
#25 t_a=1'b0;t_b=1'b1;
#25 t_a=1'b1;t_b=1'b0;
#25 t_a=1'b1;t_b=1'b1;
end

endmodule
D FLIP FLOP
module df(d,clk, q,z);
input d,clk;
output q,z;
reg q;
reg z;
always@(posedge clk)
begin
if(d==0)
q=0;
else
q=1;
z=~q;
end
endmodule
module df_tb();
reg clk,t_d;
wire t_z;
wire t_q;
initial
begin
$monitor(clk,t_d,t_q,t_z);
clk=0;
t_d=1'b0;
#10 t_d=0;
#10 t_d=1;
#10 t_d=0;
#10 t_d=1;
end
always
begin
#5 clk=~clk;
end
df mygate(.d(t_d),.clk(clk),.q(t_q),.z(t_z));

endmodule
JK FLIP FLOP
module jk(j,k,clk, q,z);
input j,k,clk;
output q,z;
reg q;
reg z;
always@(posedge clk)
begin
if(j==0 & k==1)
q=0;
else if(j==1 & k==0)
q=1;
else if(j==0 & k==10)
q=q;
else if(j==1 & k==1)
q=~q;
z=~q;
end
endmodule
module jk_tb();
reg clk,t_j,t_k;
wire t_q;
wire t_z;
initial
begin
$monitor(clk,t_j,t_k,t_q,t_z);
clk=0;
t_j=1'b0;t_k=1'b0;
#10 t_j=1'b0;t_k=1'b0;
#10 t_j=1'b0;t_k=1'b1;
#10 t_j=1'b1;t_k=1'b0;
#10 t_j=1'b1;t_k=1'b1;
#10 t_j=1'b0;t_k=1'b0;
#10 t_j=1'b0;t_k=1'b1;
#10 t_j=1'b1;t_k=1'b0;
#10 t_j=1'b1;t_k=1'b1;
end
always
begin

#5 clk=~clk;
end
jk do(.j(t_j),.k(t_k),.clk(clk),.q(t_q),.z(t_z));
endmodule
T FLIP FLOP
module tf(t,clk, q,z);
input t,clk;
output q,z;
reg q;
reg z;
always@(posedge clk)
begin
if(t==0)
q=1;
else
q=0;
z=~q;
end
endmodule
module tf_tb();
reg clk,t_t;
wire t_z;
wire t_q;
initial
begin
$monitor(clk,t_t,t_q,t_z);
clk=0;
t_t=1'b0;
#10 t_t=0;
#10 t_t=1;
#10 t_t=0;
#10 t_t=1;
end
always
begin
#5 clk=~clk;
end
tf mygate(.t(t_t),.clk(clk),.q(t_q),.z(t_z));
endmodule