Features

Compatible with All of Atmels Implementations of the ASB Memory Controllers

Double Master Memory Controller or Multi-master Memory Controller Handling of up to 8 Memory Areas Defined by the Memory Controller One Chip Select Line per Memory Area Integrates Three External Memory Controllers Static Memory Controller SDRAM Controller Burst Flash Controller Additional Logic for SmartMedia and CompactFlash Support Optimized External Bus 16- or 32-bit Data Bus Up to 26-bit Address Bus, Up to 64-Mbytes Addressable Up to 8 Chip Selects, Each Reserved to One of the Eight Memory Areas Optimized Pin Multiplexing to Reduce Latencies on External Memories External Bus Sharing Feature for Support of External Masters Configurable Chip Select Assignment Burst Flash Controller or Static Memory Controller on NCS0 SDRAM Controller or Static Memory Controller on NCS1 External Master on NCS2 Static Memory Controller on NCS3, Optional SmartMedia Support Static Memory Controller on NCS4 - NCS6, Optional CompactFlash Support Static Memory Controller on NCS7

32-bit Embedded ASIC Core Peripheral External Bus Interface (EBI)

Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded memory controller of an ARMbased device. The Static Memory, SDRAM and Burst Flash Controllers are all featured external memory controllers on the EBI. These external memory controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, SDRAM and Burst Flash. The EBI also supports the CompactFlash and the SmartMedia protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to eight external devices, each assigned to eight address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to eight chip select lines (NCS0 - NCS7) and several control pins that are generally multiplexed between the different external memory controllers. The HOLD and HOLDA interface pins are reserved for sharing the external bus with an external master.

Rev. 1759BCASIC05/02

Functional Description

The EBI transfers data between the internal ASB Bus (handled by the Double Master Memory Controller or the Multi-master Memory Controller) and external memories and peripheral devices. It controls the waveforms and the parameters of the external address, data and control busses and is composed of the following elements: The Static Memory Controller (SMC) The SDRAM Controller (SDRAMC) The Burst Flash Controller (BFC) A chip select assignor that assigns an ASB address space to the external devices A multiplex controller circuit that shares the pins between the different memory controllers A bus sharing logic module to handle external master bus requests Programmable CompactFlash support logic Programmable SmartMedia support logic

Figure 1 shows the organization of the External Bus Interface. Figure 1. Organization of the External Bus Interface

External Bus Interface

SDRAM Controller Burst Flash Controller Data Address Control

ASB

Static Memory Controller

MUX Logic SmartMedia Logic CompactFlash Logic Data Address Control PIO

Address Decoder Chip Select Assignor

User Interface

Bus Sharing Logic

HOLDA HOLD

APB

External Bus Interface (EBI)

1759BCASIC05/02

External Bus Interface (EBI)

Table 1. Pin Description List

Pin Name Function EBI D0 - D15 D16 - D31 A0 - A25 HOLD HOLDA Data Bus Data Bus Address Bus Bus Hold Request Bus Hold Acknowledge SMC NCS0 - NCS7 NWR0 - NWR3 NOE NRD NUB NLB NWE NBS0 - NBS3 Chip Select Lines Write Signal Output Enable Read Signal Upper Byte Select Lower Byte Select Write Enable Byte Mask Signal EBI for CompactFlash Support CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash I/O Read CompactFlash I/O Write CompactFlash Read Not Write CompactFlash Chip Select EBI for SmartMedia Support SMCS SMOE SMWE SmartMedia Chip Select SmartMedia Output Enable SmartMedia Write Enable SDRAM Controller SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Low Low High Low Output Output Output Low Low Low Output Output Output Output Output Output Output Low Low Low Low Low Low Output Output Output Output Output Output Output Output Low Low Low Low Low Low Low Low I/O I/O Output Input Output High High Type Active Level

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Table 1. Pin Description List (Continued)

Pin Name Function Burst Flash Controller BFCK BFCS BFAVD BFBAA BFOE BFRDY BFWE Burst Flash Clock Burst Flash Chip Select Burst Flash Address Valid Burst Flash Address Advance Burst Flash Output Enable Burst Flash Ready Burst Flash Write Enable Output Output Output Output Output Input Output Low Low Low Low High Low Type Active Level

Table 2. EBI Pins and External Device Connections

Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices SMC D0 - D7 A0 A1 A2 - A9 A10 A11 A12 A13 - A15 A16 A17 A18 - A20 A21 A22 A23 - A24 A25 CS CS CS D0 - D7 D8 - D15 A0 A1 - A8 A9 A10 A11 A12 - A14 A15 A16 A17 - A19 A20 A21 A22 - A23 A24 CS CS CS D0 - D7 D8 - D15 NLB A0 A1 - A8 A9 A10 A11 A12 - A14 A15 A16 A17 - A19 A20 A21 A22 - A23 A24 CS CS CS 16-bit Static Device Burst Flash Device BFC D0 - D7 D8 - D15 A0 A1 - A8 A9 A10 A11 A12 - A14 A15 A16 A17 - A19 A20 A21 A22 - A23 A24 CS SmartMedia or NAND Flash

Pin Controller D0 - D7 D8 - D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A9 A10 A11 SDA10 A12 A13 - A15 A16/BA0 A17/BA1 A18 - A20 A21 A22 A23 - A24 A25 NCS0/BFCS NCS1/SDCS NCS2

SDRAM SDRAMC D0 - D7 D8 - D15 D16 - D31 DQM0 DQM2 A0 - A7 A8 A9 A10 A11 - A13 BA0 BA1 CS

CompactFlash SMC D0 - D7 D8 - 15 A0 A1 A2 - A9 A10 REG(3) CFRNW(1)

AD0 - AD7 CLE(4) ALE(4)

External Bus Interface (EBI)

1759BCASIC05/02

External Bus Interface (EBI)

Table 2. EBI Pins and External Device Connections (Continued)
Pins of the Interfaced Device 8-bit Static Device CS CS CS CS OE WE WE 2 x 8-bit Static Devices CS CS CS CS OE WE(5) WE(5) 16-bit Static Device CS CS CS CS OE WE NUB Burst Flash Device CK AVD BAA OE RDY WE SmartMedia or NAND Flash

Pin NCS3/SMCS NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW BFCK BFAVD BFBAA/SMWE BFOE BFRDY/SMOE BFWE SDCK SDCKE RAS CAS SDWE NWAIT Pxx
(2)

SDRAM DQM1 DQM3 CLK CKE RAS CAS WE

CompactFlash CFCS(1) CE1 CE2 OE WE IOR IOW WAIT CD1 or CD2

WE OE CE RDY

Pxx(2) Pxx
(2)

Notes:

1. Not directly connected to the CompactFlash slot. Permits the control of the bi-directional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 3. The REG signal of the CompactFlash can be driven by any of the following address bits: A24, A22 to A11. For details, see CompactFlash Support on page 9. 4. The CLE and ALE signals of the SmartMedia device may be driven by any address bits. For details, see SmartMedia Support on page 12. 5. NWR1 enables upper byte writes. NWR0 enables lower byte writes.

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Application Example
Figure 2. EBI Connections to SDRAM and Burst Flash
EBI
D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE

D0-D7

2M x 8 SDRAM
D0-D7

D8-D15

2M x 8 SDRAM
D0-D7

CS CLK CKE SDWE WE RAS CAS DQM NBS0

A0-A9, A11 A10 BA0 BA1

A2-A11, A13 SDA10 A16/BA0 A17/BA1

CS CLK CKE SDWE WE RAS CAS DQM NBS1

A0-A9, A11 A10 BA0 BA1

A2-A11, A13 SDA10 A16/BA0 A17/BA1

SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25

D16-D23 NCS0/BFCS NCS1/SDCS NCS2 NCS3 NCS4 NCS5 NCS6 NCS7

2M x 8 SDRAM
D0-D7

D24-D31

2M x 8 SDRAM
D0-D7

CS CLK CKE SDWE WE RAS CAS DQM NBS2

A0-A9, A11 A10 BA0 BA1

A2-A11, A13 SDA10 A16/BA0 A17/BA1

CS CLK CKE SDWE WE RAS CAS DQM NBS3

A0-A9, A11 A10 BA0 BA1

A2-A11, A13 SDA10 A16/BA0 A17/BA1

BFCLK BFOE BFWE BFAVD BFRDY D0-D15

2M x 16 Burst Flash
D0-D15 CE A0-A20 A1-A21

CLK OE WE AVD RDY

128K x 8 SRAM
D0-D7 D0-D7 A0-A16 A1-A17 D8-D15

128K x 8 SRAM
D0-D7 A0-A16 A1-A17

CS NRD/NOE A0/NWR0/NBS0 OE WE NRD/NOE NWR1/NBS1

CS OE WE

External Bus Interface (EBI)

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External Bus Interface (EBI)

Bus Multiplexing
The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state, while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the memory controllers. Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM controller without delaying the other external memory controller accesses. Lastly, it prevents burst accesses on the same page of a burst Flash from being interrupted, which avoids the need to restart a high-latency first access.

Static Memory Controller The Static Memory Controller (SMC) controls a 16-bit data bus, a 26-bit address bus
and the signals that control accesses to external static devices, including up to eight chip select lines. The Chip Select Register of each of the eight chip select areas configures the behavior of the SMC. It supports byte, half-word and word-aligned accesses. For all chip selects, the user can program: Data bus width to 8 bits or 16 bits Up to 128 wait states Up to 15 data float times (wait time after a read access is finished to prevent any bus contention in case the external device is too slow in releasing the bus or latches the data too long after the chip select rising edge) In the case of a 16-bit wide data bus, the user can program the SMC to control one 16-bit device (Byte Access Select Type) or two 8-bit devices in parallel that emulate a 16-bit memory (Byte Write Access Type). The read and write signal address setup and hold times at up to seven cycles An optional address setup and hold time on the Chip Select The early read protocol, which allows assertion of the read signal at the beginning of the access and thus facilitates running at 0 wait state with external devices

For further information on the Static Memory Controller 2, see the Static Memory Controller 2 datasheet, literature number 1783.

Burst Flash Controller

The Burst Flash Controller (BFC) provides an interface for external 16-bit Burst Flash devices and handles an address space of 256M bytes. It supports byte-, half-word and word-aligned accesses. The BFC also supports data bus and address bus multiplexing. Furthermore, the Burst Flash Interface supports asynchronous and burst operating modes. Two protocols are available in Burst Mode, the clock-controlled address advance protocol and the signal-controlled address advance protocol. The clock-controlled address advance protocol automatically increments the address at each clock cycle. However, in signal-controlled address advance protocol the address is incremented only when the BFBAA signal is active. The BFC clock speed is programmable to be either Master Clock or Master Clock divided by 2 or 4. Page size handling (16 bytes to 1024 bytes) is supported for Burst Flash devices unable to handle continuous burst read. The Burst Flash Controller can also be programmed to suspend and maintain the current burst. In this mode, the BFC can restart a sequential access without any additional latency. For further information on the Burst Flash Controller, refer to the Burst Flash Controller datasheet, literature number 1757. 7

1759BCASIC05/02

SDRAM Controller

The SDRAM controller supports the interface to external 16- or 32-bit SDRAM devices. It can address up to 256M bytes. The supported page size ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte, half-word and word accesses. The SDRAM controller supports a read or write burst. It also keeps track of the active row in each bank, thus maximizing SDRAM performance (i.e., the application software may be placed in one bank and data in the other banks). Additional features include multibank ping-pong access, support of self-refresh and lowpower modes, automatic refresh operations with programmable refresh rates and automatic page break when a memory boundary has been reached. For further information on the SDRAM Controller, see the SDRAM Controller datasheet, literature number 1758.

Bus Sharing

The EBI features bus sharing which enables the external bus to be shared with any external master device. The HOLD and HOLDA pins permit, respectively, the external master to request the bus and the External Bus Interface to acknowledge this request. After the HOLD assertion by the external master, the EBI hands over the bus after completion of the transfer in progress. It activates the HOLDA signal. The external master deactivates the HOLD signal when it has finished its transfers. Only EBI accesses are blocked during the period of time lost for bus arbitration. Any onchip accesses not requiring the EBI can be performed during this time. The Bus Sharing is disabled after reset and the level on the HOLD pin cannot affect the External Bus Interface behavior until the EBSEN (External Bus Sharing Enable) bit in EBI_CFGR is set. When the bus is granted to the external master, all data and address lines are tri-stated and all the chip select lines remain inactive, except the NCS2, which is tri-stated. The HOLD and HOLDA pins are multiplexed with PIO lines and are generally programmed after reset as general-purpose I/O lines. The user must appropriately program the PIO Controller before enabling the Bus Sharing feature.

Pull-up Control

The EBI permits enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16 - D31 lines can be performed by programming the appropriate PIO controller.

External Bus Interface (EBI)

1759BCASIC05/02

External Bus Interface (EBI)

CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 address space. Programming the CS4A field of the Chip Select Assignment Register to the appropriate value enables this logic. Access to an external CompactFlash device is then made by accessing the address space reserved to NCS4 (i.e., between 0x5000 0000 and 0x5FFF FFFF). When multiplexed with CFCE1 and CFCE2 signals, the NCS5 and NCS6 signals become unavailable. Performing an access within the address space reserved to NCS5 and NCS6 (i.e., between 0x6000 0000 and 0x7FFF FFFF) may lead to an unpredictable outcome. The True IDE Mode is not supported and in I/O Mode, the signal _IOIS16 is not managed. I/O Mode, Common Memory Mode and Attribute Memory Mode Within the NCS4 address space, the current transfer address is used to distinguish I/O Mode, Common Memory Mode and Attribute Mode. More precisely, the A23 bit of the transfer address is used to select I/O Mode. Any EBI address bit not required by the CompactFlash device (i.e., bit A24 or bits A22 to A11) can be used to separate Common Memory Mode and Attribute Memory Mode. Using the A22 bit, for example, leads to the address map in Figure 3. In this figure, i stands for any hexadecimal digit. Figure 3. Address Map
0x5iBF FFFF 0x5i80 0000 0x5i7F FFFF 0x5i40 0000 0x5i3F FFFF 0x5i00 0000 A23 = 1 A22 = 0 A23 = 0 A22 = 1 A23 = 0 A22 = 0 I/O Mode

Common Memory Mode

Attribute Memory Mode

Note:

In the example above, the A22 pin of the EBI can be used to drive the REG signal of the CompactFlash Device.

Read/Write Signals

In I/O Mode, the CompactFlash logic drives the Read and Write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in Common Memory Mode and Attribute Memory Mode, the SMC signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure 4 demonstrates a schematic representation of this logic. Attribute Memory Mode, Common Memory Mode and I/O Mode are supported by setting the address setup and hold time on the NCS4 chip select to the appropriate values. For details on these signal waveforms, please refer to the Static Memory Controller 2 datasheet, literature number 1783.

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Figure 4. Read/Write Command Signals

External Bus Interface
SMC
CompactFlash Logic

A23 1 1 CFIOR CFIOW

NRD_NOE NWR0_NWE 1 1 CFOE CFWE

Access Type

The CFCE1 and CFCE2 signals enable upper- and lower-byte access on the data bus of the CompactFlash device in accordance with Table 3. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the NCS4 pin. The Chip Select Register (DBW field) of the NCS4 address space must be set as shown in Table 3 to enable the required access type. The CFCE1 and CFCE2 waveforms are identical to the NCS4 waveform. For details on these waveforms and timings, refer to the Static Memory Controller 2 datasheet, literature number 1783.

Table 3. Upper- and Lower-byte Access

Access Byte R/W Access 1 Odd Byte R/W Access Half-word R/W Access 0 0 0 1 0 1 X X Dont Care/High Z Odd Byte Odd Byte Odd Byte Dont Care/High Z Even Byte 8-bit 16-bit 16-bit CFCE2 1 CFCE1 0 A0 0 D[15:8] Dont Care/High Z D[7:0] Even Byte SMC_CSR4 (DBW) 8-bit or 16-bit

Multiplexing of CompactFlash Signals on EBI Pins

Table 4 and Table 5 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 4 are strictly dedicated to the CompactFlash interface as soon as the CS4A field of the Chip Select Assignment Register is set. These pins must not be used to drive any other memory devices. The EBI pins in Table 5 remain shared between all memory areas when the CompactFlash interface is enabled (CS4A = 1).

Table 4. Dedicated CompactFlash Interface Multiplexing

CS4A = 1 Pins NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 CompactFlash Signals CFCS CFCE1 CFCE2 CS4A = 0 EBI Signals NCS4 NCS5 NCS6

10

External Bus Interface (EBI)

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External Bus Interface (EBI)

Table 5. Shared CompactFlash Interface Multiplexing with CompactFlash Interface Enabled

Access to CompactFlash Device Pins NOE/NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW Access to Other EBI Devices EBI Signals NRD/NOE NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25

Application Example

Figure 5 illustrates an example of a CompactFlash application. CFCS and CFRNW signals are not directly connected to the CompactFlash slot, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is connected to the NWAIT input of the static memory controller. For details on these waveforms and timings, refer to the Static Memory Controller 2 datasheet, literature number 1783. Figure 5. CompactFlash Application Example
EBI CF Connector

D[15:0]
DIR /OE

D[15:0]

A25/CFRNW NCS4/CFCS

_CD1 CD (PIO) _CD2

/OE

A[10:0] A22/REG

A[10:0] _REG

NOE/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW

_OE _WE _IORD _IOWR

NCS5/CFE1 NCS6/CFE2

_CE1 _CE2

CFNWAIT

_WAIT

11
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SmartMedia Support

The EBI integrates circuitry that interfaces to SmartMedia or NAND Flash devices. The SmartMedia logic is driven by the Static Memory Controller on the NCS3 address space. Programming the CS3A field in the Chip Select Assignment Register to the appropriate value enables the SmartMedia logic. Access to an external SmartMedia device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF). The SmartMedia Logic drives the Read and Write command signals of the SMC on the SMOE and SMWE signals when the NCS3 signal is active. SMOE and SMWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. For details on these waveforms, refer to the Static Memory Controller 2 datasheet, literature number 1783. The SMWE and SMOE signals are multiplexed with BFRDY and BFBAA signals of the Burst Flash Controller. This multiplexing is controlled in the MUX logic part of the EBI by the CS3A field of the Chip Select Assignment Register. This logic also controls the direction of the BFRDY/SMOE pad.

Figure 6. SmartMedia Signal Multiplexing on EBI Pins

BFC

MUX Logic

BFRDY

BFRDY_SMOE

BFBAA

BFBAA_SMWE

SMC
NCS3 NRD_NOE

SmartMedia Logic
SMOE

SMWE NWR0_NWE

EBI User Interface CS3A

12

External Bus Interface (EBI)

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External Bus Interface (EBI)

The Address Latch Enable and Command Latch Enable signals on the SmartMedia device are driven by address bits A22 and A21 of the EBI address bus. The user should note that any bits on the EBI address bus can also be used for this purpose. The command, address or data words on the data bus of the SmartMedia device are distinguished by using their address within the NCS3 address space. The Chip Enable (CE) signal of the device and the Ready/Busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not selected, preventing the device from returning to standby mode. Some functional limitation with the supported Burst Flash device will occur when the SMOE and SMWE signals are multiplexed with BFRDY and BFBAA signals (respectively) and the SmartMedia device is activated. Figure 7. SmartMedia Application Example

D[7:0] A[22:21]

AD[7:0] ALE CLE

NCS3/SMCS

Not connected

EBI SmartMedia

BFBAA/SMWE BFRDY/SMOE

NWE NOE

PIO PIO

CE R/B

13
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EBI User Interface

EBI User Interface Base Address: 0xFFFF FF60
Offset 0x00 0x04 0x08 0x0C 0x10 - 0x2C 0x30 - 0x5C 0x60 0x64 - 0x9C Register Chip Select Assignment Register Configuration Register Reserved Reserved SMC User Interface SDRAMC User Interface BFC User Interface Reserved Name EBI_CSA EBI_CFGR Access Read/Write Read/Write See SMC2 Datasheet, literature number 1783 See SDRAMC Datasheet, literature number 1758 See BFC Datasheet, literature number 1757 Reset State 0x0 0x0

14

External Bus Interface (EBI)

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External Bus Interface (EBI)

EBI Chip Select Assignment Register
Register Name: Access Type: Reset Value: Offset: Absolute Address:
31

EBI_CSA Read/Write 0x0 0x0 0xFFFF FF60

30 29 28 27 26 25 24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

4 CS4A

3 CS3A

1 CS1A

0 CS0A

CS0A: Chip Select 0 Assignment 0 = Chip Select 0 is assigned to the Static Memory Controller. 1 = Chip Select 0 is assigned to the Burst Flash Controller. CS1A: Chip Select 1 Assignment 0 = Chip Select 1 is assigned to the Static Memory Controller. 1 = Chip Select 1 is assigned to the SDRAM Controller. CS3A: Chip Select 3 Assignment 0 = Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. 1 = Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. CS4A: Chip Select 4 Assignment 0 = Chip Select 4 is assigned to the Static Memory Controller and NCS4, NCS5 and NCS6 behave as defined by the SMC. 1 = Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. Accessing the address space reserved to NCS5 and NCS6 may lead to an unpredictable outcome.

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EBI Configuration Register

Register Name: Access Type: Reset Value: Offset: Absolute Address:
31

EBI_CFGR Read/Write 0x0 0x04 0xFFFF FF64

30 29 28 27 26 25 24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

1 EBSEN

0 DBPUC

DBPUC: Data Bus Pull-Up Configuration 0 = D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM power supply. 1 = D0 - D15 Data Bus bits are not internally pulled-up. EBSEN: Bus Sharing Enable 0 = The External Bus Sharing feature is disabled. 1 = The External Bus Sharing feature is enabled.

16

External Bus Interface (EBI)

1759BCASIC05/02

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Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Companys standard warranty which is detailed in Atmels Terms and Conditions located on the Companys web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmels products are not authorized for use as critical components in life support devices or systems.

ATMEL is the registered trademark of Atmel. ARM and ARMPowered are the registered trademarks of ARM, Ltd.; SmartMedia is a trademark of Toshiba Corporation; CompactFlash is a trademark of SanDisk Corporation. Other terms and product names may be the trademarks of others.

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1759BCASIC05/02 0M