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  • Hardware Tutorial Solution 04

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    Taqi Shah
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    If the invertor delay was exactly 1ns then this would be Ok, but no two invertors are identical, so there will still be a spike though much shorter than before. The key observation is that the gate capacitances will add when we connect gates in parallel (fan-out)

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    If the invertor delay was exactly 1ns then this would be Ok, but no two invertors are identical, so there will still be a spike though much shorter than before. The key observation is that the gate capacitances will add when we connect gates in parallel (fan-out)

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    Attribution Non-Commercial (BY-NC)
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    11 views1 page

    Hardware Tutorial Solution 04

    Uploaded by

    Taqi Shah
    If the invertor delay was exactly 1ns then this would be Ok, but no two invertors are identical, so there will still be a spike though much shorter than before. The key observation is that the gate capacitances will add when we connect gates in parallel (fan-out)

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    DOC Course 112: Hardware: Tutorial 4 Solution 1.

    A 0 0 1 1 B 0 1 0 1 C 1 1 1 0 D 1 1 0 1 E 1 0 1 1 X 0 1 1 0

    It is the exclusive or circuit. 2.


    A B UNKNOWN C D E X 2 4 6 8 10 12 14 Time (ns)

    3.
    A C B E D X

    If the invertor delay was exactly 1ns then this would be Ok, but no two invertors are identical, so there will still be a spike though much shorter than before. 4. The key observation to make is that the gate capacitances will add when we connect gates in parallel (fan-out). So, if the input capacitance for a gate is C, then in the first circuit the invertor has to supply a total capacitance of 8*C. Taking the equation from lecture 5, for the change of a gates input voltage with time we have: V = 5( 1- exp(-t/RC)) So, if in practice we can take V=1 for the point where the gate has definitely switched then we can calculate the time taken to switch as: 5exp(-t/RC) = 4 exp(t/RC) = 5/4 t = R C log(5/4) so, the time taken to switch when there are eight capacitors to charge will be t= 8RClog(5/4). Now consider the second circuit. At each stage a single invertor drives just two invertors (or two nand gates at the last stage) so the time delay associated with each stage is 2RC log(5/4), and so the total delay for the second circuit is: 6RCLog(5/4). Making the assumption that Cnand=Cint (which is reasonable) the second circuit is faster.

    DOC112: Hardware Tutorial 4

    Page 3

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