Time table

8:30 to 10:00 10:00 to 11:30 11:30 to 1:00 1:30 to 3:00 3:00 to 4:30 7:00 to 8:00 8:00 to 9:00 9:00 to 10:00

Monday

FPGA DESIGN

DSP

Contrl System

DSP(lab)

FPGA DESIGN

DSP

Cntrl system

Tuesday

FPGA DESIGN

FPGA(lab)

FPGA DESIGN Dsp

Comm. system Comm. system Cntrl system Comm. sytem Dsp Cntrl systm

Wednesday

Comm.system DSP

Comm. System(lab)

Thursday

Comm system

Contrl system

Contrl sytem(lab)

Pak study

Comm. sytem Contrl system Fpga

Friday

Assignment

Saturday

Assignment

Sunday

Dsp

Comm. system