PROCEDURE FOR XILINX

ISE

SIMULATOR

GENERAL: (SIMULATION & KIT) 1. Open Xilinx9.2 software. 2. Go to File menu New project create New project Type file name click Next Device properties window will open. Specify family-SPARTAN 3 Device XC3S400 3. Click new source Select VHDL Module & Type a file name (Diff) Define Port pinsClick NextFinishYesNext New project summary wizard window will openFinish. Filename.vhd file & Design summary will be created 4. In .vhd file type the program after begin and save it. 5. Go to Processes window Synthesis-XST Check Syntax View synthesis report FOR SIMULATION: 6. Go to Source window Right click on file name (Behavioral) New sourceSelect TEST BENCH WAVEFORMType the file name (Diff) Next Next Finish. Initial Timing and Clock Wizard window will open. 7. Set the clock i/p. If no clock i/p for the program, select combinatorial button & Click Finish. 8. Set the inputs by Clicking & save it. 9. Go to Source window select Behavioral Simulation. 10. Go to Process window Select Xilinx ISE simulator simulate Behavioral model. Output window will open. Check the Output. FOR KIT IMPLEMENTATION: 6. Go to Source Window Synthesis/Implementation. 7. Go to Processes Window User ConstraintsAssign Package pins. PACE window will be opened. 8. Set i/p and o/p pin numbers by seeing the kit & save it. Then minimize the PACE window. 9. Click Implementation DesignGenerate Programming file. Gen Programming file window will be opened. 10. Click Configure Device Impact window will open. Click Finish. 11. Assign New Configure File window will open. Select Filename.bit and open.

12. Go to boundary scanRight clickprogram Apply OK. Check the output in the kit.