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Body Effect Paper
Body Effect Paper
1. Introduction
The project is based on a specific characteristic of n-channel enhancement MOSFET (nMOS) devices, known as body effect. As an extension of work that was started last year [1], this research investigates how non-zero sourcebase voltages (VSB) influence the operational characteristics of these devices. Due to the different condition of the base voltage, the cascaded nMOS transistors (logic gates) perform differently. Specifically, the voltage required to trigger (turn on or off) these logic gates is significantly altered by the presence of body effect in the transistors. Since nMOS logic design requires the use of varying transistor sizes for proper functionality, this project also includes an evaluation of multiple nMOS transistor structures (of varying size) in order to better understand the extent of body effect on such structures. Such data will assist in improving the performance of these logic devices by incorporating the body effect in the design process.
Figure 2 Transfer characteristic of nMOS transistor Figure 3 shows the ideal transfer characteristic curve for different values of VSB. Due to the body effect, changes in the source-base voltage result in changes in the threshold voltage.
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3. Test
Transistors of multiple sizes are characterized under different test conditions in order to see the extent of the body effect. The transistors are biased in the saturation region by shorting the gate to the drain and applying a drain voltage of 5 volts. The transfer characteristics (ID vs VGS) of each transistor are then measured for different values of VSB. These data result in two analyses the changes in VT with VSB (body effect), and the influence of transistor size on the body effect.
4. Results
The devices on the wafer are labeled into 12 positions. There are 2 or 3 devices in each position. These positions are shown as Figure 4:
Figure 4 Device orders on single wafer; a: Device orders, b: Final product Table 1 is the ratio (W/L) of nMOS transistor gate regions. The ratio determines the size of the transistor for our study. Table 1 Ratio of gate region Transistor W (unit) L (unit) 4 18 1&7 a 12 4 b 4 18 2&8 a 12 4 b 4 26 3&9 a 10 4.5 b 10 4 c 4 26 4 & 10 a 10 4.5 b 10 4 c 4 34 5 & 11 a 10 3.5 b 12 3.5 c 4 34 6 & 12 a 10 3.5 b 12 3.5 c
W/L 0.22 3 0.22 3 0.15 2.22 2.5 0.15 2.22 2.5 0.12 2.86 3.43 0.12 2.86 3.43
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4.1 data
Figures 5, 6, and 7 are the transfer characteristic curves (ID vs VGS) under different source-base voltages (0V to 5V). We establish an on-current level of 0.07 mA. The intersections of the x- axis and the curves provide an estimate of the threshold voltage (VT).
ID vs.VGS 9c
I (mA)
0.32 0.27 0.22 0.17 0.12 0.07 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5
V GS (V)
0.27
0.22
0.17
ID (mA)
0.12
0.07 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5
VGS (V)
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0.195
0.17
0.145
0.12
ID (mA)
0.095
0.07 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55
VGS (V)
VT
1
vs
VSB
0.9
0.8
VT (V)
0.7
0.6
0.5
VSB (V)
Figure 8 VT vs VSB
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Our results also indicate that the extent of body effect is a function of transistor size (Figure 9). An increase in the ratio (W/L) of the gate region results in a more significant increase in the threshold voltage due to body effect.
Increase in VT (%)
5. Conclusion
The results of our study confirm the influence of body effect on the performance of nMOS enhancement mode transistors. As introduced earlier, the effect is especially significant in digital logic design. For example, consider the inverter structure in Figure 10.
Figure 10 Schematic of inverter In this circuit, the VSB of the switching transistor, M2, is always zero. However, due to the saturated load configuration, the VSB of loading transistor, M1, is never zero, and has a maximum value of VDD-VT1, where VT1 is the threshold voltage of transistor M1 [1]. The inherent limitations of the saturated load configuration are clearly demonstrated by this study in that attempts to increase the output level, Vout, are countered by the corresponding increase in VT1 due to the body effect. This is especially important in cascaded systems where this output, Vout, must trigger subsequent devices. Although the body effect cannot be eliminated, an estimation of its impact on varying transistor sizes may lead to design modifications that minimize the impact of the body effect on the overall performance of the device.
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6. References
1. Wei-Han Jeng and Kan Banchusuwan, The Design and Realization of nMOS Digital Devices , NCUR 2004 Proceedings, April 2004. 2. Jaeger, R.C. and Blalock, T.N., Microelectronic Circuit Design, 2nd ed. (2004), McGraw Hill, New York, New York, pp. 195-96, pp. 377-407. 3. Jaeger, R.C., Introduction to Microelectronic Fabrication, 2nd ed. (2002), Vol. V of the Modular Series on Solid State Devices, Prentice Hall, Upper Saddle River, New Jersey, pp. 49, pp. 53, pp. 217. 4. Gau and Boet, Microelectronic Fabrication, 2004 St. Cyr French Military Academy Training at VMI 5. Sung-Mo Kang, CMOS DIGITAL INTEGRATED CIRCUITS, 2nd ed. (1999), McGraw Hill, New York, New York, pp. 73-79.
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