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Reset

Sync-Out

Test Memory Control Output

10

Clk Phase 2

CM-ROM

11

Clk Phase 1

CM-RAM3

13

i4004

V DD

12

V SS

D3

CM-RAM2 Memory Control Outputs CM-RAM1

14

D2

Data Bus I/O 15 2


D1

CM-RAM0

16

D0

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