17/06/2021 CLK_0026

Rule: CLK_0026

Clock clock is used as

data. One or more sources of the clock fans out to a register data pin or to a
constrained primary output or
inout port.

Severity: Warning

Description

The clock is used as data in the design. This can cause

multiple problems during optimization, clock tree synthesis, and testing.
Clock signals have a high fanout. When they are used as data this can cause large transition time violations in data paths which
cannot be fixed by optimization tools. Also, if the data paths are not identified the clock tree synthesis runtime and quality can be
adversely impacted. When the clock signals drive the data pin of registers, a race condition is created between the data pin and
the clock pin of the registers. The race conditions may lead to the creation of poor test patterns or low test coverage.

Risk Associated with Violation

Clocks used as data may cause large transition time violations which cannot be fixed during optimization; this can increase
runtime or degrade quality during clock tree synthesis. It can also result in poor test pattern generation or low test coverage for
design testing.

One Possible Scenario

Consider a scenario where a clock signal drives register

data pins and register clock pins. At register ‘ff2’ the clock signal
‘CLK’
appears as data at the data pin and as clock at the clock pin.

Figure 1: Clock Signal Driving Register

Data Pins and Register Clock Pins

create_clock -name CLK -period 1 [get_ports CLK]

set_output_delay -clock CLK 0.5 [all_outputs]

What Next

The "Violation Details" section provides the name of the clock that is being used as data and the clock source locations. Use the
analyze_clock_networks command to get more detail about the data signals as shown in the report below:

ptc_shell> analyze_clock_networks -from [get_clocks CLK]

-end_type data
    
****************************************
Report : analyze_clock_networks
        -max_endpoints=1000
        -style short
        -end_types  {data}
Design : CLK_0006
Scenario: default
Version: …
Date   : …
****************************************
Clock Network End Type Abbreviations:
   D - data
                        End
Example End Pin/Port    Type Clocks            Count
----------------------------------------------------
ff2/D (FD1)              D    set 0              1
   
Clock Sets:
  set 0 (1 clocks):

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17/06/2021 CLK_0026
    CLK - positive, negative

The report generated using the analyze_clock_networks command shows there is a data path that originates from the clock port
CLK and terminates at the register data pin ff2/D. For more detail about this particular data path, use the -to [get_pins ff2/D]
option, the -style full option, and the -end_types data option as shown below:

ptc_shell> analyze_clock_networks -from [get_clocks CLK]

-end_type data -to [get_pins
ff2/D] -style full
   
****************************************
Report : analyze_clock_networks
        -max_endpoints=1000
        -style full
        -end_types  {data}
Design : CLK_0006
Scenario: default
Version: …
Date   : …
****************************************
Clock Sense Abbreviations:
   P - positive
   P,N - positive, negative
Clock Network End Type Abbreviations:
   D - data
   
Full report for clock: CLK
   
Branch 0:
       Branch
Level  Info     Sense Notes     Port/Pin
------------------------------------------------------------
    0           P     source    CLK (in)
    1           P               xor1/A (EO)
    2           P,N             xor1/Z (EO)
    3           P,N   D         ff2/D (FD1)

The report shows a data path from the port CLK through the XOR gate xor1 to the register data pin ff2/D.

Fix Suggestion

Check if the clock needs to be used as both data and clock. If possible, modify the design so the clock is not used as data. If the
clock must be used as both clock and data, consider using clock isolation logic so the data paths and clock paths are separated. A
simple clock isolation solution using a two-phase shifted clock divider is shown below:

Figure 2: Simple Clock

Isolation Logic Using Two Phase-Shifted Clock
Dividers

See Also

create_clock
analyze_clock_networks

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