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8086/8088 Microprocessor: Introduction To The Processor and Its Pin Configuration
8086/8088 Microprocessor: Introduction To The Processor and Its Pin Configuration
Topics
Basic Features Pinout Diagram Minimum and Maximum modes Description of the pins
Basic Features
8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus Both manufactured using High-performance Metal Oxide Semiconductor (HMOS) technology Both contain about 29000 transistors Both are packaged in 40 pin dual-in-line package (DIP)
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8086
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET
GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8088
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET
8088
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8086
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET
8086
Maximum mode
Pull MN/MX logic 0 Larger systems with more than one processor (designed to be used when a coprocessor (8087) exists in the system)
8086
Vcc
8086
GND
Min Mode
Max Mode
5 V R E S
C lo c k g e n e r a t o
A A E E F C/ N N 2 1
C R R
L K E A E S
D E
Y T
M I O / I N T A R D W R M NM /X + 5 V
C B
o n t r o l u s
W G
a it - S t a t e e n e r a t o r
L E
S O
T E
A A
1 9
8086 C PU
A A
D 0 - A D 1 5 1 6 - A 1 9 B H E
8 2 8 2 L a t c h
d d r e s s
D 8 2 8 6 D D TR / E N T O E
0 1 6
1 5
8288 B u s C o n tr o lle r
lo c k e n e r a
R R
M N S S S
/X 0 1 2
n d S S S 0 1 2
M M A I O I O A I N M
R W
D T W R W C C W
C C C
I O T A
W G
a it - S t a t e e n e r a t o r
8086 C PU
S O
T E
A A
0 d B
1 9 B u s
A A
D 0 - A D 1 5 1 6 - A 1 9
8 2 8 2 L a t c h
d r e s s H E
T O
T
D
r
T A
8 2 8 6 r a n s c e i v e
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8086
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET
Vcc
GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8086
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET
GND
Min Mode
Max Mode
Function
Extra segment access Stack segment access Code segment access Data segment access
0 0 1 1
0 1 0 1
QS1 0 0 1 1
QS1 0 1 0 1
Characteristics No operation First byte of opcode from queue Empty the queue Subsequent byte from queue
H A d
ig d
r e B a n k ( 5 1 2 KB O D D A A 1 d D - A 1 9 d r e s s a t a B D 8 u s s ( D - D
r s s Hx E8 )
o w A d d B a n ( 5 1 2 E V E D 0
r )
r e s s k K A 0x 8 N - D 7
B u
x x x
+ + +
1 3 5 x
x + + 2 4 x
1 - A
1 9
8 - D
B H 1 5
E =
1 D 0 - D 7
0 - D
1 5
x x
+ +
1 3
x x
B A 1 - A 1 9 D D 0 - D 1 5 8 - D 1 5
=E 0 D 0 - D 7
x x
+ +
1 3
x x
- A
- D
H =E 0 1 5 D 0 - D
A 7
- D
1 5
0 0 0
0 0 5 0 0 7 0 0 9
0 0 0
0 0 0 0 0 0
5 7 9
0 0 0
- A
9 A D 8 - D 1 1 - A 5 D 9 0 - D 7
- A
9 A D 8 - D 1 1 - A 5 D 9 0 - D 7
( a
ir s t
c c e
s s
f r o
m ( b O ) d N d e Ax t d Ad
rc e c s e s s s
L E
2-
M I /O R R D D W D E A D Y
TR / E R N
INTR (input)
Hardware Interrupt Request Pin
INTR is used to request a hardware interrupt. It is recognized by the processor only when IF = 1, otherwise it is ignored (STI instruction sets this flag bit). The request on this line can be disabled (or masked) by making IF = 0 (use instruction CLI) If INTR becomes high and IF = 1, the 8086 enters an interrupt acknowledge cycle (INTA becomes active) after the current instruction has completed execution.
For Discussion
If I/O peripheral wants to interrupt the processor, the interrupt controller will send high pulse to the 8086 INTR pin. What about if a simple system to be built and hardware interrupts are not needed; What to do with INTR and INTA?
NMI
8086 CPU
INTR
Interrupt Logic
int
into
Divide Error
Single Step
Software
Traps
TEST (input)
The TEST pin is an input that is tested by the WAIT instruction. If TEST is at logic 0, the WAIT instruction functions as a NOP. If TEST is at logic 1, then the WAIT instruction causes the 8086 to idle, until TEST input becomes a logic 0. This pin is normally driven by the 8087 coprocessor (numeric coprocessor) . This prevents the CPU from accessing a memory result before the NDP has finished its calculation
Ready (input)
This input is used to insert wait states into processor Bus Cycle. If the READY pin is placed at a logic 0 level, the microprocessor enters into wait states and remains idle. If the READY pin is placed at a logic 1 level, it has no effect on the operation of the processor. It is sampled at the end of the T2 clock pulse Usually driven by a slow memory device
8284
Reset
RES
or ci M6808
HOLD (input)
The HOLD input is used by DMA controller to request a Direct Memory Access (DMA) operation. If the HOLD signal is at logic 1, the microprocessor places its address, data and control bus at the high impedance state. If the HOLD pin is at logic 0, the microprocessor works normally.
DMA Operation