EE 574 Advanced Microprocessor Systems

1/2 ME, EEE, Semester I

Power Systems and Power Electronics

UNIT I - 8086 and 8087 Microprocessors

Session 1 – 8086 Microprocessor -
Architecture, Segmented Memory

Instructor: N.Vasantha Gowri

Assistant Professor, EEE Dept.
CBIT, Hyderabad
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Syllabus
Unit I
 8086 Microprocessor
 8086 Microprocessor Architecture
 Segmented Memory
 Addressing Modes
 Instruction Set
 8086 Assembly Language Programming
 8087 Numerical Data Processor
(Math Coprocessor)
 Architectural Details
 Data types
 Floating Point Operations
 8087 Instructions

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Introduction Ref [3]

Intel introduced
4 bit microprocessor 4004 in 1971
8 bit microprocessor 8008 in 1972
- these had design and performance limitations
8080 in 1974 - First general purpose microprocessor
8085 – more features added to it architecture
– functionally complete microprocessor
Limitations of 8 bit microprocessor
- Low speed of execution
- Low memory addressing capability
- limited number of general purpose registers
- less powerful instruction set
8086 was built to overcome these limitations.

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Introduction Ref [3]

8086 was launched in 1978.
- More powerful instruction set
- programming flexibility
- improvement in speed

• Peripheral chips designed for 8085

compatible with 8086 with slight or no modifications
• Considerable differences between the memory addressing techniques
of 8085 and 8086
• Memory interfacing is similar, but uses additional signals.
• Clock requirements are different
• Overall minimal system organization of 8086 is similar to a general 8-bit
microprocessor

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8086 Register Organization
Ref [3]

1.1.1 General Data Registers:

AX, BX, CX, DX - general purpose 16-bit registers
AX - accumulator
Lower 8 bits = AL (can be used as accumulator for 8-bit operations)
Higher 8 bits = AH
Usually L – Lower byte Ex: CL = lower 8-bits of CX
H – Higher byte Ex: CH = higher 8-bits of CX
CX - default counter in string and loop instructions
BX - offset storage for forming physical addresses
DX – gen. purpose register - used as operand or destination in a few
instructions
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8086 Register Organization
1.1.2 Segment Registers: Ref [3]
Unlike 8085, 8086 addresses a segmented memory
8086 can address 1MB memory
- divided into 16 segments of 64 KB each
4 Segment Registers
CS - Code Segment Register
Used for addressing a memory location in the code segment of memory,
where executable program is stored.

DS – Data Segment Register

Used for addressing a memory location in data segement where data is
stored.

ES – Extra Segment Register

Used to address extra segment which is essentially another data segment –
ES also contains data

SS – Stack Segment Register

- Used for addressing stack segment of the memory –
Stack Segment is the segment of memory used to store stack data
- Stack is used as temporary storage for important data by CPU
Ex: the contents of CPU registers which will be required at a later stage
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8086 Register Organization
Ref [3]
1.1.2 Segment Registers:
SS – Stack Segment Register
Data is pushed into the stack
When data is needed, data is popped off the stack.

Addressing memory location

Physical address = segment address + offset

Advantage of this scheme:

20 bit addresses can be generated using two 16-bit registers

All the segments

May or may not be physically separated
i.e. – Single segment may require more than one chip
or many segments can be accommodated in one chip

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8086 Register Organization
1.1.3 Pointers and Index Registers: Ref [3]
Pointers contain offset within particular segments
IP - offset within the code segment
BP – offset within data segment
SP – offset within stack segment

Index Registers used as

- general purpose registers
- offset storage
in indexed, based indexed, relative based indexed addressed modes
SI – stores offset of source data in data segment
DI - stores offset of destination data in data segment
Index registers are useful for string manipulations

1.1.4 Flag Register

Contains
- the results of computations in the ALU
- Flag bits to control CPU operations

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8086 Architecture
Ref [3]

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8086 Architecture
8086 Architecture: Ref [3]

Several improvements over 8085

Supports 16-bit ALU, 16-bit Registers
- Provides segmented memory addressing capability
- More powerful instruction set
- Powerful interrupt structure
- Fetched instruction queue for overlapped fetching and execution

8086 Architecture
(a) Bus Interface Unit
(b) Execution Unit

(a) Bus Interface Unit

contains the circuit for physical address calculations and precoding
instruction byte queue (6 bytes long)
- Responsible for establishing communications with external devices and
peripherals including memory via bus
- makes system bus signals available for external interfacing of the devices
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8086 Architecture
Generating Physical Address: Ref [3]
Physical address is 20 bits long
generated from - Segment and offset registers – each 16 bits long.
Contents of segment register is shifted left bit-wise 4 times
contents of offset register is added
Example:
Segment address  1005H
Offset address  5555H
Segment address  1005H  0001 0000 0000 0101
Shifted left 4 bit positions 0001 0000 0000 0101 0000
Offset address  + 0101 0101 0101 0101
Physical address 0001 0101 0101 1010 0101
1 5 5 A 5
Segment addressed by 1005H
can have offsets from 0000H to FFFFH - 64 Kbytes
Segment address = base address - taken from appropriate segment register
- code, data, or stack
offset address = address within the segment
– content IP, BX, SI, DI, SP or immediate 16-bit value

BIU has a separate adder to perform this operation

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8086 Architecture
BIU Operation Ref [3]
In 8085, once the opcode is fetched and decoded, external bus remains
free while the processor executes the instruction
In 8086, this time slot is used for overlapped fetch and execution cycles
- while the fetched instruction is executed internally
external bus is used to fetch the machine code of next instruction
arrange it in a queue called precoded instruction byte queue.
- 6 bytes long first-in first-out structure
The instructions are taken from the queue sequentially for decoding.
The queue pushes out one instruction for decoding and the queue status is
checked for the possibility of next opcode fetch cycle.
When opcode is fetched by BIU, the EU (execution unit) executes previously
decoded instruction concurrently.
BIU and EU form a pipeline.
Thus BIU manages complete interface of EU with
memory and I/O devices under the control of timing and control unit.

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8086 Architecture
(b) Execution Unit (EU): Ref [3]

EU contains
register sets except segment registers and IP.
16-bit ALU to perform arithmetic and logic operations
16-bit flag register – reflects results of execution by ALU
decoding unit – decodes the opcode bytes issued by the instruction
byte queue
Timing and Control Unit
- derives necessary control signals to execute the instruction opcode,
depending on the information made available by the decoding unit.

The EU may pass the results to BIU to store in the memory.

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8086 Memory Segmentation
1.2.1. Memory Segmentation: Ref [3]

8086 Memory is organized into segments of 64 Kbytes

Contents of 16-bit segment register point to the starting location of a
segment
Offset address is 16 bits long.
Max offset value FFFFH

Two ways of organizing rooms in L-Block at CBIT

1. Number all the rooms sequentially – say 1 to 60
To find room 54, you have to start from Room 1 and go up to Room 54
sequentially
2. Number the rooms by floor numbers and room numbers
Example: To find Room 207 - Go to second floor, go to 7th room.
In the second method, effort in finding the same room is much less.
This method is similar to Segmented memory.
Segment addresses are analogous to Floor numbers
Offset addresses are analogous to Room numbers

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8086 Memory Segmentation
Ref [3]

Non-overlapping segments:
8086 can address 1Mbytes of physical memory
Divided into 16 segments of 64 Kbytes each
Segment address - 0000H to F000H
Offset address - 0000H to FFFFH
Physical address - 00000H to FFFFFH
In this case the segments are called non-overlapping. See Fig. 1.3(a) 15
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8086 Memory Segmentation
Overlapping segments: Ref [3]
Suppose a segment starts at a particular address
its max size can be 64 Kbytes.
If another segment starts before this 64 Kbytes of the first segment
the two segments are said to be overlapping.
Overlapped segment area
the area of the memory from the start of the second segment to the possible
end of the first segment. See Fig. 1.3(b)
- The location in the overlapped area can be addressed by same physical
address generated from two diff. segment addresses and offsets.
Advantages of segmented memory scheme:
1. Allows memory capacity to be 1 Mbytes although actual addresses are
of 16-bits size.
2. Allows placing of code, data, and stack portions the same programs in
diff. parts (segments) of memory for data and code protection.
3. Permits a program and/or its data to be put into diff. areas of memory
each time program is executed. i.e. provision for relocation may be done.
In Fig. 1.3(b), physical addresses for locations in overlapped area can be
generated as CS1+IP1 = CS2 + IP2 16
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8086 Flag Register Ref [3]

Flag Register:
16-bit flag register, divided into 2 parts
(a) condition code or status flags
= lower byte of flag register + overflow flag
= like 8085 flag register + overflow flag (not present in 8085)
Reflects the results of operations performed by ALU
(b) machine control flags
contains higher byte of flag register
- Direction flag (D)
- Interrupt flag (I)
- Trap flag (T)

Complete bit configuration of the flag register is shown in Fig. 1.4.

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8086 Flag Register Ref [3]

Description of each Flag:

S - Sign flag - set when result of computation is –ve.
For signed computations Sign flag = MSB of the result.
Z - Zero flag – set when results of computation or comparison performed by
prev. instruction/instructions is 0.
P - Parity flag – set when lower byte of results contain even number of 1s.
C - Carry flag – set when there is a carry out of MSB in addition
or borrow in subtraction
T – Trap flag - when set, processor enters single step execution mode.
- trap interrupt is generated after execution of each instruction
- Processor executes current instruction and control is transferred to Trap
interrupt service routine.
I - Interrupt flag - when set maskable interrupts are recognized by processor,
otherwise they are ignored. 18
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8086 Flag Register Ref [3]

Description of each Flag:

D - Direction flag- Used in string manipulation instructions
when 0, string is processed from lowest address to
highest address (autoincrementing mode)
when 1, string is processed from highest to lowest address
(autodecrementing mode)
AC – Auxiliary Carry flag
– set if there is a carry from the lowest nibble – bit 3 – during addition 1 0011
or borrow for the lowest nibble – bit 3- during subtraction 1 1011
O – Overflow flag
- Set when overflow occurs
Ex: addition of two signed numbers, result overflows into sign bit
result > 7 bits in case of 8-bit signed operations
result > 15 bits in case of 16-bit signed operations
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8086 Signal Descriptions
Ref [3]
1.3 Signal Description:
8086 – 16 bit CPU
Available in 3 clock rates
– 5, 8, 10 MHz
40 pin CERDIP or plastic package
Can operate in single processor or
multiprocessor configuration
to achieve higher performance.
Some pins have different functions
for min. mode and max. mode
Pins are categorized in 3 groups
1. Signals common to min and
max modes
2. Special signals to min mode
3. Special signals to max mode

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8086 Signal Descriptions
Signals common to Min and Max modes: Ref [3]
AD15-AD0 Multiplexed memory, I/O address and data lines
Address remains during T1 state, data is available during T2, T3, Tw, T4
states.
T1, T2, T3, T4, Tw are clock states of machine cycle, Tw is wait state
A19/S6, A18/S5, A17/S4 , A16/S3 Time multiplexed address and status lines
During T1 - MSB of address for memory operations
During I/O operations these lines are low
During I/O operations status information is available during T2, T3, Tw, T4
states.
S5 – displays interrupt enable flag bit, updated at the beginning of each
clock cycle
S4 , S3 – indicate which segment register is used for memory accesses,
floated to tristate off during local bus hold acknowledge
S6 – always low
Address bits are separated from status bits using latches controlled by ALE
signal
Table 1.1 Segment register status

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8086 Signal Descriptions
Signals common to Min and Max modes: Ref [3]
BHE/S7 Bus high enable is used to indicate transfer of data over higher order
(D15-D8) data bus shown in Table 1.2.
Goes low for data transfers over D15-D8
Also used to derive chip select signal of odd memory banks or peripherals
BHE is low during T1 for read, write, and interrupt acknowledge cycles
whenever a byte is to be transferred on higher byte of the data bus.
Status information is available during T2, T3, T4
Signal is active low and tristated during hold.

RD – Read Read signal when low indicates the peripherals that processor is
performing memory or I/O read operation.
Active low and shows the status for T2, T3, TW of any read cycle
Signal remains tristated during ‘hold acknowledge’.
READY –Acknowledgement from slow devices or memory that they have
completed data transfer. Signal is synchronized by 8284A clock generator
to provide ready input to 8086. – Active high.
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8086 Signal Descriptions
Signals common to Min and Max modes: Ref [3]
INTR – Interrupt Request Level triggered input, sampled during last clock
cycle of each instruction to determine the availability of the request.
If interrupt request is pending, the processor enters Interrupt Acknowledge
cycle,
can be internally masked by resetting the interrupt enable flag
Active high and internally synchronized.
TEST This input is examined by WAIT instruction
If TEST goes low, execution will continue, otherwise processor will remain
idle state.
Input is synchronized during each clock cycle on leading edge.
NMI-Nonmaskable interrupt Edge triggered input which causes Type2
interrupt.
Not maskable internally by software.
A transition from low to high initiates interrupt response at the end of the
current instruction.
Internally synchronized.
RESET This input causes the processor to terminate the current activity and
start execution from FFFF0H.
Active high, must remain active for at least 4 clock cycles.
It starts execution when the RESET returns to low.
Internally synchronized.
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8086 Signal Descriptions
Signals common to Min and Max modes: Ref [3]
CLK – Clock Input Provides basic timing for the processor operation and bus
control activity.
Asymmetric square wave with 33% duty cycle.
8086 range of frequency - 5 to 10 MHz.
Vcc +5 V power supply for the internal operation of the circuit.
GND Ground for the internal circuit.
MN/MX Logic level indicates whether the processor is to operate in minimum
(single processor) or maximum (multiprocessor) mode.

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8086 Signal Descriptions
Signals for Minimum modes: Ref [3]
M/I/O – Memory/IO Status line equivalent to S2 in Maximum mode.
When low – CPU in I/O operation
When high – CPU in memory operation
Becomes active in previous T4 and remains active till T4 in current cycle.
Tristated during local bus “hold acknowledge”.
INTA-Interrupt Acknowledge
To read strobe for interrupt acknowledge cycles.
When it goes low, it means CPU has accepted the interrupt
Active low during T2, T3 , and Tw of each interrupt acknowledge cycle
ALE- Address Latch Enable Output signal indicates the availability of valid
address on the address/data lines
Connected to latch enable input of latches
Active high, never tristated.
DT/R – Data Transmit/Receive Output used to decide direction of data flow
through the transreceivers (bidirectional buffers).
Processor sends out data, when this signal is high
Processor receives data, when this signal is low.
This is equivalent to S1 in maximum mode.
Timing is same as M/I/O.
Tristated during “hold acknowledge”.

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8086 Signal Descriptions
Signals for Minimum modes: Ref [3]
DEN – Data Enable Indicates the availability of valid data over address/data
lines. Used to enable the transreceivers (bidirectional buffers) to separate
the data from the multiplexed address/data signal.
Becomes active from previous T2 and remains active till the middle of T4
Tristated during local bus “hold acknowledge” cycle.
HOLD, HLDA- Hold/Hold Acknowledge
When HOLD line goes high, indicates to the processor that another
master is requesting bus access.
The processor issues hold acknowledge signal in HLDA pin, in the middle
of next clock cycle after completing the current bus (instruction) cycle. At
the same time the processor floats the local bus and control lines.
When the processor detects the HOLD line low, it lowers the HLDA line.
HOLD is asynchronous signal, should be externally synchronized.
DMA Operation – Direct Memory Access
If DMA request is made while CPU is performing a memory or I/O cycle,
it will release the local bus provided:
1. The request occurs on or before T2 state of the current cycle
2. The current cycle is not operating on the lower byte of a word (or
operating on an odd address)
3. The current cycle is not the first acknowledge of the interrupt
acknowledge sequence.
4. A lock instruction is not being executed.
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8086 Signal Descriptions
Signals for Maximum modes: Ref [3]

S2, S1, S0 – Status lines Status lines reflect the type of operation being carried
out by the processor
Become active during previous T4 and remains active till of T1, T2 of the
current bus cycle.
Return to passive state during T3 of the current bus cycle so that it may
become active for the next bus cycle during T4 .
Any change in these lines during T3 indicates the starting of the new cycle,
and return to passive state indicates end of the bus cycle.

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8086 Signal Descriptions
Signals for Maximum modes: Ref [3]
LOCK – Lock Output pin – when low other system bus masters will be
prevented from gaining the system bus.
Activated by LOCK prefix instruction, remains active until the completion
of next instruction.
Floats to Tristate off during “hold acknowledge” cycle.
When CPU is executing critical instruction which requires system bus, the
LOCK prefix instruction ensures that the other processors in the system will
not gain the control of the bus.
The 8086 while executing the prefixed instruction, asserts the bus lock
signal output, which may be connected to an external bus controller.
QS1, QS2- Queue Status
These lines give information about the status of the code prefetch queue.
Active during the CLK cycle after which the queue operation is performed.
Encoded as shown in Table 1.4.

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8086 Signal Descriptions
Pipelined processing of instructions: Ref [3]

8085 An instruction (opcode and operand) is fetched, decoded and executed.

Next instruction is fetched from the memory only after execution of the
current instruction is completed.
8086 Has a 6-byte instruction pre-fetch queue. Thus even a largest (6-bytes)
instruction is pre-fetched from memory and stored in prefetch queue.
Results in faster execution of instructions.
Prefetching of instructions results in considerable speeding up of execution
of instructions in 8086. This scheme is known as instruction pipelining.

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8086 Signal Descriptions
The Queue Operation: Ref [3]

- At the start, the CS:IP is loaded with the required address from which the
execution is to be started.
- Initially the queue is empty.
- The microprocessor starts the fetch operation to bring
one byte (first byte) of the instruction if the CS:IP address is odd
two bytes at a time if CS:IP address is even.
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8086 Signal
The Queue Operation: (continued)
Descriptions
Ref [3]
- One byte instruction - First byte is an opcode.
- Two byte instructions – second byte also contains part of opcode.
- The opcode along with data are fetched and arranged in the queue.
- When the first byte in the queue goes for decoding and interpretation, one
byte in the queue becomes empty and the queue is updated.
- The processor performs the fetch operation only after two bytes in the
queue are emptied. The instruction cycle is never broken for fetch
operation.
- After decoding the first byte, the decoding circuit decides whether the
instruction is single opcode byte or double opcode byte.
- If it is single opcode byte, the next bytes are treated as data bytes depending
on decoded instruction length.
- Otherwise the next byte in the queue is treated as second byte of opcode
- The second byte is decoded in continuation with the first byte to decide the
instruction length and the number of subsequent bytes to be treated as data.
- The queue is updated after every byte is read from the queue, but fetch
operation is initiated by BIU only after at least two bytes are emptied from
queue.
- The EU may be concurrently executing the fetched instructions 31
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8086 Signal
The Queue Operation: (continued)
Descriptions
Ref [3]
- The next byte after the instruction is completed is again the first byte of
opcode.
- This procedure is repeated till the program is completely executed.
Main point
- Fetch operation of the next instruction is overlapped with the execution of
the current instruction.
- There are two separate units in the architecture
– Bus Interface Unit (BIU) and Execution Unit (EU)
- While the EU is executing the instruction after it is decoded, the BIU may
be fetching the next instruction from memory depending on the queue status

RQ/GT0, RQ/GT1 – Request/Grant

These pins are used by other local bus masters in max mode to force the
processor to release the local bus at the end of current bus cycle.
These pins are bidirectional
RQ/GT0 has higher priority than RQ/GT1
These pins have internal pull-up resistors and may be left unconnected

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8086 Signal Descriptions
RQ/GT0, RQ/GT1 – Request/Grant Ref [3]
Request/Grant sequence
1. A pulse one clock wide from another bus master requests the bus access
to 8086
2. 8086 sends a pulse one clock wide to the requesting master during
current T4 or next T1, indicating that the 8086 has allowed the local bus to
float and it will enter the ‘hold acknowledge’ state at the next clock cycle.
The CPU’s BIU is likely to be disconnected from the local bus of the
system.
3. A pulse one clock wide from another bus master indicates to 8086 that
the ‘hold’ request is about to end and the 8086 may regain control of the
local bus at the next clock cycle.

- Thus each master to master exchange of the local bus is a sequence of 3

pulses. There must be at least one dead clock cycle after each bus exchange.
- Request and Grant pulses are active low.
- For bus requests received while 8086 is performing memory or I/O cycle,
granting of the bus is governed by rules similar to HOLD and HLDA in
minimum mode.

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Physical Memory Organization
1.4. Physical Memory Organization Ref [3]
8086 based system
1 Mbytes memory is organized as odd bank and even bank, 512 Kbytes
each.
Addressed in parallel by the processor.
Byte data with even address transferred on D7-D0
Byte data with odd address transferred on D15-D8.
Processor provides BHE and A0 for selection even, odd or both banks
Processor fetches instruction stream as words from memory and addressed
internally as necessary.
Processor fetches a word (two consecutive bytes) from memory, there are
different possibilities:
1. Both the bytes may be data operands
2. Both the bytes may contain opcode bits
3. One of the bytes may be opcode and the other may be data.
Internal decoder circuit takes care of the above possibilities.
- identifies opcode and operands
- further derives signals that act as input to timing and control unit
Timing and control unit derives signals required for execution of the instruction.

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Physical Memory Organization
1.4. Physical Memory Organization Ref [3]
Reading from and Writing to Memory
BIU needs one or two memory cycles depending upon
whether the starting byte is located at even or odd address
When starting address is even, only one read or write cycle is required.
If word is located at odd address, two cycles are required
- First read or write cycle is needed for accessing the lower byte
- second cycle is required for accessing the higher byte.
Therefore it is always better to locate the word data at even address.
Stack structures should be initialized at an even address for efficient
operation.

Reserved memory locations:

Certain memory locations are reserved for CPU operations.
FFFF0H to FFFFFH – for jump to initialization and I/O processor initialization
00000H to 003FFH - for interrupt vector table.
Interrupt structure provides space for 256 interrupt vectors
Interrupt vectors (CS and IP) for each interrupt routine requires 4 bytes for
storing in interrupt vector table.
Therefore 256 types of interrupts require 256 x 4 = 1024 = 03FFH locations
for the complete interrupt vector table. 35
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General Bus Operation
1.5. General Bus Operation Ref [3]

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General Bus Operation
1.5. General Bus Operation Ref [3]
8086 has time multiplexed address/data bus, to limit the number of pins to 40.
The bus is demultiplexed using latches and transreceivers, whenever required.

Fig. 1.7 shows general bus operation cycle of 8086.

General Bus Operation Cycle
- All bus cycles consist of at least 4 clock cycles – T1, T2, T3 and T4
- Address is transmitted during T1. Address is present on the bus for only
one cycle
- During T2, the bus is tristated for changing direction of the bus for the
following data read cycle.
- Data transfer takes place during T3 and T4
- If the addressed device is slow and shows ‘NOT READY’ status, wait
states Tw are inserted between T3 and T4
- The clock states during the wait period are called idle states (Ti) or
wait states Tw or inactive states..
- Address Latch enable (ALE) signal is emitted during T1 by CPU (min
mode) or bus controller (max mode) depending on the status of MN/MX
input
- The negative edge of the ALE pulse is used to separate address and the
data or status information.
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General Bus Operation
1.5. General Bus Operation Ref [3]
General Bus Operation Cycle
- In Maximum mode
- the status lines S0, S1, S2 are used to indicate types of operation
- Status bits S3 to S7 are multiplexed with higher order address bits and
BHE status signal.
- Address is valid during T1
while Status bits S3 to S7 are valid during T2 to T4

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I/O Addressing Capability
1.6. I/O Addressing Capability Ref [3]
8086/8088 can address up to 64K I/O byte registers or 32K word registers.
- address of I/O devices should not be greater than 16 bits
- means max number of I/O devices that can be addressed by CPU
= 216 = 64 Kbytes
- I/O address appears on address lines A0 to A15 during T1, latched using
ALE signal
- Upper address lines (A16 – A19) are at logic 0 during I/O operations.
- DX register is used as 16-bit I/O address pointer
I/O ports are addressed in the same manner as memory locations in based
addressing mode using BX.
- In memory mapped I/O interfacing, I/O device addresses are treated as
memory locations in page 0, i.e. segment address 0000H
- Even addressed bytes are transferred on D7-D0
Odd addressed bytes are transferred on D15-D8
- While designing 8 bit I/O system around 8086, make sure that all the byte
registers in the system should be addresses even.

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Special Processor Activities
1.7. Special Processor Activities Ref [3]
1.7.1 Processor Reset and Initialization
When Logic 1 is applied to RESET pin, CPU is reset and remains in reset state
till Logic 0 is applied.
- 8086 terminates the ongoing operation on the positive edge of reset signal.
- At negative edge, reset sequence starts and continues for ~10 clock cycles.
- During reset operation, all internal registers are set to 0000H
except CS is set to F000H and IP to FFF0H. Thus execution starts again
at FFFF0H.
- Due to this EPROM in 8086 system has an address of FFFF0H to
FFFFFH, i.e. at the end of the map.
For reset signal to be accepted by 8086
- it must be high for at least 4 clock cycles.
- Reset pulse must be applied only after 50 ms after power on to allow for
proper initialization of 8086.
- In reset state all 3-state outputs are tristated.
- Status signals are active in idle state for first clock cycle after reset
becomes active, then floats to tristate.
- ALE and HLDA signals are driven low during the reset operation
- NMI that appears before 2nd clock after the end of reset operation will not
be served. For NMI to be served it must appear before 2nd clock cycle
during reset initialization or later 40
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Special Processor Activities
1.7 Special Processor Activities Ref [3]
1.7.1 Processor Reset and Initialization
- If HOLD request appears immediately after RESET, it will be
immediately served after initialization, before execution of any instruction.

1.7.2 HALT
When the processor executes HLT instruction, it enters the ‘halt’ state.
- Before entering ‘halt’ state, it indicates ‘halt’ state in two ways, depending
on whether it is in minimum or maximum mode
Minimum mode – issues ALE pulse, but does not issue any control signal.
Maximum mode – puts HALT status on S2, S1, S0 pins, then the bus
controller issues one ALE pulse, but no qualifying signal. i.e. no
appropriate address or control signals are issued onto the bus.
- Only an interrupt request or reset will force 8086 to come out of ‘halt’
state.
- Even ‘HOLD’ request can not force 8086 out of ‘halt’ state.

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Special Processor Activities
1.7 Special Processor Activities Ref [3]
1.7.3 TEST and Synchronization with External Signals
Besides interrupt, hold and general I/O capabilities
8086 has extra facility of TEST signal.
- When the CPU receives a WAIT instruction, it preserves the contents of
the registers before execution of WAIT instruction and waits for TEST
input to go low.
- If the TEST input goes low, it continues further execution.
- otherwise it keeps on waiting for TEST pin to go low.
- For TEST signal to be accepted, it must be low for at least 5 clock cycles.
- Activity of waiting does not consume any bus cycle. The processor
remains in idle state while waiting.
- While waiting, any HOLD request from an external device may be served.
- If an interrupt occurs during wait, it fetches the wait instruction once
more, executes it, and then serves the interrupt.
- After returning from interrupt, it fetches the wait instruction once more
and continues with the ‘wait’ state.
- Thus the execution of a program which appears after WAIT instruction
can be synchronized with an external signal connected with the TEST input.

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1.8 Minimum Mode 8086 System and Timings Ref [3]

The 8086 system organization is shown in Fig. 1.8. Since it has 20 address lines and
16 data lines, 8086 CPU requires three address latches and two octal data buffers for the
complete address and data separation 43
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Minimum Mode 8086 System and Timings
1.8 Minimum Mode 8086 System and Timings Ref [3]
In Minimum mode 8086 system,
There is a single micro processor
MN/MX is connected to Logic 1 (VCC)
- All the control signals are given out by microprocessor itself.
- Latches, transreceivers, clock generator, memory and I/O devices are
remaining components.
- Chip selection logic may be required to select memory or I/O devices
The latches are buffered D-type flip-flops, like 74LS373 or 8282.
- Used for separating the valid address from multiplexed address/data
signals and are controlled by ALE signal.
Transreceivers are bidirectional buffers, also called data amplifiers.
- required to separate data from multiplexed address/data signal.
- controlled by two signals DEN and DT/R
- DEN signal indicates that valid data is available on the data bus
- DT/R indicates the direction of data, i.e. from or to the processor.
The system contains memory for monitor and user program.
- EPROMs are used for monitor storage
- RAMs are used for user program storage
System may contain I/O devices for communicating with the processor and
special I/O devices.
Clock generator generates clock from the crystal oscillator, and then shapes and
divides to make it more precise to be used as accurate timing reference for
the system. Also synchronizes some ext. signals with the system clock.44
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1.8 Minimum Mode 8086 System and Timings Ref [3]
Working of min mode configuration system can be described in terms of
timing diagram
- The opcode fetch and read cycles are similar.
- The timing diagram is categorized into two parts
– read cycle and write cycle
Read Cycle
- begins with the assertion of ALE signal and M/IO signal
- During negative edge of this signal, valid address is latched on the local
bus.
- The BHE and A0 signals address low, high, or both bytes.
- From T1 to T4, the M/IO signal indicates memory or I/O operation.
At T2 address is removed from the local bus and sent to the output. The bus
is then tristated.
- The read signal RD is also activated in T2. The RD signal causes the
addressed device to enable its data bus drivers.
- After RD goes low, the valid data is available on the bus.
- The addressed device will drive the READY line high.
- When the processor returns the RD signal to high level, the addressed
device will again tristate the bus drivers.

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1.8 Minimum Mode 8086 System and Timings Ref [3]
Write Cycle
- begins with the assertion of ALE signal and the emission of address
- the M/IO signal is asserted indicating memory or I/O operation
- After sending the address in T1, in T2 the processor sends the data to be
written to the addressed location.
- The data remains in the bus till the middle of T4.
- The WR becomes active at the beginning of T2 (unlike RD is delayed in
T2 to provide time for floating)
- BHE and A0 signals are used to select proper byte or bytes of memory or
I/O word as discussed in signal description.
- M/IO, RD, and WR signals indicate the type of data transfer as shown in
Table 1.5.

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1.8 Minimum Mode 8086 System and Timings Ref [3]
1.8.1. Hold Response Sequence

- The hold pin is checked at the leading edge of each clock pulse.
If it is received active by the processor before T4 of the previous cycle
or during T1 of current cycle, the CPU activates HLDA in the next
clock cycle and for the succeeding bus cycles. The bus will be given
to another requesting master.
- The control of the bus regained by the processor when the
requesting master drops the HOLD pin low.
- then the HLDA is dropped by the processor at the trailing edge of
the next clock as shown in Fig. 1.9(c)
The other conditions for HOLD and HLDA are discussed in signal
description section.
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1.9 Maximum Mode 8086 System and Timings Ref [3]

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1.9 Maximum Mode 8086 System and Timings Ref [3]
In Maximum mode 8086 system,
There may be more than one micro processor in the system
MN/MX is connected to Logic 0 (GND)
- the processor drives the status signals S2, S1, S0.
- Another chip, known as bus controller, derives control signals from status
signals.
- The other components in the system are the same as in minimum mode
system
- The functions of all the pins having special functions in max mode have
been discussed in the section on pin description.
The basic function of the controller chip IC8288
is to derive control signals like RD, WR (for memory and I/O devices)
DEN, DT/R, ALE, etc. using the status signals.
- The bus controller chip has input lines S2, S1, S0, and CLK.
- These inputs to 8288 are driven by CPU
- It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC,
IOWC, and AIOWC.
- AEN and IOB are generally grounded. CEN is tied to +5 V.
- Significance of MCE/PDEN output depends on status of IOB pin.
(master cascade enable/peripheral data enable)
- If IOB is grounded, it acts as a master cascade enable for cascaded 8259A
else it acts as peripheral data enable used in multiple bus configurations.
- INTA pin is used to issue two interrupt acknowledge pulses to the
interrupt controller or to an interrupting device. 51
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IORC = IO read command
IOWC = IO write command
These signals enable an IO interface to read or write data from or to the
addressed port.
MRDC = memory read command
MWTC = memory write command
These signals are used as memory read or write signals. These command
signals instruct the memory to accept or send data from or to the bus.
For both IO and memory write command signals, advanced commands are
available. AIOWC and AMWTC.
These also serve the same purpose, but are activated one clock cycle earlier
than IOWC and MWTC signals respectively.

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1.9 Maximum Mode 8086 System and Timings Ref [3]

The timing diagrams are divided in two portions as read (input) and write
(output) timing diagrams.
The address/data and address/status timings are similar to minimum mode
The only difference lies in the status signals used and available control
and advanced command signals.
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1.9 Maximum Mode 8086 System and Timings Ref [3]
1.9.1 Timings for RQ/GT Signals

The request/grant response sequence contains a series of 3 pulses as

shown in Fig. 1.11(c).
- The request/grant pins are checked at each rising pulse of clock input.
- When a request is detected, and if the conditions discussed in the section
on signal descriptions for valid HOLD request are satisfied, the processor
issues a grant pulse over the RQ/GT pin immediately during the T4
(current) or T1 (next) state.
- When requesting master receives this pulse, it accepts the control of the
bus.
- The requesting master uses the bus till it requires.
- When it is ready to relinquish the bus, it sends a release pulse to the
processor (host) using the RQ/GT pin. 55
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Suggested Reading
1. Barry B. Brey, “Intel Microprocessors: 8086/88, 80186/188, 80286,
80386, 80486, Pentium, Pentium II, Pentium III, Pentium IV –
Architecture, Programming and Interfacing”, Pearson Education,
2003.
2. Badri Ram, “Advanced Microprocessors and Interfacing”, Tata-
McGraw Hill, 2001.
3. A.K. Ray and K.M. Bhurchandi, “Advanced Microprocessors and
Peripherals – Architecture, Programming and Interfacing”, Tata-
McGraw Hill, 2000.

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