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6.004 Computation Structures

Spring 2009

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Sequential Logic:
adding a little state

6.004: Progress so far

PHYSICS: Continuous variables, Memory, Noise, f(RC) = 1 - e-t/RC

COMBINATIONAL: Discrete, memoryless, noise-free, lookup table functions

C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Y 0 1 0 1 0 0 1 1

2.71354 volts
01101

Lab #1 is due tonight

(checko meeting by next Thursday).

What other building blocks do we need in order to compute?

QUIZ #1 Tomorrow!
(covers thru L4/R5)

6.004 Spring 2009

2/19/09

modied 2/17/09 10:26

L05 Sequential Logic 1

6.004 Spring 2009

2/19/09

L05 Sequential Logic 2

Something We Cant Build (Yet)

What if you were given the following design specication:
When the button is pushed: 1) Turn on the light if it is o 2) Turn o the light if it is on The light should change state within a second of the button press

Digital State
One model of what wed like to build
New State

Memory Device
light

Current State

button

LOAD Input

Combinational Logic
Output

What makes this circuit so dierent from those weve discussed before?
1. State i.e. the circuit has memory 2. The output was changed by a input event (pushing a button) rather than an input value
6.004 Spring 2009 2/19/09 L05 Sequential Logic 3

Plan: Build a Sequential Circuit with stored digital STATE Memory stores CURRENT state, produced at output
Combinational Logic computes NEXT state (from input, current state) OUTPUT bit (from input, current state) State changes on LOAD control input
6.004 Spring 2009 2/19/09 L05 Sequential Logic 4

Needed: Storage
Combinational logic is stateless:
valid outputs always reect current inputs.

Storage: Using Capacitors

Weve chosen to encode information using voltages and we know from 6.002 that we can store a voltage as charge on a capacitor:
word line Bit line N-channel fet serves as access switch VREF

To build devices with state, we need components which store information (e.g., state) for subsequent access.
ROMs (and other combinational logic) store information wired in to their truth table Read/Write memory elements are required to build devices capable of changing their contents.

How can we store and subsequently access -- a bit?

Mechanics: holes in cards/tapes Optics: Film, CDs, DVDs, Magnetic materials Delay lines; moonbounce Stored charge
2/19/09 L05 Sequential Logic 5

To write: Drive bit line, turn on access fet, force storage cap to new voltage To read: precharge bit line, turn on access fet, detect (small) change in bit line voltage
6.004 Spring 2009 2/19/09

Pros: compact low cost/bit (on BIG memories) Cons: complex interface stable? (noise, ) it leaks! refresh
Suppose we refresh CONTINUOUSLY?

6.004 Spring 2009

L05 Sequential Logic 6

Storage: Using Feedback

IDEA: use positive feedback to maintain storage indenitely. Our logic gates are built to restore marginal signal levels, so noise shouldnt be a problem! Result: a bistable storage element
VIN
VTC for inverter pair Feedback constraint: VIN = VOUT

Settable Storage Element

Its easy to build a settable storage element (called a latch) using a lenient MUX: Heres a feedback path,
so its no longer a combinational circuit.

state signal appears as both input and output

VOUT Not aected by noise

G D QIN QOUT Q Y 0 0 1 1 --0 1 0 1 --0 1 0 1

Q stable Q follows D

VOUT

Three solutions: two end-points are stable middle point is unstable

VIN Well get back to this!
2/19/09 L05 Sequential Logic 7

D B G S

6.004 Spring 2009

6.004 Spring 2009

2/19/09

L05 Sequential Logic 8

New Device: D Latch

G=1: Q follows D Q A D G
D G
BUT A change in D or G contaminates Q, hence Q how can this possibly work? 0 1

A Plea for Lenience

G=0: Q holds A Q
0 1 V2
G 1 1 X X 0 0 D 0 1 0 1 X X Q X X 0 1 0 1 Q 0 1 0 1 0 1

D G Q
TPD

V1

V2

Q Y

D G Q
Q
TPD

V1

D G

Q Y

V1 TPD

V2

V1 TPD

V2

Assume LENIENT Mux, propagation delay of TPD Then output valid when G=1, D stable for TPD, independently of Q; or Q=D stable for TPD , independently of G; or G=0, Q stable for TPD , independently of D
L05 Sequential Logic 9 6.004 Spring 2009 2/19/09

Q(D,G)

Does lenience guarantee a working latch?

What if D and G change at about the same time

Q(D,Q) Q(G,Q)

G=1: Q Follows D, independently of Q G=0: Q Holds stable Q, independently of D

2/19/09

6.004 Spring 2009

L05 Sequential Logic 10

with a little discipline

D Stable

Lets try it out!

New State

Q A D G

0 1

Q Y

D G Q

V2

D
V2 TPD TPD TPD

Q
Current State

Combinational Logic
Output

To reliably latch V2:

Apply V2 to D, holding G=1 After TPD, V2 appears at Q=Q After another TPD, Q & D both valid for TPD; will hold Q=V2 independently of G Set G=0, while Q & D hold Q=D After another TPD, G=0 and Q are sucient to hold Q=V2 independently of D
6.004 Spring 2009

Input

TSETUP THOLD

Dynamic Discipline for our latch:

TSETUP = 2TPD: interval prior to G transition for which D must be stable & valid THOLD = TPD: interval following G transition for which D must be stable & valid
2/19/09 L05 Sequential Logic 11

Plan: Build a Sequential Circuit with one bit of STATE Single latch holds CURRENT state
Combinational Logic computes NEXT state (from input, current state) OUTPUT bit (from input, current state) State changes when G = 1 (briey!)
6.004 Spring 2009 2/19/09 L05 Sequential Logic 12

What happens when G=1?

Flakey Control Systems Combinational Cycles

New State

Q
Current State

1
Input

Combinational Logic
Output

Heres a strategy for saving 3 bucks on the Sumner Tunnel!

When G=1, latch is Transparent

provides a combinational path from D to Q. Cant work without tricky timing constrants on G=1 pulse: Must t within contamination delay of logic Must accommodate latch setup, hold times Want to signal an INSTANT, not an INTERVAL
6.004 Spring 2009 2/19/09

Looks like a stupid Approach to me

Figure by MIT OpenCourseWare.

L05 Sequential Logic 13

6.004 Spring 2009

2/19/09

L05 Sequential Logic 14

Escapement Strategy
The Solution: Add two gates and only open one at a time.

Edge-triggered Flip Flop

The gate of this latch is open when the clock is low

D
D0 1
S

D G

D G

D CLK

What does that one do?

master

slave

CLK

The gate of this latch is open when the clock is high

Observations: Transitions mark only one latch transparent at any time: instants, not intervals master closed when slave is open slave closed when master is open no combinational path through ip op
(the feedback path in one of the master or slave latches is always active)

Figure by MIT OpenCourseWare.

6.004 Spring 2009 2/19/09 L05 Sequential Logic 15 6.004 Spring 2009

Q only changes shortly after 0 1 transition of CLK, so ip op appears to be triggered by rising edge of CLK
2/19/09 L05 Sequential Logic 16

Flip Flop Waveforms

D D G CLK Q D G Q Q D CLK D Q Q
master slave

Um, about that hold time

The masters contamination delay must meet the hold time of the slave

D G

D G

master

slave

CLK

Consider HOLD TIME requirement for slave: D CLK

Negative (1 0) clock transition slave freezes data: SHOULD be no output glitch, since master held constant data; BUT master output contaminated by change in G input! HOLD TIME of slave not met, UNLESS we assume sucient contamination delay in the path to its D input! slave closed master open
2/19/09 L05 Sequential Logic 17

Q
master closed slave open
6.004 Spring 2009

Accumulated tCD thru inverter, G Q path of master must cover slave tHOLD for this design to work!
6.004 Spring 2009 2/19/09 L05 Sequential Logic 18

Flip Flop Timing - I

<tPD
D CLK D Q Q

Single-clock Synchronous Circuits

>tCD
Does that symbol register?

Well use Flip Flops and Registers groups of FFs sharing a clock input in a highly constrained way to build digital systems:

Q CLK D
tPD: maximum propagation delay, CLK tCD: minimum contamination delay, CLK tSETUP: setup time
guarantee that D has propagated through feedback path before master closes

Single-clock Synchronous Discipline

No combinational cycles Single clock signal shared among all clocked devices >tSETUP >tHOLD Only care about value of register data inputs just before rising edge of clock Period greater than every combinational delay Change saved state after noiseinducing logic transitions have stopped!
L05 Sequential Logic 19 6.004 Spring 2009 2/19/09 L05 Sequential Logic 20

Q Q

tHOLD: hold time

guarantee master is closed and data is stable before allowing D to change
6.004 Spring 2009 2/19/09

Flip Flop Timing - II

D Q QR1 1 D Q

Model: Discrete Time

New State

reg1 CLK

reg2

Questions for register-based designs: how much time for useful work (i.e. for combinational logic delay)? does it help to guarantee a minimum tCD? How bout designing registers so that tCD,reg > tHOLD,reg? what happens if CLK signal doesnt arrive at the two registers at exactly the same time (a phenomenon known as clock skew)?

Memory Device
Clock Input

Current State

Combinational Logic
Output

t1 CLK QR1
tPD,reg1 tCD,reg1 tCD, 1 tPD, 1

t2

Active Clock Edges punctuate time -- Discrete Clock periods Discrete State Variables Discrete specications (simple rules eg tables relating outputs to inputs, state variables) ABSTRACTION: Finite State Machines (next lecture!)

t1 = tCD,reg1 + tCD,1 > tHOLD,reg2 t2 = tPD,reg1 + tPD,1 < tCLK - tSETUP,reg2

2/19/09

6.004 Spring 2009

L05 Sequential Logic 21

6.004 Spring 2009

2/19/09

L05 Sequential Logic 22

Sequential Circuit Timing

tCD,R = 1ns tPD,R = 3ns tS,R = 2ns tH,R = 2ns
Clock Input New State Current State

Summary
Sequential Circuits (with memory): Basic memory elements:
Feedback, detailed analysis => D basic level-sensitive devices Clk (eg, latch) 2 Latches => Flop Q Dynamic Discipline: constraints on input timing
Simple rules for sequential circuits Yields clocked circuit with TS, TH constraints on input timing >t s >t h

Combinational Logic
tCD,L = ? tPD,L = 5ns
Output

>t cd <t pd

Synchronous 1-clock logic:

Questions:
Constraints on TCD for the logic? Minimum clock period? Setup, Hold times for Inputs?
> 1 ns > 10 ns (TPD,R+TPD,L+ TS,R) TS = TPD,L +TS,R TH = TH,R -TCD,L

In

DQ

Combinational logic

DQ

Out

Clk

Finite State Machines

Next Lecture Topic!

This is a simple Finite State Machine more next lecture!!

6.004 Spring 2009 2/19/09 L05 Sequential Logic 23 6.004 Spring 2009 2/19/09 L05 Sequential Logic 24