clk

Multi2to1
control
[25:0]
[11:0]

out[11:0]

AdderPC2
PC[11:0]

out[11:0]

[0]

JumpAdd
in[25:0]

MainCtrl
[11:0]

Jump2

[11:0]

AddPC2

Zero
clk

RegPC
MuxJump
control

MuxJump
[11:0]

SignEx
ctrl
[15:0]

out[31:0]

in[15:0]

SignExtend

[31:0]
[31:0]

ShiftLeft
in[31:0]

Shift2

out[11:0]

[11:0]
[11:0]

AdderPC
exSign[11:0]

AddPC

out[11:0]

[11:0]

control

PC[11:0]

[11:0]
[11:0]
[11:0]

A[11:0]

out[11:0]

B[11:0]

[11:0]

control

MuxJump

[11:0]
[11:0]

A[11:0]

out[11:0]

B[11:0]

Jump3

reset
clk

[11:0]
[11:0]

A[11:0]

out[11:0]

B[11:0]

[11:0]
[11:0]

q[11:0]

[11:0]
[11:0]

InstructionMem
address[11:0]

instruction[31:0]

[31:0]
[31:0]

Intruc[31:0]

d[11:0]

InsMem
PCReg

OpAlu[1:0]

JumpJR

[31:0]
[31:0]

out

Unsign

dataMem
MuxALU

writeenable
readenable
clk

control
data[31:0]

address[31:0]

[31:0]
[31:0]
[31:0]

A[31:0]

out[31:0]

[31:0]

B[31:0]

writedata[31:0]

regfile

MuxOperand1

enWrite
clk
RE

Data
[31:0]

[1:0]

[25:21]

Control

Jump1

[20:16]

MuxReg2
control

RE

in[1:0]

[26]

RegDest
ALUSrc
MemWrite
MemRead
MemToReg
Branch
Jump
JR
RegWrite
out4
EXT

[31:0]

out[4:0]

Intruc[31:0]

[4:0]
[4:0]

alu
unsign
ReadData1[31:0]

WriteData[31:0]

ReadData2[31:0]

ReadRegister1[4:0]

MuxALU
control
A[31:0]

out[31:0]

B[31:0]

MuxOperand

[31:0]
[31:0]

BussA[31:0]
BussB[31:0]
ALUControl[1:0]

ALU

WriteRegister[4:0]

Register

[31:0]

[31:0]

[1:0]

ReadRegister2[4:0]

Mux1

[31:0]

[31:0]

[31:0]

CarryOut
zeroF
overflow
negative
out[31:0]

CarryOut
zeroF
overflow
negative
[31:0]