FPGA Implementation of

Simple Microprocessor
Introduction:
A microprocessor in a Field-Programmable Gate Array (FPGA) is not world news, but a free
8051 emulated core with a Controller Area Network (CAN) interface in a FPGA is not available
at the marked at the moment. The embedded microprocessor core chosen for this project is a free
soft core 8-bit RISC processor from Xilinx named PicoBlazeTM, implemented in a XC3S200
Spartan-3 FPGA at the development board “Spartan-3 starter kit board” from Xilinx.

The FPGA today is used in a lot of products from

Digital Video Technologies, Industrial/Scientific &
Medical, Wireless Communications to Satellites
project in orbit. Satellites and cars typically uses
CAN for communication between Microprocessors.

NAPIER Benjamin Grydehoej - BEng (Honours) Electronic and Computer Engineering

UNIVERSITY Supervisor: Dr. Thomas David Binnie
Emulated 8051 Microprocessor
Specification and Block Diagram over the Emulated 8051 Microprocessor
with CAN bus interface:

PICROBLAZ core and BOOT ROM: Special Function Register (SFR):

• 16 Byte wide Arithmetic Logic Unit(ALU) • The SFR control all the call to Ports,
with CARRY and ZERO indicator flag serial UART, interrupt control,
• 64-byte internal scratchpad RAM FPGA timer etc.
• 256 input and 256 output ports JTAG
WATCHDOG TIMER (WDT):
• Automatic 31-location Boot Rom
Instruction Code
• If the WDT is set and not cleared
CALL/RETURN stack 1K x 16 before every 65ms will the system
• Predictable performance, always two auto reset.
clock cycles per instruction PicoBlaze • The microprocessor reset is with a
Special Function
• Fast interrupt response; worst-case 5
Core Register HIGH
Watchdog
SYSTEM CLOCK:

Internal Address/Data and Control Bus

Reset
clock cycles Timer
System
• 1,024-Instruction Program Store Serial UART
Clock
CLK (50MHz) • Standard option is 50MHz

8051 Emulation Peripherals

18 bits wide EA
WR
• Run up to 200MHz or 100MIPS in a
SERIAL UART (RS232): Control RD Virtex-II Pro FPGA
CAN Bus UART
• Standard configuration 1 start bit,
PSEN
Data[7:0]
CONTROL:
8 data bits, No Parity and 1 stop bit.
Address
Decoder ADD[15:0] • Control signal for external Rom and
• Baud rates from 9600 to 115200. Timer P1[7:0] RAM or other peripherals compo-
P3[7:0]
nents
CAN BUS UART: I/O PORTS P4[7:0]
P5[7:0] ADDRESS D
DECODER:
ECODER:
• Designed to ISO 11898-1, CAN 2.0 A & B Serial Flash Rom
Interface
• Address bus expander up to 16 bit
• Supports bit rates up to 1Mbit/s for
with a latch the 8 bit data bus to the
CAN 2.0B
JTAG low end of 8 the bit address bus, this
TIMER: Serial Flash Rom
function is normally done outside
Platform Flash
• Timer 0 and 1 as 8-bit timer the microcontroller
• Timer 2 as 16-bit timer I/O PORTS:
SERIAL FLASH ROM INTERFACE: • Port 4 and 5 is clearly data ports at
• Controller interface of extern serial 8 bit
program store up to 2Mbit • Port 1 and 3 distribute the external
interrupt, timer, Serial RS232 and
CAN
Controller Area Network Specification 2.0A & 2.0B
Introduction to CAN:
The CAN Bus interface is a serial asynchronous transmission
scheme, that uses a communication protocol which efficiently
supports distribution of real time control with a very high level
of security. The specification is defined with the ISO 11898 “OSI
Model”. The CAN 2.0A is an extended message format defined
in CAN 1.2 and CAN 2.0B describing both standard and
extended message formats.
Physical Layer:
• Balanced differential 2-wire interface bus using either a
shielded Twisted Pair (STP) or Un-shielded (UTP) cable with
a male 9-PIN SUB-D connector
• Less than 40 meters-1Mbps, and less at 1km-20Kbps
• Non Return to Zero (NRZ) bit encoding
Transfer Layer:
Message transfer is manifested and controlled by four different
frame types:
• The Arbitration field identifier the ID.
• The Control field consists of four bits Data length Code that identify
how many Bytes there are in the data packet
• The Data field consists of the data to be transferred
• The Cyclic Redundancy Code (CRC) sequence is calculate from the
Start Of Frame (SOF) field to and with the Data field, with the
polynomial X15+X14+X10+X8+X7+X4+X3+1
• The ACK field acknowledgment a valid message received correctly
Object Layer:
There are 5 different error types:
• Bit Error, Stuff Error, CRC Error, Form Error and
Acknowledgment Error.
 Evolution - Simulation - Test and Result
Development of a Microprocessor in a FPGA: Development and Simulation
• VHDL Design in Xilinx ISE Project Navigator
• Assembler and ANSI C programming with Picoblaze C Compiler
named PCCOMP by Francesco Poderico for software development
• Convert the code to machine code in VHDL format, using the KCPSM3
• Software debugging the Assembler code in Mediatronix pBlazeIDE
• Simulation of Software and VHDL Design in ModelSim XE
• Download the data to the development board via JTAG interface using
the program named iMPACT
• Test of the circuit using a Logic Analyzer

Practical test with Logic Analyzer

Current Results 22/02/2006:

The microprocessor core is running on the board
with Serial UART and it is possible to communi-
cate (read & write) with the parallel I/O ports.
The CAN bus interface is the part of the project
that will be worked out over the next weeks before
the 8051 emulated peripherals will be designed.

WWW.BG-ELEKTRONIK.DK/FPGA