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5

TERASIC CYCLONE II EP2C35 DAUGHTER BOARD


D

SCHEMATIC
TOP
AUDIO
DISPLAY
EP2C35
ETHERNET
INPUT
MEMORY
POWER
USB BLASTER
USB DEVICE
VIDEO

CONTENT

PAGE

COVER PAGE , TOP


WM8731
LCD , LED , 7SEGMENT
EP2C35 BANK1..BANK8 , POWER , CONFIG
DM9000A
CLOCK , PS2 , RS232 , KEY , SWITCH , CONNECT
SRAM , DRAM , FLASH , SD CARD
POWER
USB BLASTER
USB DEVICE
ADV7181 , ADV7123

01
04
05
07
12
13
18
20
21
22
23

~
~
~
~
~
~
~
~
~
~
~

03
04
06
11
12
17
19
20
21
22
24

Title
ALTERA DE2
Size
B
Date:
5

Document Number
<Doc>
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

of

24

DC
9V

USB
DEVICE

USB
HOST

LINE LINE MIC


IN
OUT IN

TV
DECODER

VGA
OUTPUT

RJ45

PS2
KEYBORAD

RS232

BAT
IN

ISP1362

WM8731

ADV7181

ADV7123

DM9000A
CON_A

FT245

CON_B

USB
BLASTER

M3128
LCD MODULE

EP2C35

SD CARD
EPCS16
SDRAM

SRAM

IrDA

FLASH

LED19

LED20

LED21

KEY0

KEY1

KEY2

KEY3

SW0

SW1

SW2

SW3

SW4

SW5

SW6

SW7

SW8

SW9

SW10

SW11

SW12

SW13

SW14

SW15

SW16

SW17

LED22

LED23

LED24

LED25

LED26
LED0

LED1

HEX0
LED2

HEX1
LED3

HEX2
LED4

LED5

LED6

HEX3

LED18
LED7

LED8

HEX4
LED9

HEX5
LED10

LED11

HEX6
LED12

LED13

LED14

LED15

LED16

LED17

HEX7

EXT CLK

Title
ALTERA DE2
Size
B
Date:
5

Document Number
PLACEMENT
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

of

24

AUDIO
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
I2C_SDAT
I2C_SCLK
AUD_XCK

AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
I2C_SDAT
I2C_SCLK
AUD_XCK

PAGE 4
AUD_ADCDAT

EP2S35

HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
HEX4_D[0..6]
HEX5_D[0..6]
HEX6_D[0..6]
HEX7_D[0..6]
LCD_BLON
LCD_ON
LCD_WR
LCD_D[0..7]
LCD_EN
LCD_RS
LED[0..26]

NCONFIG
TDI
TMS
CONF_DONE
NSTATUS
TCK
NCE
ASDO
SW[10..17]
GPIO_B[0..71]

ENET_RESET
25MHZ
ENET_CMD
ENET_IOR
ENET_IOW
ENET_CS
ENET_D[0..15]

ENET_RESET
25MHZ
ENET_CMD
ENET_IOR
ENET_IOW
ENET_CS
ENET_D[0..15]

INPUT
GPIO_B[0..71]
PS2_CLK
PS2_DAT
UART_TXD
IRDA_TXD

GPIO_B[0..71]
PS2_CLK
PS2_DAT
UART_TXD
IRDA_TXD

MEMORY
FLASH_RESET
FLASH_WE
FLASH_A[0..21]
FLASH_CE
FLASH_OE
DRAM_A[0..11]
DRAM_LDQM
DRAM_UDQM
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_D[0..15]
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_CS
SRAM_A[0..17]
SRAM_D[0..15]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_UB
SRAM_LB
SD_DAT
SD_CMD
SD_CLK
SD_DAT3

PAGE 5-6

HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
HEX4_D[0..6]
HEX5_D[0..6]
HEX6_D[0..6]
HEX7_D[0..6]
LCD_BLON
LCD_ON
LCD_WR
LCD_D[0..7]
LCD_EN
LCD_RS
LED[0..26]

ETHERNET
C

FLASH_RESET
FLASH_WE
FLASH_A[0..21]
FLASH_CE
FLASH_OE
DRAM_A[0..11]
DRAM_LDQM
DRAM_UDQM
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_D[0..15]
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_CS
SRAM_A[0..17]
SRAM_D[0..15]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_UB
SRAM_LB
SD_DAT
SD_CMD
SD_CLK
SD_DAT3

FLASH_D[0..7]
SD_DAT
KEY[0..3]
SW[6..9]
DCLK
NCSO
SRAM_D[0..15]
TD_D[0..7]
ENET_D[0..15]
TD_HS
TD_VS
27MHZ
ENET_INT
LINK_D0
LINK_D1
LINK_D2

PAGE 12

ENET_INT

ENET_INT

IN/OUT
SW[0..17]
UART_RXD
KEY[0..3]
50MHZ
EXT_CLOCK
IRDA_RXD

PAGE 7-11

SW[0..17]
UART_RXD
KEY[0..3]
50MHZ
EXT_CLOCK
IRDA_RXD

AUD_ADCDAT
I2C_SDAT
UART_RXD
PS2_DAT
SW[3..5]
OTG_DREQ1
OTG_DREQ0
OTG_INT1
OTG_INT0
OTG_D[0..15]
SW[0..2]
DRAM_D[0..15]
50MHZ
EXT_CLOCK
IRDA_RXD

NCONFIG
TDI
TMS
CONF_DONE
NSTATUS
TCK
NCE
ASDO
SW[10..17]
GPIO_B[0..71]

TDO
DATA0
LED[5..26]
FLASH_A[0..21]
SD_CLK
SD_CMD
SD_DAT3
HEX6_D[0..6]
HEX4_D[0..6]
HEX7_D[0..6]
HEX5_D[0..6]
FLASH_CE
FLASH_OE
FLASH_RESET
FLASH_WE
VGA_B[0..9]
VGA_CLOCK
VGA_R[0..9]
VGA_G[0..9]
VGA_BLANK
VGA_SYNC
VGA_VS
VGA_HS
TD_RESET
ENET_RESET
25MHZ
ENET_CMD
ENET_IOR
ENET_IOW
ENET_CS

FLASH_D[0..7]
SD_DAT
KEY[0..3]
SW[6..9]
DCLK
NCSO
SRAM_D[0..15]
TD_D[0..7]
ENET_D[0..15]
TD_HS
TD_VS
27MHZ
ENET_INT
LINK_D0
LINK_D1
LINK_D2
AUD_ADCDAT
I2C_SDAT
UART_RXD
PS2_DAT
SW[3..5]
OTG_DREQ1
OTG_DREQ0
OTG_INT1
OTG_INT0

LINK_D3
AUD_XCK
AUD_BCLK
AUD_DACDAT
AUD_DACLRCK
AUD_ADCLRCK
UART_TXD
PS2_CLK
LCD_D[0..7]
LCD_WR
LCD_EN
LCD_RS
LCD_BLON
LCD_ON
OTG_LSPEED
OTG_FSPEED
OTG_DACK1
OTG_DACK0
OTG_RESET
HEX3_D[0..6]
HEX2_D[0..6]
HEX1_D[0..6]
HEX0_D[0..6]
OTG_CS
OTG_OE
OTG_WE
OTG_A0
OTG_A1
LED[0..4]

OTG_D[0..15]
SW[0..2]
DRAM_D[0..15]
50MHZ
EXT_CLOCK
IRDA_RXD

PAGE 18-19
FLASH_D[0..7]

PWR

PAGE 20

USB BLASTER

PAGE 21

AUD_ADCDAT

DISPLAY

FLASH_D[0..7]

I2C_SCLK
DRAM_A[0..11]
DRAM_WE
DRAM_CLK
DRAM_CAS
DRAM_CKE
DRAM_RAS
DRAM_BA0
DRAM_CS
DRAM_BA1
DRAM_LDQM
DRAM_UDQM
SRAM_CE
SRAM_OE
SRAM_WE
SRAM_UB
SRAM_LB
SRAM_A[0..17]
IRDA_TXD

TDO
DATA0
LED[5..26]
FLASH_A[0..21]
SD_CLK
SD_CMD
SD_DAT3
HEX6_D[0..6]
HEX4_D[0..6]
HEX7_D[0..6]
HEX5_D[0..6]
FLASH_CE
FLASH_OE
FLASH_RESET
FLASH_WE
VGA_B[0..9]
VGA_CLOCK
VGA_R[0..9]
VGA_G[0..9]
VGA_BLANK
VGA_SYNC
VGA_VS
VGA_HS
TD_RESET
ENET_RESET
25MHZ
ENET_CMD
ENET_IOR
ENET_IOW
ENET_CS

LINK_D3
AUD_XCK
AUD_BCLK
AUD_DACDAT
AUD_DACLRCK
AUD_ADCLRCK
UART_TXD
PS2_CLK
LCD_D[0..7]
LCD_WR
LCD_EN
LCD_RS
LCD_BLON
LCD_ON
OTG_LSPEED
OTG_FSPEED
OTG_DACK1
OTG_DACK0
OTG_RESET
HEX3_D[0..6]
HEX2_D[0..6]
HEX1_D[0..6]
HEX0_D[0..6]
OTG_CS
OTG_OE
OTG_WE
OTG_A0
OTG_A1
LED[0..4]

DATA0
TDO
LINK_D3

DATA0
TDO
LINK_D3

NCSO
DCLK
ASDO
TMS
TDI
NCONFIG
TCK
CONF_DONE
NCE
NSTATUS
LINK_D0
LINK_D1
LINK_D2
12MHZ

USB DEVICE
OTG_WE
OTG_OE
OTG_RESET
OTG_DACK0
OTG_DACK1
OTG_CS
OTG_A1
OTG_A0
OTG_D[0..15]
OTG_LSPEED
OTG_FSPEED
12MHZ

PAGE 22

OTG_WE
OTG_OE
OTG_RESET
OTG_DACK0
OTG_DACK1
OTG_CS
OTG_A1
OTG_A0
OTG_D[0..15]
OTG_LSPEED
OTG_FSPEED
12MHZ

OTG_INT1
OTG_INT0
OTG_DREQ1
OTG_DREQ0

VIDEO
VGA_BLANK
VGA_R[0..9]
VGA_G[0..9]
VGA_B[0..9]
VGA_SYNC
VGA_CLOCK
VGA_HS
VGA_VS
TD_RESET
I2C_SDAT
I2C_SCLK

NCSO
DCLK
ASDO
TMS
TDI
NCONFIG
TCK
CONF_DONE
NCE
NSTATUS
LINK_D0
LINK_D1
LINK_D2
12MHZ

OTG_INT1
OTG_INT0
OTG_DREQ1
OTG_DREQ0

PAGE 23-24

VGA_BLANK
VGA_R[0..9]
VGA_G[0..9]
VGA_B[0..9]
VGA_SYNC
VGA_CLOCK
VGA_HS
VGA_VS
TD_RESET
I2C_SDAT
I2C_SCLK

TD_D[0..7]
TD_HS
27MHZ
TD_VS

TD_D[0..7]
TD_HS
27MHZ
TD_VS

I2C_SCLK
DRAM_A[0..11]
DRAM_WE
DRAM_CLK
DRAM_CAS
DRAM_CKE
DRAM_RAS
DRAM_BA0
DRAM_CS
DRAM_BA1
DRAM_LDQM
DRAM_UDQM
SRAM_CE
SRAM_OE
SRAM_WE
SRAM_UB
SRAM_LB
SRAM_A[0..17]
IRDA_TXD

Title
ALTERA DE2
Size
B
Date:

Document Number
TOP LEVEL
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

of

24

J2

R3

2K

C1 1U

R1

4.7K

C2 1U

R4

4.7K

NCL
R
NCR
L
GND

R2
D

2K

I2C_SCLK
I2C_SDAT

R5
4.7K

I2C ADDRESS READ IS 0x34


I2C ADDRESS WRITE IS 0x35

AGND

GND

AGND

AGND

5
2
4
1
3

C3

WM8731
QFN28-0.45

C4

21
20
19
18
17
16
15

10U
AGND
A_VCC33

R9
47K

C5

AGND

1000P
AGND

AGND

J3

AGND

LINEOUT

AUD_XCK
AUD_BCLK
AUD_DACDAT
AUD_DACLRCK
AUD_ADCDAT
AUD_ADCLRCK

TC1 100U/6.3V
C-1210+

A_VCC33

AGND
A_VCC33

BC1
0.1U
R12

BC2
0.1U

TC2 100U/6.3V
C-1210+

BC3
0.1U

BC4
0.1U

R10
47K

AGND

R11
47K

AGND

GND

NCL
R
NCR
L
GND

MBIAS
VMID
AGND
AVDD
ROUT
LOUT
HPGND

1U

680

5
2
4
1
3

MCLK
XTO
DCVDD
DGND
DBVDD
CLKO
BCLK

R8

8
9
10
11
12
13
14

DACDAT
DACLRCK
ADCDAT
ADCLRCK
HPVDD
LHPOUT
RHPOUT

SCLK
SDIN
CSB
MODE
LLINEIN
RLINEIN
MICIN

U1

330

28
27
26
25
24
23
22

R7

MICIN

NCL
R
NCR
L
GND

J1

1
2
3
4
5
6
7

R6
4.7K

I2C_SDAT
I2C_SCLK

A_VCC33
GND

LINEIN

VCC33

5
2
4
1
3

VCC33

AGND

AGND

Title
ALTERA DE2
Size
A
Date:
5

Document Number
AUDIO
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

of
1

24

Q1 8050
1

LED0
LED1
LED2
LED3

VCC43

2
680

2
4
6
8

LEDR0 LEDR
LEDR1 LEDR

330

GND

R14

1
3
5
7

C6
1U

R13
680

LCD_ON

RN1

Q2 8550
3

VCC5
D

LEDR2 LEDR

Q3
8050

LEDR3 LEDR

GND

GND

RN2

VCC43 Q4 8550
1
3

LED4
LED5
LED6
LED7

2
4
6
8

RN3
LED19
LED20
LED21
LED22

LEDR4 LEDR

1
3
5
7

LEDG0LEDG
2
4
6
8

LEDG1LEDG

LCD_BLON

1
3
5
7

R15

680

VCC43

R16
680

LCD_D[0..7]
LCD_RS
LCD_EN
LCD_WR
LED[0..26]

R17
1K

3
2

LEDR5 LEDR

330

LEDG2LEDG

330

LEDR6 LEDR

LEDG3LEDG
GND

Q5
8050

LEDR7 LEDR
GND

RN4
GND

R18
47

LCD_BL
LCD_D7
LCD_D6
LCD_D5
LCD_D4
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD_EN
LCD_WR
LCD_RS
LCD_CONT
LCD_VCC

GND

GND

LED8
LED9
LED18

1
3
5
7

2
4
6
8
330

RN5
LED23
LED24
LED25
LED26

LEDR8 LEDR
LEDR9 LEDR

1
3
5
7

LEDG4LEDG
2
4
6
8

330

LEDG5LEDG
C

LEDG6LEDG

GND
GND

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2 X 16 DIGIT LCD

LEDG7LEDG
GND

GND1
BL
D7
D6
D5
D4
D3
D2
D1
D0
EN
WR
RS
CONT
VCC
GND0

NC3
NC2
NC1
NC0

20
19
18
17

LEDG8LEDG

RN6
LED10
LED11
LED12
LED13

1
3
5
7

2
4
6
8
330

LEDR10LEDR
LEDR11LEDR
LEDR12LEDR
LEDR13LEDR

U2

GND

RN7

LCD16
LED14
LED15
LED16
LED17

1
3
5
7

2
4
6
8
330

LEDR14LEDR
LEDR15LEDR
LEDR16LEDR
LEDR17LEDR
GND

Title
ALTERA DE2
Size
B
Date:
5

Document Number
LCD AND LED
Friday, November 18, 2005

Rev
1.1
Sheet
1

of

24

HEX7
10 A

RN8

HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
HEX4_D[0..6]
HEX5_D[0..6]
HEX6_D[0..6]
HEX7_D[0..6]

HEX7_D0
HEX7_D1
HEX7_D2
HEX7_D3

1
3
5
7

2
4
6
8

A7
B7
C7
D7

8 C

4 E

RN10
1
3
5
7

9 B

2
4
6
8

VCC33

HEX6_D0
HEX6_D1
HEX6_D2
HEX6_D3

E7
F7
G7

2 F

2
4
6
8

9 B

A6
B6
C6
D6

8 C

HEX6_D4
HEX6_D5
HEX6_D6

3 G

1
3
5
7

2
4
6
8

HEX5_D0
HEX5_D1
HEX5_D2
HEX5_D3

1
3
5
7

3 G
7 DP

330

A5
B5
C5
D5

HEX5_D4
HEX5_D5
HEX5_D6

1
3
5
7

9 B
8 C

4 E

RN14
2
4
6
8

E5
F5
G5

2 F

VCC33

HEX4_D0
HEX4_D1
HEX4_D2
HEX4_D3

1
3
5
7

2
4
6
8

9 B

A4
B4
C4
D4

8 C

HEX4_D4
HEX4_D5
HEX4_D6

3 G

1
3
5
7

2
4
6
8

HEX3_D0
HEX3_D1
HEX3_D2
HEX3_D3

1
3
5
7

A3
B3
C3
D3

7 DP

4 E

RN18
1
3
5
7

9 B

2
4
6
8

VCC33

HEX2_D0
HEX2_D1
HEX2_D2
HEX2_D3

5 D

330
HEX3_D4
HEX3_D5
HEX3_D6

7Segment Display

E3
F3
G3

2 F

1
3
5
7

2
4
6
8

9 B

A2
B2
C2
D2

8 C

HEX2_D4
HEX2_D5
HEX2_D6

3 G

1
3
5
7

2
4
6
8

3 G
7 DP

330

HEX0_D0
HEX0_D1
HEX0_D2
HEX0_D3
HEX1
10 A

RN20
2
4
6
8

A1
B1
C1
D1

HEX0
10 A

4 E

RN22
HEX1_D4
HEX1_D5
HEX1_D6

1
3
5
7

2
4
6
8
330

E1
F1
G1

2 F

2
4
6
8

9 B

A0
B0
C0
D0

8 C

VCC33

HEX0_D4
HEX0_D5
HEX0_D6

1
3
5
7

VCC33

5 D
1

4 E

RN23

5 D

330

1
3
5
7
330

9 B
8 C

7Segment Display

RN21

1
3
5
7

2 F

E2
F2
G2

7Segment Display

HEX1_D0
HEX1_D1
HEX1_D2
HEX1_D3

4 E

RN19

VCC33

5 D

330

7 DP

330

HEX2
10 A

RN17

8 C

3 G

330

HEX3
10 A
2
4
6
8

2 F

E4
F4
G4

7Segment Display

RN16

4 E

RN15

VCC33

5 D

330

7 DP

330

HEX4
10 A

RN13

5 D

330
C

7Segment Display

HEX5
10 A
2
4
6
8

2 F

E6
F6
G6

7Segment Display

RN12

4 E

RN11

VCC33

5 D

330

7 DP

330

1
3
5
7

HEX6
10 A

RN9

5 D

330
HEX7_D4
HEX7_D5
HEX7_D6

2
4
6
8

2 F

E0
F0
G0

3 G
7 DP

330

7Segment Display

3 G

7 DP
7Segment Display
Title
ALTERA DE2
Size
B
Date:

Document Number
7 SEGMENT
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

of

24

U11A
HEX7_D[0..6]
HEX6_D[0..6]
HEX5_D[0..6]
HEX4_D[0..6]

DRAM_D[0..15]
DRAM_A[0..11]
DRAM_UDQM
DRAM_LDQM
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_CS

LCD_ON
LCD_BLON
LCD_RS
LCD_EN
LCD_WR
LCD_D[0..7]
SW[10..17]

OTG_INT1
OTG_INT0
OTG_DREQ1
OTG_DREQ0
OTG_DACK1
OTG_DACK0
OTG_RESET
OTG_A1
OTG_A0
OTG_CS
OTG_WE
OTG_OE
OTG_LSPEED
OTG_FSPEED
B

OTG_D[0..15]
50MHZ

GND
VCC12
GND
DRAM_CKE
DRAM_CLK
DRAM_CS
DRAM_RAS
DRAM_CAS
DRAM_BA1
DRAM_BA0
DRAM_WE
DRAM_LDQM
DRAM_UDQM
DRAM_D15
DRAM_D14
DRAM_D13
DRAM_D12
DRAM_D11
DRAM_D10
DRAM_D9
DRAM_D8
DRAM_D7
DRAM_D6
DRAM_D5
DRAM_D4
DRAM_D3
DRAM_D2
DRAM_D1
DRAM_D0
DRAM_A11
DRAM_A10
DRAM_A9
DRAM_A8
DRAM_A7
DRAM_A6
DRAM_A5
DRAM_A4
DRAM_A3
DRAM_A2
DRAM_A1
DRAM_A0
SW13
SW17
SW16
SW15
SW14
HEX4_D0
HEX4_D1
HEX4_D2
HEX4_D3
HEX4_D4
HEX4_D5
HEX4_D6
HEX5_D0
HEX5_D1
HEX5_D2
HEX5_D3
HEX5_D4
HEX5_D5
HEX5_D6
HEX6_D0
HEX6_D1
HEX6_D2
SW11
SW12

Y6
Y7
W7
AA6
AA7
AC3
AB4
AB3
AE3
AE2
AD3
AD2
Y5
AA5
AC1
AC2
AA3
AA4
AB1
AB2
W6
V7
T8
R8
Y4
Y3
AA1
AA2
V6
V5
Y1
W3
W4
U5
U7
U6
W1
W2
V3
V4
T6
T7
V2
V1
U4
U3
U10
U9
U1
U2
T4
R7
R6
T3
T2
P6
P7
T9
T10
R5
R4
R3
R2
P4
P3
P1
P2

U11B

GND_PLL1
VCCD_PLL1
GND_PLL1
PLL1_OUTN
PLL1_OUTP
B1_IO_0
B1_L0N
B1_L0P
B1_L1N
B1_L1P
B1_L2N
B1_L2P
B1_L3N
B1_L3P
B1_L4N
B1_L4P
B1_L5N
B1_L5P
B1_L6N
B1_L6P
B1_VREFN1
B1_IO_1
B1_L7N
B1_L7P
B1_L8N
B1_L8P
B1_L9N
B1_L9P
B1_L10N
B1_L10P
B1_IO_2
B1_L11N
B1_L11P/CDPCLK1
B1_IO_3
B1_L12N
B1_L12P
B1_L13N
B1_L13P
B1_L14N
B1_L14P
B1_L15N
B1_L15P
B1_L16N
B1_L16P
B1_L17N
B1_L17P
B1_L18N
B1_L18P
B1_L19N
B1_L19P
B1_VREFN0
B1_L20N
B1_L20P
B1_L21N
B1_L21P
B1_L22N
B1_L22P
B1_L23N
B1_L23P
B1_L24N
B1_L24P
B1_L25N
B1_L25P
B1_L26N
B1_L26P/DPCLK1
CLK3
CLK2

SW10
50MHZ
HEX6_D3
HEX6_D4
HEX6_D5
HEX6_D6

BANK1

N1
N2
M2
M3
M5
M4
L10
L3
L2
L9
L6
L7
P9
N9
L4
K2
K1
K3
K4
J1
J2
H1
H2
J4
J3
H4
H3
G2
G1
F1
F2
K7
K8
J6
G3
G4
K5
K6
E1
E2
H6
J7
J8
J5
F7
D1
D2
F4
F3
G6
G5
C3
C2
F6
E5
B3
B2
G7
H7
E4

HEX7_D0
HEX7_D1
HEX7_D2
HEX7_D3
HEX7_D4
HEX7_D5
HEX7_D6
LCD_ON
LCD_BLON
LCD_RS
LCD_EN
LCD_WR
LCD_D0
LCD_D1
LCD_D2
LCD_D3
LCD_D4
LCD_D5
LCD_D6
LCD_D7
OTG_OE
OTG_WE
OTG_CS
OTG_A1
OTG_A0
OTG_D15
OTG_D14
OTG_D13
OTG_D12
OTG_D11
OTG_D10
OTG_D9
OTG_D8
OTG_D7
OTG_D6
OTG_D5
OTG_D4
OTG_D3
OTG_D2
OTG_D1
OTG_D0
OTG_FSPEED
OTG_LSPEED
OTG_RESET
OTG_INT1
OTG_DACK0
OTG_DREQ0
OTG_DREQ1
OTG_INT0
OTG_DACK1
GND
VCC12
GND

CYCLONE II EP2C35

CLK1
CLK0
B2_L27N
B2_L27P/DPCLK0
B2_L28N
B2_L28P
B2_IO_0
B2_L29N
B2_L29P
B2_IO_1
B2_L30N
B2_L30P
B2_L31N
B2_L31P
B2_VREFN1
B2_L32N
B2_L32P
B2_L33N
B2_L33P
B2_L34N
B2_L34P
B2_L35N
B2_L35P
B2_L36N
B2_L36P
B2_L37N
B2_L37P
B2_L38N
B2_L38P/CDPCLK0
B2_L39N
B2_L39P
B2_L40N
B2_L40P
B2_IO_2
B2_L41N
B2_L41P
B2_L42N
B2_L42P
B2_L43N
B2_L43P
B2_IO_3
B2_L44N
B2_L44P
B2_VREFN0
B2_IO_4
B2_L45N
B2_L45P
B2_L46N
B2_L46P
B2_L47N
B2_L47P
B2_L48N
B2_L48P
PLL3_OUTN
PLL3_OUTP
B2_L49N/CLKUSR
B2_L49P/CRCERR
GND_PLL3
VCCD_PLL3
GND_PLL3

BANK2

CYCLONE II EP2C35

VCCINT
VCC12
A

BC5
0.1U

BC6
0.1U

GND

GND

Title
ALTERA DE2
Size
B
Date:

Document Number
EP2C35 BANK1 AND BANK 2
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

of

24

U11C

SW[7..9]
VGA_R[0..9]
VGA_G[0..9]
VGA_B[0..9]
VGA_BLANK
VGA_SYNC
VGA_CLOCK
VGA_HS
VGA_VS

TD_D[0..7]
TD_RESET
TD_HS
TD_VS
27MHZ
C

ENET_D[0..15]
ENET_IOW
ENET_IOR
ENET_CMD
ENET_CS
ENET_RESET
ENET_INT

AUD_XCK
AUD_BCLK
AUD_DACDAT
AUD_DACLRCK
AUD_ADCLRCK
AUD_ADCDAT

I2C_SDAT
I2C_SCLK
LINK_D0
LINK_D1
LINK_D2
LINK_D3

VCC12
GND
AUD_ADCLRCK
AUD_DACLRCK
AUD_DACDAT
AUD_BCLK
AUD_XCK
AUD_ADCDAT
I2C_SDAT
I2C_SCLK
TD_RESET
TD_HS
TD_VS
TD_D0
TD_D1
TD_D2
TD_D3
TD_D4
TD_D5
TD_D6
TD_D7
VGA_BLANK
VGA_SYNC
VGA_HS
VGA_VS
VGA_R0
VGA_R1
VGA_R2
VGA_R3
VGA_R4
VGA_CLOCK
VGA_R5
VGA_R6
VGA_R7
VGA_R8
VGA_R9
VGA_G0
VGA_G1
VGA_G2
VGA_G3
VGA_G4
VGA_G5
VGA_G6
VGA_G7
VGA_G8
VGA_G9
VGA_B0
VGA_B1
VGA_B2
VGA_B3
VGA_B4
VGA_B5
VGA_B6
VGA_B7
VGA_B8
VGA_B9
27MHZ
SW7

G8
F8
C5
C6
A4
B4
A5
B5
B6
A6
C4
D5
K9
J9
E8
H8
H10
G9
F9
D7
C7
D6
B7
A7
D8
C8
F10
G10
D9
C9
B8
A8
H11
H12
F11
E10
B9
A9
C10
D10
B10
A10
G11
D11
E12
D12
J13
J14
F12
G12
J10
J11
C11
B11
C12
B12
D13
C13

U11D

VCCA_PLL3
GNDA_PLL3
B3_L50N/DEV_CLRN
B3_L50P
B3_L51P
B3_L51N
B3_L52P
B3_L52N
B3_L53P/CDPCLK7
B3_L53N
B3_L54P
B3_L54N
B3_L55P
B3_L55N
B3_VREFN1
B3_IO_0
B3_L56P
B3_L56N
B3_IO_1
B3_L57P
B3_L57N
B3_IO_2
B3_L58P
B3_L58N
B3_L59P
B3_L59N
B3_L60P
B3_L60N
B3_L61P
B3_L61N
B3_L62P/DPCLK11
B3_L62N
B3_L63P
B3_L63N
B3_L64P
B3_L64N
B3_L65P
B3_L65N
B3_L66P
B3_L66N
B3_L67P
B3_L67N
B3_IO_3
B3_VREFN0
B3_L68P
B3_L68N
B3_L69P
B3_L69N
B3_L70P
B3_L70N
B3_L71P
B3_L71N
B3_L72P
B3_L72N
B3_L73P/DPCLK10
B3_L73N
CLK11
CLK10

SW9
SW8
LINK_D0
LINK_D1
LINK_D2
LINK_D3

ENET_D7
ENET_D6

ENET_D5
ENET_D4

ENET_D3
ENET_D2
ENET_D1
ENET_D0

BANK3

ENET_D15
ENET_D14
ENET_D13
ENET_D12
ENET_D11
ENET_D10
ENET_D9
ENET_D8

ENET_CMD
ENET_INT
ENET_IOW
ENET_IOR
ENET_CS
ENET_RESET

GND
VCC12

CYCLONE II EP2C35

A13
B13
B14
A14
D14
F14
G14
F13
G13
C15
B15
B16
C16
D15
E15
D16
H15
H16
A17
B17
G15
F15
F16
G16
A18
B18
C17
D17
G17
F17
H17
J17
F18
G18
D18
E18
A19
B19
D19
C19
A20
B20
E20
D20
K16
J16
K17
J18
A21
B21
B22
A22
A23
B23
D21
C21
C22
C23
F19
G19

CLK9
CLK8
B4_L74P/DPCLK9
B4_L74N
B4_IO_0
B4_L75P
B4_L75N
B4_L76P
B4_L76N
B4_L77P
B4_L77N
B4_L78P
B4_L78N
B4_L79P
B4_L79N
B4_VREFN1
B4_L80P
B4_L80N
B4_L81P
B4_L81N
B4_L82P
B4_L82N
B4_L83P
B4_L83N
B4_L84P
B4_L84N
B4_L85P/DPCLK8
B4_L85N
B4_L86P
B4_L86N
B4_L87P
B4_L87N
B4_L88P
B4_L88N
B4_L89P
B4_L89N
B4_L90P
B4_L90N
B4_L91P
B4_L91N
B4_L92P
B4_L92N
B4_VREFN0
B4_IO_1
B4_L93P
B4_L93N
B4_L94P
B4_L94N
B4_L95P
B4_L95N
B4_L96P/CDPCLK6
B4_L96N
B4_L97P
B4_L97N
B4_L98P
B4_L98N
B4_L99P
B4_L99N
GNDA_PLL2
VCCA_PLL2

BANK4

CYCLONE II EP2C35

VCCINT
VCC12

BC7
0.1U

BC8
0.1U
Title

GND

ALTERA DE2

GND
Size
B
Date:

Document Number
EP2C35 BANK3 AND BANK 4
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

of

24

U11E
GND
VCC12
GND

UART_RXD
UART_TXD
PS2_DAT
PS2_CLK
SD_CMD
SD_CLK
SD_DAT
25MHZ
GPIO_B[0..71]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]

KEY[0..3]
SW[0..2]
EXT_CLOCK
IRDA_RXD
IRDA_TXD
SD_DAT3

25MHZ
UART_TXD
UART_RXD
PS2_DAT
PS2_CLK
GPIO_B0
GPIO_B1
GPIO_B2
GPIO_B3
GPIO_B4
GPIO_B5
GPIO_B6
GPIO_B7
GPIO_B8
GPIO_B9
GPIO_B10
GPIO_B11
GPIO_B12
GPIO_B13
GPIO_B14
GPIO_B15
KEY0
GPIO_B16
GPIO_B17
GPIO_B18
GPIO_B19
GPIO_B20
GPIO_B21
GPIO_B22
GPIO_B23
GPIO_B24
GPIO_B25
GPIO_B26
GPIO_B27
GPIO_B28
GPIO_B29
GPIO_B30
GPIO_B31
GPIO_B32
GPIO_B33
GPIO_B34
GPIO_B35
GPIO_B36
GPIO_B37
GPIO_B38
GPIO_B39
GPIO_B40
GPIO_B41
GPIO_B42
GPIO_B43
GPIO_B44
GPIO_B45
KEY1
GPIO_B46
SW0
SW1

E21
H20
G20
F20
F21
E22
D23
G21
G22
H21
E23
E24
B24
B25
C25
C24
D26
D25
J22
E26
E25
F24
F23
J21
J20
F25
F26
N18
P18
G23
G24
K22
G25
G26
H23
H24
J23
J24
H25
H26
H19
K18
K19
K21
K23
K24
L21
L20
J25
J26
L23
L24
L25
L19
K25
K26
M22
M23
M19
M20
N20
M21
M24
M25
N23
N24
N25
N26

U11F

GND_PLL2
VCCD_PLL2
GND_PLL2
PLL2_OUTN
PLL2_OUTP
B5_L100P
B5_L100N
B5_L101P
B5_L101N
B5_IO_0
B5_L102P
B5_L102N
B5_L103P
B5_L103N
B5_L104P
B5_L104N
B5_L105P
B5_L105N
B5_VREFN0
B5_L106P
B5_L106N
B5_L107P
B5_L107N
B5_L108P
B5_L108N
B5_L109P
B5_L109N
B5_L110P
B5_L110N
B5_L111P
B5_L111N
B5_IO_1
B5_L112P/CDPCLK5
B5_L112N
B5_L113P
B5_L113N
B5_L114P
B5_L114N
B5_L115P
B5_L115N
B5_IO2
B5_L116P
B5_L116N
B5_IO_3
B5_L117P
B5_L117N
B5_L118P
B5_L118N
B5_L119P
B5_L119N
B5_VREFN1
B5_L120P
B5_L120N
B5_IO_4
B5_L121P
B5_L121N
B5_L122P
B5_L122N
B5_L123P
B5_L123N
B5_L124P
B5_L124N
B5_L125P
B5_L125N
B5_L126P/DPCLK7
B5_L126N
CLK4
CLK5

SW2
EXT_CLOCK
KEY2
GPIO_B47
GPIO_B48
GPIO_B49
GPIO_B50
GPIO_B51
GPIO_B52
GPIO_B53
GPIO_B54
GPIO_B55
GPIO_B56
GPIO_B57
GPIO_B58
GPIO_B59
GPIO_B60
GPIO_B61
GPIO_B62
GPIO_B63
GPIO_B64
GPIO_B65
GPIO_B66
GPIO_B67
GPIO_B68
GPIO_B69
KEY3
GPIO_B70
GPIO_B71
HEX3_D6
HEX3_D5
HEX3_D4
HEX3_D3
HEX3_D2
HEX3_D1
HEX3_D0
HEX2_D6
HEX2_D5
HEX2_D4
HEX2_D3
HEX2_D2
HEX2_D1
HEX2_D0
HEX1_D6
HEX1_D5
HEX1_D4
HEX1_D3
HEX1_D2
HEX1_D1
HEX1_D0
SD_CMD
SD_DAT
SD_CLK
IRDA_TXD
IRDA_RXD
SD_DAT3
GND
VCC12
GND

BANK5

CYCLONE II EP2C35

P25
P26
P23
P24
R25
R24
R20
T22
T23
R17
P17
T24
T25
T18
T17
T21
T20
U26
U25
U23
U24
R19
T19
U20
U21
V26
V25
V24
V23
W26
W25
W23
W24
U22
Y25
Y26
AA26
AA25
Y23
Y24
AB25
AB26
AC26
AC25
V22
AB23
AB24
AA23
AA24
Y22
W21
V21
V20
Y21
AD24
AD25
AE24
AE25
AC23
W20
Y20
AA21

CLK6
CLK7
B6_L127P/DPCLK6
B6_L127N
B6_L128P
B6_L128N
B6_IO_0
B6_L129P
B6_L129N
B6_L130P
B6_L130N
B6_L131P
B6_L131N
B6_L132P
B6_L132N
B6_VREFN0
B6_IO_1
B6_L133P
B6_L133N
B6_L134P
B6_L134N
B6_L135P
B6_L135N
B6_L136P
B6_L136N
B6_L137P
B6_L137N
B6_L138P
B6_L138N
B6_L139P/CDPCLK4
B6_L139N
B6_L140P
B6_L140N
B6_IO_2
B6_L141P
B6_L141N
B6_L142P
B6_L142N
B6_L143P
B6_L143N
B6_L144P
B6_L144N
B6_L145P
B6_L145N
B6_VREFN1
B6_L146P
B6_L146N
B6_L147P
B6_L147N
B6_L148P
B6_L148N
PLL4_OUTP
PLL4_OUTN
B6_IO_3
B6_L149P
B6_L149N
B6_L150P/NCEO
B6_L150N/INIT_DONE
B6_IO_4
GND_PLL4
VCCD_PLL4
GND_PLL4

BANK6

CYCLONE II EP2C35

VCCINT
VCC12

BC9
0.1U

BC10
0.1U
Title

GND

ALTERA DE2

GND
Size
B
Date:

Document Number
EP2C35 BANK5 AND BANK 6
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

of

24

U11G

LED[0..26]
SW[3..6]

SRAM_D[0..15]
SRAM_A[0..17]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_UB
SRAM_LB
FLASH_RESET
FLASH_CE
FLASH_OE
FLASH_WE
FLASH_A[0..21]
FLASH_D[0..7]
HEX0_D[0..6]

VCC12
GND
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED19
LED20
LED21
LED22
LED23
LED24
LED25
LED26
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_RESET
FLASH_WE
FLASH_CE
FLASH_OE
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
LED8
LED9
LED10
LED11
LED12
LED13
SW3
SW4

AA19
Y19
AE23
AF23
AB21
AC22
AD22
AD23
AD21
AC21
AE22
AF22
W19
V18
U18
U17
AA20
Y18
AE21
AF21
AC20
AB20
AE20
AF20
AC19
AD19
AA18
AA17
V17
W17
AC18
AB18
AE19
AF19
AE18
AF18
Y16
AA16
AD17
AC17
AE17
AF17
W16
W15
AC16
AD16
AE16
AC15
AB15
AA15
Y15
Y14
AA14
Y13
AA13
AC14
AD15
AE15
AE14
AF14

U11H

VCCA_PLL4
GNDA_PLL4
B7_L151N
B7_L151P
B7_L152N
B7_L152P
B7_L153N
B7_L153P
B7_L154N
B7_L154P/CDPCLK3
B7_L155N
B7_L155P
B7_L156N
B7_L156P
B7_L157N
B7_L157P
B7_IO_0
B7_VREFN0
B7_L158N
B7_L158P
B7_L159N
B7_L159P
B7_L160N
B7_L160P
B7_L161N
B7_L161P
B7_L162N
B7_L162P
B7_L163N
B7_L163P
B7_L164N
B7_L164P
B7_L165N
B7_L165P/DPCLK5
B7_L166N
B7_L166P
B7_L167N
B7_L167P
B7_L168N
B7_L168P
B7_L169N
B7_L169P
B7_L170N
B7_L170P
B7_VREFN1
B7_L171N
B7_L171P
B7_L172N
B7_L172P
B7_L173N
B7_L173P
B7_L174N
B7_L174P
B7_L175N
B7_L175P
B7_IO_1
B7_L176N
B7_L176P
CLK12
CLK13

SW5
SW6
LED14
LED15
LED16
LED17
LED18

HEX0_D6
HEX0_D5
HEX0_D4
HEX0_D3
HEX0_D2
HEX0_D1
HEX0_D0
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_UB
SRAM_LB
SRAM_D15
SRAM_D14
SRAM_D13
SRAM_D12
SRAM_D11
SRAM_D10
SRAM_D9
SRAM_D8
SRAM_D7
SRAM_D6
SRAM_D5
SRAM_D4
SRAM_D3
SRAM_D2
SRAM_D1
SRAM_D0
SRAM_A17
SRAM_A16
SRAM_A15
SRAM_A14
SRAM_A13
SRAM_A12
SRAM_A11
SRAM_A10
SRAM_A9
SRAM_A8
SRAM_A7
SRAM_A6
SRAM_A5
SRAM_A4
SRAM_A3
SRAM_A2
SRAM_A1
SRAM_A0
GND
VCC12

BANK7

CYCLONE II EP2C35

AD13
AC13
AF13
AE13
AE12
AD12
Y12
AA12
U12
V11
V13
V14
AE11
AD11
AC12
AB12
AF10
AE10
AC11
AD10
AF9
AE9
AC10
AC9
W12
W11
AF8
AE8
AF7
AE7
Y11
AA11
AB10
AA10
AA9
AF6
AE6
AD8
AC8
AB8
Y10
W10
W8
AC7
V9
V10
AD7
AD6
AF5
AE5
AD5
AD4
AC6
AC5
AF4
AE4
Y8
AA8

CLK14
CLK15
B8_L177N
B8_L177P/DPCLK3
B8_L178N
B8_L178P
B8_L179N
B8_L179P
B8_L180N
B8_L180P
B8_L181N
B8_L181P
B8_L182N
B8_L182P
B8_VREFN0
B8_IO_0
B8_L183N
B8_L183P
B8_L184N
B8_L184P
B8_L185N
B8_L185P
B8_L186N
B8_L186P
B8_L187N
B8_L187P
B8_L188N
B8_L188P/DPCLK2
B8_L189N
B8_L189P
B8_L190N
B8_L190P
B8_L191N
B8_L191P
B8_IO_1
B8_L192N
B8_L192P
B8_L193N
B8_L193P
B8_IO_2
B8_L194N
B8_L194P
B8_IO_3
B8_VREFN1
B8_L195N
B8_L195P
B8_L196N
B8_L196P
B8_L197N
B8_L197P
B8_L198N
B8_L198P
B8_L199N
B8_L199P
B8_L200P
B8_L200N/DEV_OE
GNDA_PLL1
VCCA_PLL1

BANK8

CYCLONE II EP2C35
VCCINT

VCC12
BC11
0.1U

BC12
0.1U

Title
ALTERA DE2

GND

GND
Size
B
Date:

Document Number
EP2C35 BANK7 AND BANK 8
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

10

of

24

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

BC15
0.1U

BC16
0.1U

BC17
0.1U

W9
V12
AF11
AF3
AB13
AB9
AB6

VCCIO

BC18
0.1U

VCCINT
Y17
Y9
W22
W14
W13
W5
U19
U8
AF25
AF15
AF12
AF2
AE26
AE1
AD18
AD14
AD9
AC4
AB19
AB16
AB11
AB7

BC14
0.1U

GND

VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8
VCCIO8

W18
V15
AF24
AF16
AD20
AB22
AB17
AB14
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7

V19
T26
R18
P22
AD26
AA22
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6

N22
M18
L26
J19
F22
C26
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5

J15
H18
E17
E14
D22
C20
A24
A16
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4

N5
M9
L1
F5
C1

J12
H9
E13
E9
E6
A11
A3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3

VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO1

U11I

VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2

V8
T1
R9
P5
AD1
AB5

BC13
0.1U

VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT

EP2C35-672 PIN POWER

GND

V16
U16
U15
U14
U13
U11
T16
T11
R16
R11
R10
P10
N17
N10
M17
M16
M11
M10
L18
L17
L16
L11
K15
K14
K13
K12
K11
K10

BC19
0.1U

BC20
0.1U

BC21
0.1U

BC22
0.1U

BC24
0.1U

BC25
0.1U

BC26
0.1U

BC27
0.1U

GND
VCCIO

BC23
0.1U
GND
VCCIO

BC28
0.1U

BC29
0.1U

BC30
0.1U

BC31
0.1U

BC32
0.1U

BC34
0.1U

BC35
0.1U

BC36
0.1U

BC37
0.1U

GND
VCCINT

BC33
0.1U

BC38
0.1U

BC39
0.1U

BC40
0.1U

T5
R26
R21
R1
P19
P8
N19
N8
M26
M1
L22
L5
K20
H22
H14
H13
H5
E19
E16
E11
E7
D24
D4
C18
C14
B26
B1
A25
A15
A12
A2
T15
T14
T13
T12
R15
R14
R13
R12
P16
P15
P14
P13
P12
P11
N16
N15
N14
N13
N12
N11
M15
M14
M13
M12
L15
L14
L13
L12

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

CYCLONE II EP2C35

GND

U11J
CONF_DONE
NSTATUS
NCONFIG
NCE
ASDO
NCSO
TDI
TCK
TMS
TDO
DCLK
DATA0
NCONFIG
NCE

TDI
TMS
TCK
TDO
ASDO
DCLK
NCSO
DATA0

E3
D3
M8
M6
L8
M7
N6
N3
N7
N4

ASDO
NCSO
TDI
TCK
TMS
TDO
DCLK
DATA0
NCONFIG
NCE

NSTATUS
CONF_DONE
MSEL1
MSEL0
NC0
NC1
NC2

R22
R23
P21
P20
Y2
N21
AC24

NSTATUS
CONF_DONE
GND
GND

EP2C35 CTRL AND CONFIG


Title

CYCLONE II EP2C35

ALTERA DE2
Size
B
Date:
5

Document Number
EP2C35 POWER AND CONFIG
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

11

of

24

ENET_D7
ENET_D6
ENET_D5
ENET_D4
ENET_D3
ENET_D2
ENET_D1
ENET_D0
ENET_D15
ENET_D14

N_VCC33

SD14
VDD
SD15
EEDCS
EEDCK
EEDIO
SD0
SD1
SD2
GND
SD3
SD4

24
23
22
21
20
19
18
17
16
15
14
13

GND
U35

NGND

C7
0.1U

ENET_INT
ENET_IOR
ENET_IOW

N_VCC33

37
38
39
40
41
42
43
44
45
46
47
48

R34
4.7K

NGND

RXRX+

1
2
3
4
5
6
7
8

N_VCC25
L1

N_VCC25

BEAD

R21
49R9

R22
49R9

TD+
TDRD+
CTT
CTR
RDNC
CHSG

16

14

J4
TXTX+

C8
R30
6.8K

DM9000AE/LQFP48

BC57
0.1U

BC58
0.1U

TC30
100U/6.3V
C-1210+

CHSGND

D3

11

YELLOW D4

12

D2

10

MNT0

R20
49R9

SMNT1

R19
49R9

MNT1

GND

ENET_D8
ENET_CMD

12
11
10
9
8
7
6
5
4
3
2
1

SMNT0

N_VCC33

CHSGND

SD5
SD6
SD7
AVDD25
TXTX+
AGND
AGND
RXRX+
AVDD25
BGRES

15

R27
4.7K

DM9000A-8/16bit
SD13
SD12
SD11
SD10
SD9
VDD
SD8
CMD
GND
INT
IOR#
IOW#

13

N_VCC33

25
26
27
28
29
30
31
32
33
34
35
36

CS#
LED2(IOWAIT / WAKEUP for eeprom)
LED1(IO16 for eeprom)
PWRST#
TEST
VDD
X2
X1
GND
SD
AGND
BGGND

ENET_D13
ENET_D12
ENET_D11
ENET_D10
ENET_D9

GREEN D1
RJ45INTLED

N_VCC33

N_VCC33

CHSGND

0.1U
NGND

ENET_RESET
N_VCC33
B

ENET_CS
ACT
SPEED
25MHZ

L7
NGND

BEAD
SPEED
ACT

GND

R28
R29

GND

NGND

NGND

BC51
0.1U
ENET_D[0..15]
ENET_RESET
ENET_INT
ENET_IOR
ENET_IOW
ENET_CS
ENET_CMD
25MHZ

N_VCC33

BC52
0.1U

N_VCC25
CHSGND

BC53
0.1U

120
120

BC54
0.1U

BC55
0.1U

BC56
0.1U

BC59
0.1U

GND

CHSGND

BC60
0.1U

NGND

Title
ALTERA DE2
Size
B
Date:
5

Document Number
DM9000AE
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

12

of

24

U14
1
2
3
4
5
6
7
8
9

GND
VCC33

R23

120

R24

120

IRDA_RXD
IRDA_TXD

GND

VCC33

J5

47

IRDA

R25

GND
IOVCC
VCC
AGND
SD
RXD
TXD
VLED
SHIELD

C11
1U
1

C12
1U

GND

GND

EXT CLOCK
VCC33
C

R35
1K

GND

BC41
0.1U

BC42
0.1U

BC43
0.1U

GND
VCC33

GND

GND

GND

Y1
BC61
0.1U

OSC_EN

EN

VCC

GND

OUT

GND

50MHZ

50MHZ
EXT_CLOCK

IRDA_RXD
IRDA_TXD

Title
ALTERA DE2
Size
A
Date:
5

Document Number
CLOCK
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

13

of
1

24

UART_RXD
D

RXD

LEDR

1
3
5
7

2
4
6
8

RXD

RN24 330
TXD

J6

U15

VCC33
LEDG

UART_TXD

13
8
11
10

R1IN
R2IN
T1IN
T2IN

1
3
4
5
2
6

C+
C1C2+
C2V+
V-

C13
1U
C14
1U

R1OUT
R2OUT
T1OUT
T2OUT

12
9
14
7

VCC
GND

16
15

VCC33

C15
1U
GND

11

10

RS232
MAX232

1
6
2
7
3
8
4
9
5

GND

GND

C16
1U
GND

VCC5

VCC5
R36

R37

2K

2K

PS2_DAT
PS2_CLK

R38
R39

120
120

J7

D2
BAT54S

D1
BAT54S

VCC5
GND

BC62
0.1U
GND

VCC33 GND

1
2
3
4
5
6
7
8
9

GND
GND
GND

VCC33

TOP

NC0
DAT
VCC
GND
NC1
CLK
SHIELD0
SHIELD1
SHIELD2

6
4

3
1

PS2

GND

Title
ALTERA DE2
Size
A
Date:
5

Document Number
PS2 AND RS232
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

14

of
1

24

RN25
1
3
5
7

2
4
6
8

VCC33

U16

4.7K

GND
KEYIN0
KEYIN1
KEYIN2
KEYIN3
KEY0
1
2

4
3

PBSW

KEY1
1
2

4
3

PBSW

KEY2
1
2

KEY3
1
2

4
3

PBSW

4
3

C17
0.1U

C18
0.1U

C19
0.1U

C20
0.1U

PBSW
GND

10

GND

9
8
7
6
5
4
3
2
1

A8
A7
A6
A5
A4
A3
A2
A1
DIR

VCC

20

VCC33 RN26

B8
B7
B6
B5
B4
B3
B2
B1
G

11
12
13
14
15
16
17
18
19

2
4
6
8

KEY0
KEY1
KEY2
KEY3

1
3
5
7
120

GND

VCC33
74HC245
DIP20-SOP

GND
C

SW0

SW1
5
1
2
3
4

GND
VCC33
SW0
GND
GND

DPDT SW

GND
VCC33
SW1
GND
GND

DPDT SW

SW8
GND
VCC33
SW8
GND
GND

DPDT SW

GND
VCC33
SW9
GND
GND

GND
VCC33
GND
GND

DPDT SW

DPDT SW

GND
VCC33

GND
VCC33
SW10
GND
GND

SW5
5
1
2
3
4

DPDT SW

GND
VCC33
SW11
GND
GND

DPDT SW

GND
GND

GND
VCC33
SW5
GND
GND

DPDT SW

SW7
5
1
2
3
4

GND
VCC33
SW6
GND
GND

5
1
2
3
4

DPDT SW

GND
VCC33
SW7
GND
GND

DPDT SW

SW13
5
1
2
3
4

DPDT SW

GND
VCC33

5
1
2
3
4

SW12
5
1
2
3
4

SW6

GND
VCC33
SW4
GND
GND

GND
VCC33
SW12
GND
GND

5
1
2
3
4

DPDT SW

GND
VCC33
SW13
GND
GND

R40

120

DPDT SW
RN27

SW17
5
1
2
3
4

GND
GND

GND
VCC33
SW3
GND
GND

SW11
5
1
2
3
4

SW16
5
1
2
3
4

SW4
5
1
2
3
4

DPDT SW

DPDT SW

SW15
5
1
2
3
4

GND
VCC33
SW2
GND
GND

SW10
5
1
2
3
4

DPDT SW

SW14

SW3
5
1
2
3
4

DPDT SW

SW9
5
1
2
3
4

SW2
5
1
2
3
4

5
1
2
3
4

GND
VCC33

2
4
6
8

GND
GND

1
3
5
7

SW17
SW16
SW15
SW14

120

DPDT SW

KEY[0..3]
SW[0..17]

Title
ALTERA DE2
Size
A
Date:

Document Number
KEY AND SWITCH
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

15

of
1

24

VCC33

GND

GND

VCC33

GND

VCC33

VCC33

GND

2
VCC33

GND

VCC33

GND

VCC33
C

GPIO_B35

D38
BAT54S

GPIO_B34

GPIO_B26

D29
BAT54S

GPIO_B17

2
2

GPIO_B25

VCC33

GND

VCC33

D37
BAT54S

D20
BAT54S

GPIO_B8

1
3

1
3

GND

GND

GPIO_B33

GPIO_B16

D36
BAT54S

VCC33

3
3

GND

GND

VCC33

D28
BAT54S

GPIO_B32

VCC33

GND

GPIO_B24

D27
BAT54S

VCC33

D11
BAT54S

GPIO_B7

VCC33

D19
BAT54S

GPIO_B15

GND

GPIO_B23

GND

VCC33

D18
BAT54S

D10
BAT54S

VCC33

D35
BAT54S

GND

GND

GPIO_B31

GPIO_B14

GPIO_B6

1
1

VCC33

D9
BAT54S

VCC33

D26
BAT54S

GND

GPIO_B22

GPIO_B5

VCC33

1
3

1
GND

D17
BAT54S

GPIO_B13

VCC33

GND
D34
BAT54S

GND

GPIO_B30

GND
D25
BAT54S

D8
BAT54S

VCC33

1
1

2
VCC33

VCC33

D33
BAT54S

GPIO_B21

GND
D16
BAT54S

GPIO_B4

2
2

VCC33

GND

GPIO_B29

GPIO_B12

D7
BAT54S

VCC33

D32
BAT54S

GND

D24
BAT54S

GPIO_B3

VCC33

GND

GPIO_B20

D23
BAT54S

VCC33

D15
BAT54S

VCC33

2
GPIO_B28

GND

GPIO_B11

D14
BAT54S

GND

D31
BAT54S

GPIO_B27

VCC33

D6
BAT54S

VCC33

GND

GPIO_B19

GPIO_B2

GND

D30
BAT54S

VCC33

GND

VCC33

D22
BAT54S

GND

GPIO_B18

GND

GPIO_B10

VCC33

D21
BAT54S

VCC33

D13
BAT54S

D5
BAT54S

GPIO_B1

GPIO_B9

GND

GND

D12
BAT54S

GND

D4
BAT54S

VCC33

GND

GPIO_B0

D3
BAT54S

VCC33

GPIO_B[0..35]

JP1
GPIO_B0
GPIO_B1
GPIO_B2
GPIO_B3

1
3
5
7

2
4
6
8

IO_A0
IO_A1
IO_A2
IO_A3

GPIO_B4
GPIO_B5
GPIO_B6
GPIO_B7

1
3
5
7

RN28 47

2
4
6
8

IO_A4
IO_A5
IO_A6
IO_A7

GPIO_B8
GPIO_B9
GPIO_B10
GPIO_B11

1
3
5
7

RN29 47

2
4
6
8

IO_A8
IO_A9
IO_A10
IO_A11

2
4
6
8

IO_A20
IO_A21
IO_A22
IO_A23

2
4
6
8

IO_A32
IO_A33
IO_A34
IO_A35

RN30 47

IO_A0
IO_A2
IO_A4
IO_A6
IO_A8
VCC5

GPIO_B12
GPIO_B13
GPIO_B14
GPIO_B15

1
3
5
7

2
4
6
8

IO_A12
IO_A13
IO_A14
IO_A15

GPIO_B16
GPIO_B17
GPIO_B18
GPIO_B19

1
3
5
7

RN31 47

2
4
6
8

IO_A16
IO_A17
IO_A18
IO_A19

GPIO_B20
GPIO_B21
GPIO_B22
GPIO_B23

1
3
5
7

RN32 47

RN33 47
VCC33

GPIO_B24
GPIO_B25
GPIO_B26
GPIO_B27

1
3
5
7

2
4
6
8

IO_A24
IO_A25
IO_A26
IO_A27

GPIO_B28
GPIO_B29
GPIO_B30
GPIO_B31

RN34 47

1
3
5
7

2
4
6
8

IO_A28
IO_A29
IO_A30
IO_A31

GPIO_B32
GPIO_B33
GPIO_B34
GPIO_B35

1
3
5
7

RN35 47

IO_A10
IO_A12
IO_A14
IO_A16
IO_A18
IO_A20
IO_A22
IO_A24
IO_A26
IO_A28
IO_A30
IO_A32
IO_A34

RN36 47

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

IO_A1
IO_A3
IO_A5
IO_A7
IO_A9
GND
IO_A11
IO_A13
IO_A15
IO_A17
IO_A19
IO_A21
IO_A23
IO_A25
GND
IO_A27
IO_A29
IO_A31
IO_A33
IO_A35

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

GND
B

GPIO_A
HEADERBG20X2H

Title
ALTERA DE2
Size
B
Date:
5

Document Number
CONNECT A
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

16

of

24

VCC33

GND

VCC33

VCC33

GND

VCC33

GND

VCC33

GND

VCC33

GND

GND

2
VCC33

GND

2
VCC33
C

GPIO_B71

D74
BAT54S

GPIO_B70

GPIO_B62

D65
BAT54S

GPIO_B53

VCC33

GND

VCC33

GPIO_B61

VCC33

D73
BAT54S

D56
BAT54S

VCC33

GND

GND

GPIO_B69

GPIO_B52

GPIO_B44

1
3
3

VCC33

D47
BAT54S

GND

VCC33

D64
BAT54S

GPIO_B60

D72
BAT54S

GND

GND

GPIO_B68

VCC33

D55
BAT54S

VCC33

GPIO_B43

VCC33

1
D63
BAT54S

GND

GPIO_B51

GND

GPIO_B59

D46
BAT54S

VCC33

D54
BAT54S

1
D71
BAT54S

GPIO_B67

GND

GPIO_B50

GPIO_B42

1
3

2
2

D62
BAT54S

D45
BAT54S

VCC33

GND

D70
BAT54S

VCC33

GPIO_B66

GND

GPIO_B58

GND

D53
BAT54S

GPIO_B41

VCC33

1
3

VCC33

D61
BAT54S

GPIO_B57

D44
BAT54S

GND

GPIO_B49

VCC33

GND

D69
BAT54S

D52
BAT54S

VCC33

GND

GPIO_B65

GND

GPIO_B48

GPIO_B40

1
1
1

VCC33

D43
BAT54S

VCC33

D60
BAT54S

GPIO_B39

VCC33

GND

GPIO_B56

1
GND

D51
BAT54S

GPIO_B47

VCC33

GND
D68
BAT54S

GND

VCC33

GND
D59
BAT54S

D42
BAT54S

GPIO_B38

2
2
GPIO_B64

GND
D50
BAT54S

D67
BAT54S

VCC33

GPIO_B63

GPIO_B55

D41
BAT54S

1
GND

D66
BAT54S

VCC33

GND

D58
BAT54S

GPIO_B46

VCC33

GPIO_B54

GPIO_B37

VCC33

GND

D57
BAT54S

D49
BAT54S

VCC33

GND

GND

GPIO_B45

D48
BAT54S

GND

VCC33

GND

D40
BAT54S

GPIO_B36

D39
BAT54S

VCC33

GPIO_B[36..71]

GPIO_B36
GPIO_B37
GPIO_B38
GPIO_B39

1
3
5
7

2
4
6
8

IO_B0
IO_B1
IO_B2
IO_B3

GPIO_B40
GPIO_B41
GPIO_B42
GPIO_B43

1
3
5
7

RN37 47

2
4
6
8

IO_B4
IO_B5
IO_B6
IO_B7

GPIO_B44
GPIO_B45
GPIO_B46
GPIO_B47

1
3
5
7

RN38 47

2
4
6
8

IO_B8
IO_B9
IO_B10
IO_B11

2
4
6
8

IO_B20
IO_B21
IO_B22
IO_B23

2
4
6
8

IO_B32
IO_B33
IO_B34
IO_B35

JP2
IO_B0
IO_B2
IO_B4
IO_B6
IO_B8

RN39 47

VCC5
GPIO_B48
GPIO_B49
GPIO_B50
GPIO_B51

1
3
5
7

2
4
6
8

IO_B12
IO_B13
IO_B14
IO_B15

GPIO_B52
GPIO_B53
GPIO_B54
GPIO_B55

1
3
5
7

RN40 47
GPIO_B60
GPIO_B61
GPIO_B62
GPIO_B63

1
3
5
7

2
4
6
8

IO_B16
IO_B17
IO_B18
IO_B19

GPIO_B56
GPIO_B57
GPIO_B58
GPIO_B59

1
3
5
7

RN41 47

2
4
6
8

IO_B24
IO_B25
IO_B26
IO_B27

GPIO_B64
GPIO_B65
GPIO_B66
GPIO_B67

1
3
5
7

RN43 47

RN42 47

2
4
6
8
RN44 47

IO_B28
IO_B29
IO_B30
IO_B31

GPIO_B68
GPIO_B69
GPIO_B70
GPIO_B71

1
3
5
7

VCC33

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

IO_B10
IO_B12
IO_B14
IO_B16
IO_B18
IO_B20
IO_B22
IO_B24
IO_B26
IO_B28
IO_B30
IO_B32
IO_B34

RN45 47

IO_B1
IO_B3
IO_B5
IO_B7
IO_B9
GND
IO_B11
IO_B13
IO_B15
IO_B17
IO_B19
IO_B21
IO_B23
IO_B25
GND
IO_B27
IO_B29
IO_B31
IO_B33
IO_B35

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

GND

GPIO_B
HEADERBG20X2H

Title
ALTERA DE2
Size
B
Date:
5

Document Number
CONNECT B
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

17

of

24

U17
U18
R_VCC33
DRAM_D0
R_VCC33
DRAM_D1
DRAM_D2
GND
DRAM_D3
DRAM_D4
R_VCC33
DRAM_D5
DRAM_D6
GND
DRAM_D7
R_VCC33
DRAM_LDQM
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_CS
DRAM_BA0
DRAM_BA1
DRAM_A10
DRAM_A0
DRAM_A1
DRAM_A2
DRAM_A3
R_VCC33

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

VSS
D15
VSSq
D14
D13
VDDq
D12
D11
VSSq
D10
D9
VDDq
D8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS

VDD
D0
VDDq
D1
D2
VSSq
D3
D4
VDDq
D5
D6
VSSq
D7
VDD
LDQM
nWE
nCAS
nRAS
nCS
BA0
BA1
A10
A0
A1
A2
A3
VDD

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

GND
DRAM_D15
GND
DRAM_D14
DRAM_D13
R_VCC33
DRAM_D12
DRAM_D11
GND
DRAM_D10
DRAM_D9
R_VCC33
DRAM_D8
GND

SRAM_A0
SRAM_A1
SRAM_A2
SRAM_A3
SRAM_A4
SRAM_CE
SRAM_D0
SRAM_D1
SRAM_D2
SRAM_D3
R_VCC33
GND
SRAM_D4
SRAM_D5
SRAM_D6
SRAM_D7
SRAM_WE
SRAM_A5
SRAM_A6
SRAM_A7
SRAM_A8
SRAM_A9

DRAM_UDQM
DRAM_CLK
DRAM_CKE
DRAM_A11
DRAM_A9
DRAM_A8
DRAM_A7
DRAM_A6
DRAM_A5
DRAM_A4
GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

A0
A1
A2
A3
A4
nCE
D0
D1
D2
D3
VCC0
GND0
D4
D5
D6
D7
nWE
A5
A6
A7
A8
A9

SRAM_A17
SRAM_A16
SRAM_A15
SRAM_OE
SRAM_UB
SRAM_LB
SRAM_D15
SRAM_D14
SRAM_D13
SRAM_D12
GND
R_VCC33
SRAM_D11
SRAM_D10
SRAM_D9
SRAM_D8

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A17
A16
A15
nOE
nUB
nLB
D15
D14
D13
D12
GND1
VCC1
D11
D10
D9
D8
NC
A14
A13
A12
A11
A10

SRAM_A14
SRAM_A13
SRAM_A12
SRAM_A11
SRAM_A10

IS61LV25616
DIP44-TSOP
SRAM_CE

R_VCC33
R41 4.7K

DRAM_CS

SDRAM 1Mx16x4
DIP54-TSOP

R42 4.7K
R_VCC33
DRAM_D[0..15]
DRAM_A[0..11]
DRAM_UDQM
DRAM_LDQM
DRAM_CLK
DRAM_CKE
DRAM_BA0
DRAM_BA1
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_CS

R_VCC33

BC63
0.1U
GND

BC64
0.1U
GND

BC65
0.1U
GND

BC66
0.1U
GND

BC67
0.1U
GND

BC68
0.1U
GND

BC69
0.1U
GND

BC70
0.1U
GND

SRAM_D[0..15]
SRAM_A[0..17]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_UB
SRAM_LB

Title
ALTERA DE2
Size
A
Date:
5

Document Number
SDRAM AND SRAM
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

18

of
1

24

F_VCC33
U19

R93 4.7K
SD_DAT3
SD_CMD
SD_CLK
SD_DAT

9
1
2
3
4
5
6
7
8

GND
F_VCC33
GND

F_VCC33
R94 4.7K

10
11

DAT2
DAT3
CMD
VSS
VCC
CLK
VSS
DAT0
DAT1 VSS
VSS
SW0 VSS
SW1 VSS

F_VCC33

F_VCC33

12
13
14
15

BC71
0.1U
GND

BC72
0.1U
GND

BC73
0.1U
GND

SD CON-SDC1
GND

FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A20
FLASH_A21
FLASH_WE
FLASH_RESET

FLASH_A19
FLASH_A18
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2

U20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RST
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1

S29AL032DTFN

A16
BYTE
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
GND
CE
A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

FLASH_A17
GND
GND

FLASH_A0
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
F_VCC33
FLASH_D3
FLASH_D2

FLASH_D1
FLASH_D0
FLASH_OE
GND

FLASH_CE
FLASH_A1

F_VCC33
R43 4.7K

TSOP-48

FLASH_D[0..7]
FLASH_A[0..21]
FLASH_CE
FLASH_OE
A

Title
ALTERA DE2
Size
A
Date:
5

Document Number
FLASH
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

19

of
1

24

V+5V
VCC5

SW18
1

5
6

J8

1
2
3

D76 SS14
D-SS14
1
2

D77 SS14
D-SS14
1

D78 SS14
D-SS14
1

DC_9V

U21
2

TC4
10U/35V
C-2012+

TC3
10U/35V
C-2012+
GND
GND

GND

BC45
0.1U

GND

TC7
220U/10V
C-2012+

D80
SS14
D-SS14
1
GND

GND

VCC33

F_VCC33

VCC33

GND

R_VCC33

VCC33

V_VCC33

120
R45 0

GND

GND

TC5
220U/10V
C-2012+

GND

TC8
100U/6.3V
C-1210+

BC77
0.1U

VCC33

BC46
0.1U

VCC33

R44

D79
SS14
D-SS14

GND

47UH

L2

SW

NC

GND

C10 0.01U

GND

GND FB

7
SINK EN
8

BC76
0.1U

LM2676-3.3
BS

GND

USB5V

GND

VIN

TC6
220U/10V
C-2012+

BC75
0.1U

GND

V+3V3
VCC33

GND

4.7K

U22

VOUT

BC74
0.1U

O_VCC5

R98

VIN

POWER SW

D81 SS14
D-SS14

VCC5

LM7805-0.8A

GND

R46 0

GND
POWER
LEDB

R47 0

TC9
100U/6.3V
C-1210+

BC78
0.1U

TC10
100U/6.3V
C-1210+

BC79
0.1U

TC11
100U/6.3V
C-1210+

BC80
0.1U

V+1V8
VCC18
GND
U23

VCC18
LM1117-1.8-0.8A

VIN

TC12
100U/6.3V
C-1210+

BC81
0.1U

VCC33

VCC18

VOUT
GND

TC13
100U/6.3V
C-1210+

BC82
0.1U

GND

A_VCC33

VCC33

R48 0

GND

GND

GND

GND

VCC12

GND

VOUT

BC86
0.1U

VCC5

TC17
100U/6.3V
C-1210+

TC18
100U/6.3V
C-1210+

GND

GND

U_VCC33

R50 0
TC15
100U/6.3V
C-1210+

BC84
0.1U

GND

BC87
0.1U

R54
330

BC88
0.1U

GND

GND

U_VCC5

VCC5

R51 0

TC16
100U/6.3V
C-1210+

BC85
0.1U

GND

GND

VGA_VCC5

GND
VCC18

R52 0

GND
B

V_VCC18

R53 0

TC20
220U/10V
C-2012+

BC89
0.1U
GND

VCC33

VCC12

VIN

GND

V+1V2
VCC12

LM1117-1.2-0.8A
3

GND

R49 0

GND
U24
B

GND

N_VCC33

TC14
100U/6.3V
C-1210+

BC83
0.1U
GND

GND

GND

VCC33

TC21
220U/10V
C-2012+

BC90
0.1U

TC22
100U/6.3V
C-1210+

BC91
0.1U

GND

GND
GND

GND

H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
HEATO HEATO HEATO HEATO HEATO HEATO HEATO HEATO HEATO HEATO

GND
VCCINT

GND

GND

VCC12
VCCIO

R91

GND1
GND

R92

GND3
GND

GND4
GND

H27
GND

H28
GND

H19
GND

H20
GND

H21
GND

H22
GND

TC19
100U/6.3V
C-1210+
H23
HOLE

H24
HOLE

H25
HOLE

H29
HOLE

H30
HOLE

H31
HOLE

H32
HOLE

GND

1
GND

TC28
100U/6.3V
C-1210+

TC27
100U/6.3V
C-1210+

H26
HOLE

GND
GND

GND2
GND

VCC33

VCC33

GND

GND

GND

Title
ALTERA DE2
Size
Document Number
CustomPOWER
Date:

Wednesday, November 16, 2005

Rev
1.1
Sheet
1

20

of

24

R56

1.5K

USB_DP

R57

22

USBDP

USB_DM

R58

22

USBDM

VCC
EARTH

GND

D82
BAT54S

D83
BAT54S

USB_B_CONN
JACK-USB-B

GND

GND

GND

USB5V

GND

USB5V

6MHZ

PWRON
USBON

XTOUT

/RESET

ISPTMS

2
1
32

EEDATA
EECLK
EECS

FP3V

22

29

C9
47P
GND
USB5V

16
15
14
12

28

AGND

R26
C

/RD
WR
/TXE
/RXF

ULED
6MHZ
FP3V
ISPTDI
UD0
UD1
UD2
UD3
UD4
UD5
GND
UD6
UD7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

100K

R59

25
24
23
22
21
20
19
18

XTIN

nRESET

USB5V

D0
D1
D2
D3
D4
D5
D6
D7

27
3

-D

+D

3
26

/RSTOUT

J9
6

13

3V3OUT

GND

SI/WU
PWREN

FT245BM
QFP32-0.8-2

USB3V

11
10

IOA7
IOA6
IOA5
IOA4
IOA3
GNDIO
IOA2
IOA1
IOA0
VCCINT
OE2
GCLRn
OE1
GCLK1
GNDINT
IOH8
IOH7
IOH6
VCCIO
IOH5
IOH4
IOH3
GNDIO
IOH2
IOH1

GND

URD
UWR
TXE
RXF

ULED
R61

IOH0
GNDIO
TDO
IOG7
IOG6
IOG5
IOG4
IOG3
IOG2
VCCIO
GNDIO
IOG1
IOG0
TCK
IOF7
IOF6
GNDIO
IOF5
IOF4
IOF3
IOF2
IOF1
GNDIO
IOF0
VCCIO

IOA8
IOA9
VCCIO
TDI
IOB1
IOB2
IOB3
IOB4
IOB5
IOB6
GNDIO
IOB7
IOB8
IOB9
TMS
IOC1
IOC2
VCCIO
IOC3
IOC4
IOC5
IOC6
IOC7
IOC8
IOC9

LOAD
LEDB
FP3V

GND

GNDIO
IOD0
IOD1
IOD2
IOD3
IOD4
IOD5
GNDIO
VCCIO
IOD6
IOD7
IOD8
GNDINT
VCCINT
IOE0
IOE1
IOE2
GNDIO
IOE3
IOE4
IOE5
IOE6
IOE7
IOE8
IOE9

GND

GND

BC93
0.1U
U26

GND

VCC
VCC

GND

AVCC

BC97
0.1U

U25

TEST
GND
GND

BC96
0.1U

VCC-IO

BEAD

BC95
0.1U

30

BC92
0.1U
BC94
0.1U

FP3V

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

USB5V

BEAD

L4

USB5V

31
17
9

L3

330

GND

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

GND
ISPTDO
FPTDI
FPNCSO
FPTCK
FPNST
FP3V
TDO
TCK
ISPTCK
TMS
TDI

GND
2 LINK_D0
4 LINK_D1
6 LINK_D2
8 LINK_D3

1
3
5
7

RN53 120
R0603-4R-N
FP3V
GND

GND
TRGDCLK
TRGASDO
TRGNCS
TRGNST
GND

FP3V

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

R55

FP3V

24MHZ

GND

12MHZ

EPM3128AT
LQFP100-0.5

120

U28
GND
2

TC23
100U/6.3V
C-1210+

BC98
0.1U

BC99
0.1U

BC101
0.1U

BC102
0.1U
R62 1.5K

GND

GND

GND

GND

8
6
4
2

7
5
3
1

GND

CONF_DONE
NSTATUS
TCK
NCE

EEPCS 1
EEPCLK 2
EEPDI 3
EEPDO 4

1
3
5
7

CS VCC
CLK NC
DI ORG
DO GND

USB3V
GND

RN47 10K

GND

EEPDI

1
3
5
7

ISPTCK
ISPTDO
ISPTMS
EEPDO
ISPTDI

1
3
5
7
9

10K

GND

VCC33

Q6 8550
3

VCC5

1
3
5
7

GND

R63

1.5K

SW19
RUN/PROG

10K

GND
FP3V

TRGNCS
TRGNST

RN50

ASDO
DCLK
NCSO
DATA0

2
4
6
8

1
3
5
7

TRGASDO
TRGDCLK
TRGNCS
TRGNST

Y2
4

120

24MHZ

12MHZ
LINK_D0
LINK_D1
LINK_D2
LINK_D3

VCC
OUT

1
2
3
4
5
6
7
8

BC103
EN

GND

R100

R101

R102

1K

10K

1K

10K

R104

4.7K

VCC5

VCC
DCLK
VCC
ASDI
NC
NC
NC
NC
NC
NC
NC
NC
NCS
GND
DATA0 VCC

16
15
14
13
12
11
10
9

USBON
4.7K

BC44

TRGDCLK
TRGASDO

2
0.1U

Q8
8050

3
2

R105

R106

1K

1K

Q9
8050

GND
GND
VCC33
GND

GND

GND

GND

FP3V

EPCS16
DIP16-SOP1

0.1U
BC100

BC122

BC123

BC124

BC125

BC126

0.1U

0.1U

0.1U

0.1U

0.1U

0.1U

24MHZ
GND

Title
ALTERA DE2

GND

GND

GND

GND

GND

GND

Size
B
Date:

FP3V

R99

PWRON

U30
VCC33
VCC33

Q7 8550
3

USB5V

GND
R103

NCE
VCC33
TRGOE
GND
GND

1
2
3
4
5

USB3V

USB3V

EEPCLK
EEPCS

VCC33
RN49
2
4
6
8

FP3V

GND

2
4
6
8
10

CPLD ISP

NCONFIG
TDI
TMS
TDO

GND

FP3V
TRGOE

JP3

2
4
6
8

GND

BC104
0.1U
GND

RN48
GND

GND

FP3V

8
7
6
5

93LC46B
DIP8-SOP

120

VCC33

2
4
6
8

GND

USB5V

U29

RN46

VOUT
GND

VIN

LM1117-3.3-0.8A
3

Document Number
USB BLASTER
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

21

of

24

U_VCC33

U_VCC5

BC105
0.1U

OTG_LSPEED
OTG_FSPEED
OTG_D[0..15]

BC106
0.1U

BC107
0.1U

BC108
0.1U

BC109
0.1U

BC110
0.1U

BC111
0.1U
GND

GND

GND

DREQ2
nDACK2
DREQ1
nDACK1

ID
nOTGMODE
VBUS
CP_CAP2
CP_CAP1

48
45
55
54
53

nGL

39

TEST2
TEST1
TEST0

60
59
23

CLKOUT

38

X1
X2

43
44

BC112
0.1U
GND
R66

1
3

C21
47P

GND

VAUX
DM
DP
GND
C

C22
47P

GND

GND

5
6

SHIELD1
SHIELD2

22
GND
CON_USB_A

R60

4.7K
R68

4.7K

U_VCC33
U_VCC33

R67

22

R69

22

R70

22

C23
0.1U

R108

15K

15K

GND

330
GND

R72

GOOD
D-0805

GND

O_VCC5

GND

O_VCC5

D87
BAT54S

LEDB
R31

10K

R73

10K

1.5K
L6

R32

BEAD

1.5K

BC113
0.1U

100K
GND

C25
47P
GND

C26
47P
GND

J10
+D

-D

2
1

U_VCC33
R74

D88
BAT54S
3

OTG_LSPEED
OTG_FSPEED

GND

GND

O_VCC5

U_VCC33
R71

ISP1362
LQFP64-0.5

R107

25
29
24
28

nH_OC1
nH_PSW1
OTG_DM1
OTG_DP1

42
35
49
50

1
2
3
4

TC24
220U/10V
C-2012+

OTG_DREQ1
OTG_DACK1
OTG_DREQ0
OTG_DACK0

41
36
46
47

J11

nCS
nWR
nRD
INT2
INT1
nRESET

56

D86
BAT54S
SOT-323

BEAD

GND

21
22
20
31
30
32

VDD_5V
nH_OC2
nH_PSW2
H_DM2
H_DP2

L5

D85
BAT54S
SOT-323

OTG_CS
OTG_WE
OTG_OE
OTG_INT1
OTG_INT0
OTG_RESET

H_VCC5

33
34

AGND

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

H_SUSWKUP
D_SUSWKUP

51

18
17
16
15
13
12
11
10
8
7
6
5
3
2
64
63

U_VCC5

A1
A0

DGND5
DGND4
DGND3
DGND2
DGND1
DGND0

62
61

OTG_D15
OTG_D14
OTG_D13
OTG_D12
OTG_D11
OTG_D10
OTG_D9
OTG_D8
OTG_D7
OTG_D6
OTG_D5
OTG_D4
OTG_D3
OTG_D2
OTG_D1
OTG_D0

57
37
27
19
9
1

H_VCC5

58
52
40
26
14
4
VCC5
VCC4
VCC3
VCC2
VCC1
VCC0

U31

GND

U_VCC5

OTG_CS

OTG_A1
OTG_A0

H_VCC5

R65
4.7K

U_VCC33

U_VCC33

VCC
GND

EARTH
5

USB_B_CONN
JACK-USB-B
GND

GND

GND
12MHZ
R33

22
C27
47P

GND

Title
ALTERA DE2
Size
B
Date:
5

Document Number
ISP 1362
Wednesday, November 16, 2005

Rev
1.1
Sheet
1

22

of

24

TD_D[0..7]
27MHZ

V_VCC33

TD_RESET

R75

TD_HS
TD_VS

AV_VCC33

V_VCC18

V_VCC33

AV_VCC33

PV_VCC18

TC26
100U/6.3V
C-1210+

BC114
0.1U

42
41

31

40

4
11

CML
REFOUT

GND
27M
C36
10U

XTAL
XTAL1

GND
TD_RESET

51

nRESET

V_VCC33

29

nPWRDWN

GND

52

ALSB

I2C_SCLK
I2C_SDAT

SCLK
SDATA
DGND
DGND
DGND
DGND

54
53

I2C ADDRESS READ IS 0x40


I2C ADDRESS WRITE IS 0x41

3
10
24
57

V_VCC33

AGND
AGND
AGND
AGND
AGND

GND

C37
10U

22
21

ELPF
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

26
25
19
18
17
16
15
14
8
7
6
5
62
61
60
59

FIELD
VS
HS
SFL

63
64
2
9

nINTRQ
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
LLC

1
55
56
13
12
50
33
28
27
20

BC116
0.1U
GND

EN

VCC

GND

OUT

BC115
0.1U

RN51
1
3
5
7

2
4
6
8

TD_D0
TD_D1
TD_D2
TD_D3

GND

C31
10U
GND

R78

47
RN52

GND

1
3
5
7

2
4
6
8

VGND

TD_D4
TD_D5
TD_D6
TD_D7
AV_VCC33

VGND

47
D89
120 TD_VS
120 TD_HS

R79
R80

BAT54S
SOT-323

AV_VCC33
R81
Q10
8050

2
1

1
2

R83

27MHZ

VGND

J12 RCA JACK

120

3
1

CVBS_IN

75

Q11
8550

R82
75
VGND

C39
470P
VGND

VGND

VGND

27M

GND

VGND
Title
ALTERA DE2

27MHZ
Size
A
Date:

1.7K

VGND
ADV7181B
LQFP64-0.5

Y3
A

R77

C40
470P

32
34
37
43
45

GND

C35
0.1U

R76
30

C34
0.1U

PVDD

CAPC2
CAPY2
CAPY1

AVDD

44
39
38

10U

PV_VCC18

C33

V_VCC18

10U

AIN1
AIN2
AIN3
AIN4
AIN5
AIN6

C30
0.1U

C32

0.1U

C29
0.01U

C38

35
36
46
47
48
49

DVDDIO
DVDDIO

CVBS_IN

DVDD
DVDD

U33

23
58

GND

Document Number
ADV7181B
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

23

of
1

24

VGA_R[0..9]
VGA_G[0..9]
VGA_B[0..9]
VGA_BLANK
VGA_SYNC
VGA_CLOCK

VGA_VCC5

VGA_HS
VGA_VS

VGA_R9
VGA_R8
VGA_R7
VGA_R6
VGA_R5
VGA_R4
VGA_R3
VGA_R2
VGA_R1
VGA_R0

R84
RSET R85

4.7K
560
BC117
0.1U

U34

1
2
3
4
5
6
7
8
9
10
11
12

G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
nBLANK
nSYNC

BC119
0.1U

J13
R95
R96
R97

VGA_R
VGA_G
VGA_B

R86
75
GND

R87
75

GND

0
0
0

R88
75

GND
VGA_HS
VGA_VS

R89
R90

47
47

13
14
15
16
17
18
19
20
21
22
23
24

GND

VGA_B0
VGA_B1
VGA_B2
VGA_B3
VGA_B4
VGA_B5
VGA_B6
VGA_B7
VGA_B8
VGA_B9
VGA_CLOCK

VGA_VCC5

36
35
34
33
32
31
30
29
28
27
26
25

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

R
G
B
NC0
GND0
RG
BG
GG
NC1
GND1
NC2
NC3
HS
VS
NC4
SHIELD0
SHIELD1

ADV7123
LQFP48-0.5

VREF
COMP
IOR
nIOR
IOG
nIOG
VAA2
VAA1
IOB
nIOB
GND1
GND0

11

VAA0
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
CLOCK

VGA_G0
VGA_G1
VGA_G2
VGA_G3
VGA_G4
VGA_G5
VGA_G6
VGA_G7
VGA_G8
VGA_G9
VGA_BLANK
VGA_SYNC

R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
nPSAVE
RSET

BC118
0.1U

48
47
46
45
44
43
42
41
40
39
38
37

GND

VGA_VCC5
GND
BC120
0.1U
GND

VGA

DB15-RA-F2

BC121
0.1U
GND

Title
ALTERA DE2
Size
A
Date:
5

Document Number
ADV7123
Wednesday, November 16, 2005
2

Rev
1.1
Sheet

24

of
1

24

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