Professional Documents
Culture Documents
Lect09-CN303 (Compatibility Mode)
Lect09-CN303 (Compatibility Mode)
Lecture#9:Interrupts
Introduction
A computer must execute one of the collection of special routines whenever certain conditions exits within a program or the microcomputer system. For instance the microcomputer system should give response to devices such as a keyboard, mouse and other components when they request for a service.
Introduction
The most common method is polling, where the CPU tests each device in sequence and in effect ask each one if it needs communication with a PROCESSOR. But polling requires that large portion of the I/O program to continuous monitor the peripheral devices in a loop. Polling affects system throughput ,thus affecting number of tasks and cost effectives of a microcomputer system.
Introduction
A more desirable method is the one that allows the CPU to execute I/O programs and stop peripheral devices when its told by the peripheral devices. In effect this method provides external asynchronous input that inform the CPU to complete the current instruction and fetch a new routine that serves a requesting device. Once this routine completes the CPU resumes where it left off.
Introduction
This method that causes the CPU to finish the current instruction and fetch the new routine that serves the requesting device is called INTERRUPT METHOD. It is easy to see how throughput increases to enhance cost effectiveness of microcomputer systems through this method.
Introduction
Microcomputer systems allow execution of special routines called INTERRUPT SERVICE ROUTINES when they receives an interrupt. Remember an interrupt cause a processor to stop executing a normal program and call a special routine that services an interrupt.
Hardware interrupts These are caused by external signals applied to the NonMaskable Interrupt (NMI) input pin or the interrupt(INTR) input pin.
Software interrupts
These are caused by a special instruction INT n(integer) or by a condition produced in the 8086 by execution of an instruction(Divide by zero etc).
Answer
From the INTERRUPT VECTOR TABLE
In an 8086 system the 1st 1Kbyte of memory from 00000H to 003FFH is reserved for storing the starting addresses of ISRs.
8086 IVT
Only five have explicit definitions such as divide by zero and non-maskable interrupt. The next 5-31 are reserved by Intel for use in future microprocessors. The upper 32-255 are available for hardware and software interrupts.
An 8086 is used in this mode by setting the Trap flag, once the TF is set an 8086 automatically execute Type 1 interrupt after executing each instruction. But TF can be set or clear by manipulating the flag register contents in memory using PUSHF instruction.
Breakpoint Interrupt(Type 3)
Is produced by execution of INT 3 instruction, inserting a breakpoint causes a system to execute instructions up to breakpoint, and then goes to the breakpoint procedure.
Overflow Interrupt(Type 4)
Checks overflow condition after any signed arithmetic operation in the system and then executes the INTO or INT 4 instruction.
Figure 11-8 shows the timing diagram for the INTR and INTA pins of the microprocessor.
Interrupt Priorities
Priority 1 Interrupt Divide error and all software interrupts ( Int n) except those listed bellow Priority Level HIGHEST
2 3 4
LOWEST
Interrupt Priorities
To enforce priorities;
An 8086 clears the interrupt flag automatically as part of responding to an interrupt. This prevents a signal on INTR input from interrupting a higher priority ISR. But an 8086 allows a signal on NMI input to interrupt higher priority interrupt.
Note that : An 8086 checks internal interrupts before it checks external interrupts.(Divide error and NMI example)
Features of 8259
1. It can manage 8 priority interrupts, equivalent to providing 8 interrupt pins on the processor INTR input pin. 2. It is possible to locate vector table for these additional interrupts anywhere in the memory map . However, all 8 interrupts must be spaced at the interval of 4 or 8 locations. 3. By cascading 8259s it is possible to get 64 priority interrupts.
Features of 8259
4. An interrupt mask register makes it possible to mask individual interrupt request. 5. Can be programmed to accept either the level triggered or the edge triggered interrupt request. 6. User can get the information of pending interrupts, in-service interrupts and masked interrupts from 8259A. 7. The 8259A is designed to minimize software and real time overhead in handling multi-level priority interrupts.
RD
The read input connects to the read strobe signal.
INT
The interrupt output connects to the INTR pin on the microprocessor from the master, and is connected to a master IR pin on a slave.
A0
The A0 address input selects different command words within the 8259A.
CAS0-CAS2
The cascade lines are used as outputs from the master to the slaves for cascading multiple 8259As in a system.
Read/Write logic
The RD and WR control the data flow on the bus when the device is selected by asserting its chip select(CS) input low.
Interrupt Sequence
The events occurs as follows;
1. One or more INTERRUT REQUEST lines(IR0-IR7) are raised high, setting the corresponding IRR bit(s). 2. The priority resolver checks the three registers : IRR for interrupt request,IMR for masking bits and ISR for interrupt request being served. It resolves the priority and sets the INT high when appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse.
Interrupt Sequence
4. Upon receiving an INTA from the CPU,the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259 does not drive data bus during this cycle. 5. The 8086 initiates a second INTA pulse, during this pulse the 8259 releases a 8-bit pointer(interrupt type) onto the data bus where it is read by the CPU.
Interrupt Sequence
4. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse.Otherwise,the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. 5. Note that : The priority modes can configured by the programmer dynamically at any time during the main program to define the complete interrupt service structure based on system requirements.
Poll Mode
In this mode the INT output is not used. Instead the microprocessor checks the status of interrupt requests by issuing a poll command. After issuing a poll command the microprocessor reads contents of 8259A and the 8259A provides polled word and sets ISR bit of highest priority active interrupt request.
Polled word
I X X X X W2 W1 W0
I=1One or more interrupt request activated I=0No interrupt request activated W2 W1 W0Binary code of highest priority active interrupt request
IMPORTANT NOTE
The sequence shown on the flow chart must be followed to initialize 8259A. According to the flow chart an ICW1 and an ICW2 must be sent to any 8259A in the system. If a system has any slave 8259s(cascade mode) then an ICW3 must be sent to the master, and difference ICW3 must be sent to the slave.
IMPORTANT NOTE
If the system is an 8086,or if you want to specify certain special conditions , then send ICW4 to the master and to each slave.
8259A Interfacing
Fig 11.4 shows how an 8259A can be interfaced with the 8086 microprocessor system in minimum mode. The 74LS138 address decoder will assert the CS input to the 8259A when an I/O base address is FFF0H or FFF2H on the address bus. The A0 input of the 8259A is used to select one of the two internal addresses in the device.
8259A Interfacing
Since A0 is connected to system line A1,so the system internal addresses are FFF0H and FFF2H. Data lines of an 8259A are connected to the lower half of the system data bus, because the 8086 expects to receive interrupt types on these lower eight data lines. RD and WR signals are connected to the system RD and WR lines.
8259A Interfacing
The interrupt request signal INT from the 8259A is connected to the INTR input of the 8086 and INTA from 8086 is connected to INTA on the 8259A. Since we are using a single 8259A in the system SP/EN pin is tied high and CAS0CAS2 lines are left open. The 8 IR inputs are available for interrupt signals.
8259A Interfacing
Note that; 1. Unused IR inputs should be tied to ground so that a noise pulse cannot accidentally cause an interrupt. 2. In maximum mode RD and INTA signals of 8259A are connected to the IORC,IOWC and INTA lines of 8288 bus controller.