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PSpice Intro v8
PSpice Intro v8
Introduction to PSpice
schematic capture program. Not introduced at CERN. v9 to be introduced at CERN after Windows upgrade. OrCAD will use MicroSim schematics for next two years.
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Probe
Also available at CERN: Parts (modelling program) Stimulus Editor (to produce custom voltage/current/digital sources) Optimizer (can automatically vary circuit component values to satisfy design criteria)
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Set-up PSpice
Run set-up from Windows menu Makes default directories for temp files, backup files and user libraries. Copies required files over to PC
msim.ini (contains all library paths, controls look of the programs) msim.prb (used while running Probe)
Introduction to PSpice
Freq1.sch (1)
Enter the circuit
shown.
Use components:
VDC R C VAC (VSIN) AGND OP-07 Bubble
Freq1.sch (2)
Get new part
toolbar menu - Draw/Get new part keyboard - ctrl-G
Flip/rotate part
menu - Edit/Flip/rotate keyboard - ctrl-F, ctrl-R
Cut/Copy/Paste part
menu - Edit Cut/Copy/Paste keyboard - ctrl-X, ctrl-C,ctrl-V
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Freq1.sch (3)
Wire circuit
Draw/Wire ctrl-W use space bar/RMB
Des(ignators) Label node v_out Change VDC values Label bubble connectors
Introduction to PSpice
*VSIN can also be used for AC analysis - see Appendix 1 for set-up explanation
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From keyboard
F11
or
from the keyboard Ctrl N,I,O,A To re-scale axes double-click on any axis
or
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In Probe:
Trace/Add, DB(V(v_out)) To make cursors active select Place one cursor on nominal 0dB point Move other cursor until dif shows difference of 3dB
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N.B. to see a detailed explanation of this goal function and its parameters, select: Trace/Goal Functions, LPBW, View The g.f. can also be evaluated from this window (select Eval instead of View)
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Adding parameters
Change C1 value to {c_val}
N.B. name is unimportant but { } are mandatory Add a PARAM symbol (Draw/Get New Part/ Param) Set up NAME1 and VALUE1 PARAM values (double-click on the symbol).
Click OK
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(typically) show:
The analysis results are split
into sections. There is one section for each value of parametric sweep
Click on OK
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Select Trace/Add. Plot (LPBW(V(v_out),3)) Select Plot/Add Plot Select Trace/Add. Plot 1/(LPBW(V(v_out),3))
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Transient.sch (1)
Load transient.sch Complete by adding
IPWL*
(IPWL is a Piece Wise Linear current source)
satisfies:
risetime I(L1) < 2s overshoot I(L1) < 10% ?
Hints:
Range is somewhere between 0.4 and 1.5 Ohms (set-up Parametric Analysis in Schematics using Analysis/Setup/Parametric) In Probe, select Trace/Performance Analysis , click OK Use GenRise() and Overshoot() goal functions
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Exercises
Exercise 1 Design a perfect non-inverting voltage op-amp using E (voltage-controlled voltagesource). Verify using VPULSE (appendix 2) and transient analysis Design a perfect non-inverting voltage op-amp using A(nalog) B(ehavioral) M(odelling) parts (found in ABM library) Design an imperfect non-inverting voltage op-amp (output limited to supply voltage). Exercise 2 Design an attenuator with input parameters IMP and ATT. Calculate values for R1,R2 such that: v_out = v_in - ATT dB The impedance seen from RS = IMP Add parameter checking
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Slow.sch
Load and simulate
slow.sch Zoom in on the output Replace the digital pullup with a 1k resistor to +5V and re-simulate Whats the difference?
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characterised digital parts - these are mostly behavioural models only (which includes timing information) To simulate real (analogue) input/output behaviour, find the transistor-level circuits
proprietary information very slow simulation speeds
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times specified here) Each device has an I/O model. This will be shared by all devices in the same logic family
The I/O model includes a nominal impedance representation for each I/O pin. It also includes information on which type of AtoD and DtoA converter to use for each device. These converters are powered off the supplies defined by IPIN(supply).
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Digital Setup
Timing mode leave on Typical Flip-flop initialization depends on circuit Default Interface leave on Level 1
If you have lots of unimportant digital warnings - set Default A/D Interface to Level 2 (see Appendix 6)
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simulator using:
IC on components Setpoints Nodeset Save/Load Bias Point
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Appendices
1) 2) 3) 4) 5) 6) 7)
Setup VSIN Setup VPULSE Setup ISTIM Default digital power supplies Changing CMOS power supplies Default A/D interface definitions Setting Initial Conditions
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Save and exit Stimulus Editor N.B this saves the stimulus test in transient.stl
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stimulii already have a default power supply. The four default power supplies provided in the model library are:
DIGIFPWR (TTL) CD4000_PWR (CD4000 series CMOS) ECL_10K_PWR (ECL10K) ECL_100K_PWR (ECL 100K).
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Exercise 1 Solution
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