Flip-Flop Applications

Registers

Registers
a register is a collection of flip-flops basic function is to hold information a shift register is a register that moves information on the clock signal
serial-in/serial-out serial-in/parallel-out parallel-in/serial-out parallel-in/parallel-out

Serial-in, serial-out unidirectional shift register.

Figure 6.26

Serial-in, parallel-out unidirectional shift register.

Figure 6.27

Parallel-in unidirectional shift register.

Figure 6.28

Universal shift register. (a) Logic diagram. (b) Mode control. (c) Symbol.
Figure 6.29

Flip-Flop Applications
Counters

Counters
Also called pattern generators Function: produce a specified output pattern sequence Types of counters
Binary ripple counters (asynchronous counters) Synchronous counters

State diagram of a counter.

Figure 6.30

Binary Ripple Counters

also called asynchronous binary counters the LSB flip-flop recieves clock input from a clock source the ith flip-flop recieves clock input from output of the ith-1 flip-flop

Four-bit binary ripple counter. (a) Logic diagram. (b) Timing diagram. (c) Counting sequence.
Figure 6.31

Synchronous Binary Counters

Solve the settling time problem of the ripple counters Every flip-flop changes on clock input simultaneously Large number of flip-flops can cause loading complications

Four-bit synchronous binary counter.

Figure 6.32

Four-bit synchronous binary counter variation.

Figure 6.33

Four-bit synchronous binary counter with parallel load inputs. (a) Logic diagram. (b) Symbol.
Figure 6.34

Synchronous mod-10 counter. (a) Connections. (b) Counting sequence.

Figure 6.35

8-bit synchronous binary counter constructed from two 4-bit synchronous binary counters.
Figure 6.36

Counters Based on Shift Registers

Nonbinary counters
a ring counter: a circular shift register where only one flip-flop is in 1-state and the rest are in 0-state a switch-tail counter (twisted-ring counter or Johnson counter): complement of the rightmost flip-flop becomes input of the leftmost flip-flop

Mod-4 ring counter. (a) Logic diagram. (b) Counting sequence.

Figure 6.37

Mod-8 twisted-ring counter. (a) Logic diagram. (b) Counting sequence.

Figure 6.38

Mod-7 twisted-ring counter. (a) Logic diagram. (b) Counting sequence.

Figure 6.39

Synchronous Counter Design

To design a synchronous counter, perform the following steps Decide the counting sequence Draw an excitation table, which consists of 3 parts
Present state| Next state| flip-flop inputs
(flip-flop inputs can be obtained from an application table of the selected flip-flop)

Determine inputs of each flip-flop

General structure of a synchronous mod-6 counter using positive-edge-triggered JK flip-flops.

Figure 6.40

Determination of the minimal-sum expressions for a synchronous mod-6 counter using clocked JK flip-flops.
Figure 6.41

Logic diagram of a synchronous mod-6 counter.

Figure 6.42

Determination of the minimal-sum expressions for a synchronous mod-6 counter using clocked D flip-flops.
Figure 6.43

Determination of the minimal-sum expressions for a synchronous mod-6 counter using clocked T flip-flops.
Figure 6.44

Determination of the minimal-sum expressions for a synchronous mod-6 counter using clocked SR flip-flops.
Figure 6.45

Complete state diagram for the synchronous mod-6 counter of Fig. 6.42.
Figure 6.46