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  • Fifo 2

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    brk_318
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    This document contains Verilog code for testing a FIFO module. It defines tasks to reset, load data into, and read data from the FIFO. It instantiates the FIFO module and connects its ports. It generates a clock signal and loads test data into the FIFO using the load_data task. It then reads data from the FIFO using the read_data task. The code simulates the FIFO's behavior under a test data loading and reading scenario.

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    fifo2

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    This document contains Verilog code for testing a FIFO module. It defines tasks to reset, load data into, and read data from the FIFO. It instantiates the FIFO module and connects its ports. It generates a clock signal and loads test data into the FIFO using the load_data task. It then reads data from the FIFO using the read_data task. The code simulates the FIFO's behavior under a test data loading and reading scenario.

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    Attribution Non-Commercial (BY-NC)
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    4 views2 pages

    Fifo 2

    Uploaded by

    brk_318
    This document contains Verilog code for testing a FIFO module. It defines tasks to reset, load data into, and read data from the FIFO. It instantiates the FIFO module and connects its ports. It generates a clock signal and loads test data into the FIFO using the load_data task. It then reads data from the FIFO using the read_data task. The code simulates the FIFO's behavior under a test data loading and reading scenario.

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    Attribution Non-Commercial (BY-NC)
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    of 2

    File: /media/BRK/fo2.

    v
    include "fifo.v" module fifo_tb; reg clk, rst_n, rd_n, wr_n; wire over_flow; wire under_flow; wire [`DATA_WIDTH-1:0] data_out; reg [`DATA_WIDTH-1:0] data_in; task reset; begin rd_n = 1; wr_n = 1; rst_n = 1; #2 rst_n = 0; #10 rst_n = 1; end endtask // Tarea para guardar un dato en la fifo. task load_data ( input [`DATA_WIDTH-1:0] data ); begin data_in = data; #10 wr_n = 0; #10 wr_n = 1; end endtask // Tarea para leer un dato en la fifo. task read_data; begin #10 rd_n = 0; #10 rd_n = 1; end endtask fifo dut (.clk(clk), .rst_n(rst_n), .rd_n(rd_n), .wr_n(wr_n), .data_out(data_out), .data_in(data_in), .over_flow(over_flow), .under_flow(under_flow) ); // Creo el clock always begin clk = 0; forever #10 clk = ~clk; end // Guardo las variables initial begin $dumpfile("fifo_tb.vcd"); $dumpvars(10); end initial begin reset(); load_data(1); load_data(2); load_data(3); load_data(4); load_data(5); load_data(22); load_data(21); load_data(20); load_data(19); load_data(18); load_data(17); load_data(16); load_data(15); load_data(14); load_data(13); load_data(12); load_data(61);

    Page 1 of 2

    File: /media/BRK/fo2.v
    load_data(26); load_data(36); read_data(); read_data(); read_data(); read_data(); read_data(); read_data(); read_data(); read_data(); read_data(); $finish; end endmodule

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