7).

setup time and hold time, meta-stability;(how will be the output) Setup - the minimum time before which data must be stable before clock transition Hold time - the minimum time after which data must be stable after clock transition Set up and hold is related to input signal and clock edge, not output. If you input meets these requirement then you will get a valid output.(after clock to Q delay of flop from clock edge).

9).implement all the gates using 2:1 mux;

1. Designing an Inverter using 2:1 MUX. To design an inverter using 2:1 mux, we have to use the input as the select line of the MUX and the zeroth select line would be tied with Logic 1 and First select line would be tired with Logic 0, Now when the select line (Input) goes to 1 the out put will be 0 ( inverted). Image : MUX to inverter -

2:1 mux as an inverter 2. Designing an AND Gate using 2:1 MUX. To design an AND using 2:1 mux, we need to tie the zeroth input to Logic 0 and the First input to the o ne of the input of the AND Gate. The other input of AND gate would be connected with the select line of the MUX. Now, the out put of the MUX would be 1 only if the both of the inputs are 1 otherwise it would be 0 for all conditions. Image : MUX to AND Gate -

2:1 MUX as an AND gate 3. Designing an OR Gate using 2:1 MUX. To design an OR using 2:1 mux, we need to tie the First input to Logic 1 and the Zeroth input to the one of the input of the OR Gate. The other input of OR gate would be connected with the select line of the MUX.

Now, the output of the MUX would be 1 when any oth the two inputs would be 1 otherwise it would be 0 for all conditions. Image : MUX to OR Gate -

2:1 MUX as an OR Gate 4. Designing an NOR Gate using 2:1 MUX. To design the NOR using 2:1 mux, we need to tie the Zeroth input of mux to one of the input of NOR and another input of MUX is tied to 0 . The another input of NOR gate would be applied to the select line of the MUX. Now, the output of the MUX would be AB = (A+B). which is as same as the output of NOR Gate. Image : MUX to NOR Gate -

2:1 mux as a NOR Gate