1.

TO VERIFY THE TRUTH TABLE OF BASIC LOGIC GATES

Three basic logic gates
 AND gate
 OR gate
 NOT gate

AND: -

Definition: -

The AND gate is a basic digital logic gate that implements logical conjunction (∧)

from mathematical logic – AND gate behaves according to the truth table. A HIGH output (1)
results only if all the inputs to the AND gate are HIGH (1). If not all inputs to the AND gate
are HIGH, LOW output results.

Truth table: -

Block diagram: -

Conclusion: - The output of an AND gate is true only when all of the inputs are true. If
one or more of an AND gate's inputs are false, then the output of the AND gate is false. The
truth table for an AND gate with two inputs appears to the right.
OR: -

Definition: -

An OR gate is a logical gate that produces inclusive disjunction. The function of an

OR gate is to find the maximum between the inputs which are binary in nature. It is
one of the basic gates used in Boolean algebra and electronic circuits like transistor-
transistor logic, and complementary metal-oxide semiconductors make use of it.

Truth table: -

Block diagram: -

Conclusion: - An XOR gate implements an exclusive OR, i.e., a true output result occurs if
one – and only one – of the gate’s inputs is true. If both inputs are false (i.e. LOW or 0) or
both inputs are true, the output is false.
NOT: -

Definition: -

A NOT gate is a logic gate that inverts the digital input signal. For this reason, a NOT gate is
sometimes is referred to as an inverter (not to be confused with a power inverter). A NOT
gate always has high (logical 1) output when its input is low (logical 0). Conversely, a logical
NOT gate always has low (logical 0) output when the input is high (logical 1).

Truth table: -

Block diagram: -

Conclusion: - The NOT gate has a logic of inverter, and an inverted logic of input appears at
the output. A logic NOT gate results in a logic “LOW” when input logic is “HIGH” and in a
logic “HIGH” when input logic is “LOW”.
2.TO VERIFY THE TRUTH TABLE OF COMBINATIONAL LOGIC
GATES

Two combinational logic gates

 EX-OR
 EX-NOR

EX-OR: -

Definition: -

 The EX-OR gate returns high output with one of two high inputs.
 For example, if both the inputs are binary 0 or 1, it will return the output as 0.
Similarly, if one input is binary 1 and another is binary 0, the output will be 1.
 The operation for the EX-OR gate is denoted by encircled plus symbol.
 The EX-OR operation is widely used in digital circuits.

Truth table: -

Block diagram: -

Conclusion: -An XOR gate may serve as a "programmable inverter" in which one input
determines whether to invert the other input, or to simply pass it along with no change.
 EX-NOR: -

Definition: -

 The EX-NOR gate is a circuit that returns low output with one of two high inputs.
 For example, if both the inputs are binary 0 or 1, it will return the output as 1.
Similarly, if one input is binary 1 and another is binary 0, the output will be 0.
 The symbol for the EX-NOR gate is denoted by encircled plus symbol which
inverts the binary values.

Truth table: -

Block diagram: -

Conclusion: -XNOR gate is a combination of an exclusive-OR gate and a NOT gate but

has the same truth table as a standard NOR gate, usually when the logic level is “1” and the
output is “low. Any inputs are at logic level “1”.” to logic level “0”.
3.TO VERIFY THE TRUTH TABLE OF UNIVERSAL LOGIC GATES

TWO UNIVERSAL LOGIC GATES

 NAND
 NOR

NAND: -

DEFINITION: -

 The term NAND is a contraction of the expression NOT-AND gate.

 A NAND gate is an AND gate followed by an inverter.

Truth table: -

Block diagram: -
 Conclusion: - NAND is a logic gate; it stands for Not-And. A NAND gate is the logical
inverse of an AND gate. An AND gate only returns true if all inputs are true.

NOR: -

Definition: -

 The term NOR is a contradiction of the expression NOT-OR.

 A NOR gate, is an OR gate followed by an inverter.

Truth table: -

Block diagram: -

Conclusion: - NOR is a universal gate whose resultant operation is a combination of OR

operation followed by NOT operation. We can realise it using NOT and OR gates or
construct it using transistors. The output of the NOR gate is high only when all the inputs are
low.
4.TO VERIFY THE TRUTH TABLE OF HALF ADDER
COMBINATIONAL CIRCUIT

Definition: -: Half adder is a combinational circuit that is used to add two binary numbers
of one-bit each. It does not hold the ability to consider the carry-in generated from previous
summations. The addend, when added with the augend, provides sum and carry (if present).

Truth table: -

Block diagram: -

Conclusion: - Half Adder Circuit and its Construction. Computer uses binary numbers 0
and 1. An adder circuit uses these binary numbers and calculates the addition. A
binary adder circuit can be made using EX-OR and AND gates.
5.TO VERIFY THE TRUTH TABLE OF FULL ADDER
COMBINATIONAL CIRCUIT

Definition: -

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as
C-OUT and the normal output is designated as S which is SUM. A full adder logic is
designed in such a manner that can take eight inputs together to create a byte-wide adder
and cascade the carry bit from one adder to another. we use a full adder because when a
carry-in bit is available, another 1-bit adder must be used since a 1-bit half-adder does not
take a carry-in bit. A 1-bit full adder adds three operands and generates 2-bit results.

Truth table:

Block diagram: -
Conclusion: -Full Adder is the circuit that consists of two EX-OR gates, two AND gates,
and one OR gate. Full Adder is the adder that adds three inputs and produces two outputs
which consist of two EX-OR gates, two AND gates, and one OR gate.

6.TO VERIFY THE TRUTH TABLE OF HALF SUBTRACTOR

COMBINATIONAL CIRCUIT

Definition: -
 Half Subtractor is a combinational logic circuit.
 It is used for the purpose of subtracting two single bit numbers.
 It contains 2 inputs and 2 outputs (difference and borrow).
Block Diagram: -

Truth table: -

Logic circuit diagram: -

 Conclusion: -In conclusion, a half subtractor is a digital circuit that performs the
subtraction of two binary digits and provides two outputs, difference and borrow.

7.TO VERIFY THE TRUTH TABLE OF FULL SUBTRACTOR

COMBINATIONAL CIRCUIT

Definition: -

A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, taking into account borrow of the previous adjacent lower
minuend bit. This circuit has three inputs and two outputs. The three inputs A, B and Bin,
denote the minuend, subtrahend, and previous borrow, respectively. The two outputs, D and
Bout represent the difference and output borrow, respectively.

Block diagram: -

Truth table: -
Logic circuit diagram: -

Conclusion: -Although subtraction is usually achieved by adding the complement of

subtrahend to the minuend, it is of academic interest to work out the Truth Table and logic
realisation of a full subtractor; x is the minuend; y is the subtrahend; z is the input borrow;
D is the difference; and B denotes the output borrow. 
8.TO VERIFY THE TRUTH TABLE OF DECODER COMBINATIONAL
CIRCUIT

Definition: -

Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output lines.
One of these outputs will be active High based on the combination of inputs present, when
the decoder is enabled. That means decoder detects a particular code. The outputs of the
decoder are nothing but the min terms of ‘n’ input variables lines when it is enabled.

Block diagram of decoder: -

2-to-4- line decoder: -

A decoder takes in an address and then activates the output line corresponding to it. Pulling
that line high or low depending on the decoder. The 2to4 means it takes a 2-bit address and
controls 4 outputs. The number of outputs is always 2 inputs. They typically have an enable
input to make it ignore the input and turn all outputs off.

Block diagram: -
Truth table: -

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows: -

Y3=E.A1.A0
Y2=E.A1A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expression is given below: -

3-to-8- line decoder: -

Definition: -

The 3-to-8-line decoder is also known as Binary to Octal Decoder. In a 3-to-8-line decoder,
there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e.,
A0, A1, and A2. This circuit has an enable input 'E'. Just like 2-to-4-line decoder, when enable
'E' is set to 1, one of these four outputs will be 1. The block diagram and the truth table of the
3-to-8-line encoder are given below.

Block Diagram:

Truth Table: -
The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows: -

Y0=A0'A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below: -

Conclusion: -

A decoder is an IC which splits an n-bit input value into 2 n output lines. A decoder has many
uses, but the one presented here is translating a 2-bit input value into 4 lines to allow the 4
different operations of the CPU. The decoder will also be used in the next chapter.
9.TO VERIFY THE TRUTH TABLE OF ENCODER COMBINATIONAL
CIRCUIT.

Definition: -

The encoders are used for coding binary data. They are opposite to decoders. So, they
perform inverse operation of a decoder. The opposite of the decoding process is called
encoding. The encoder is a combinational logic circuit that converts an active input signal
into a coded output signal.

It has n input lines, only one of which is active at any time and m output lines. It encodes
one of the active inputs to a coded binary output with m bits. In an encoder, the number of
output lines is less than the number of inputs. If an encoder has n input lines and m output
lines than

N<=2m.

Block diagram-
For example, let us consider Priority Encoder. It is a special type of encoder in which
priority is given to the input lines. If two or more input lines is HIGI at the same time, then
the input line with highest priority is considered. In a 4-to-2-line priority encoder, there are
four inputs say DO, D1, D2 and D3 and two outputs say YO and YI. Out of the four inputs
D3 has the highest priority and DO has the lowest priority. That means if D3 - 1 then YI YO
will be equal to 11 irrespective of the other inputs. Similarly, if D3 = 0 and D2 = 1 then YI
YO will be equal to 10 irrespective of the other inputs.

A 4-to-2-line priority encoder can be represented by the fallowing block diagram –

TRUTH TABLE-

An encoder can be constructed using AND, NOT, OR gates. From the above truth table, the
digital logic circuit for 4-to-2-line encoder can designed as follow-
Conclusion: -

• Encoders are combinational circuits implemented with the help of logic gates.

• The main idea behind using encoders is to save space occupied by data and reduce the
number of wires required to implement circuits.

• Encoders have maximum 2n input lines and n output lines.

• Types of Encoders discussed:

1. 4:2
2. 8: 3 (octal to binary)
3. Decimal to BCD
4. Priority Encoder

• Priority encoder solves the problem of ambiguity when all inputs are low, and also the
main problem of more than one active High inputs in encoders.
10. TO VERIFY THE TRUTH TABLE OF MULTIPLEXER
COMBINATIONAL CIRCUIT.
12.TO VERIFY THE WORKING AND TRUTH TABLE OF SR FLIP
FLOP.

Definition:

SR flip flop, also known as SR latch is the basic and simplest type of flip flop. It is a single
bit storage element. It has only two logic gates. The output of each gate is connected to the
input of another gate.

The state of the SR flip flop is determined by the condition of the output Q If its value is 1.
then the state is said to be SET and if Q-0, the state is said to be RESET. Hence it is called
SR flip flop. The SR flipflop can be constructed by using NAND gates or NOR gates. In the
following section, let us learn at SR flip flop in detail.

SR flip flop

It has two active-low inputs S, R' and two outputs Q, Q’.

Block Diagram:
Logic Diagram: -

Operation and truth table

When S’ = 0, R’ = 0, the respective next state outputs will be Q +1 = 1 and Q’+1 = 1, which is
not allowed, since both are complement to each other.

When the inputs are S’ = 0, R’ = 1, irrespective of the value of Q’, the next state output of
NAND gate A is logic HIGH, i.e Q+1 = 1, which will SET the flip flop. So the two inputs of
NAND gate B are R’ = 1 and Q = 1. The output thus produced is Q’+1 = 0.

For the inputs S’ = 1, R’ = 0, irrespective of the values of Q, the next state output of NAND
gate B is logic HIGH, i.e, Q’+1 = 1. The two inputs for NAND gate A are S’ = 1 and Q’ = 1,
producing an output Q+1 = 0, which will RESET the flip flop.

When the inputs are S’ = 1, R’ = 1 and the present state outputs are Q = 1 and Q’ = 0, then the
next state output produced from the NAND gate A is Q+1 = 1. If Q = 0 and Q’ = 1, the next
state output is Q+1 = 0. In this case, there is no change in the output state.

Truth table-