porta not

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios IS
PORT(

A: IN STD_LOGIC;
Y: OUT STD_LOGIC
);

END exercicios;
ARCHITECTURE behavior OF exercicios IS
BEGIN
Y <= (NOT A);
END behavior;
----------------------------------------------------------------------porta and
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios IS
PORT(

A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC
);

END exercicios;
ARCHITECTURE behavior OF exercicios IS
BEGIN
Y <= (A AND B);
END behavior;
--------------------------------------------------------------------------porta or
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios IS
PORT(

A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC
);

END exercicios;
ARCHITECTURE behavior OF exercicios IS
BEGIN
Y <= (A OR B);
END behavior;
----------------------------------------------------------------------porta NAND
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios IS
PORT(

A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC
);

END exercicios;
ARCHITECTURE behavior OF exercicios IS
BEGIN
Y <= (A NAND B);
END behavior;
------------------------------------------------------------------porta nor
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios IS
PORT(

A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC
);

END exercicios;
ARCHITECTURE behavior OF exercicios IS
BEGIN
Y <= (A NOR B);
END behavior;
------------------------------------------------------------------porta xor
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios IS
PORT(

A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC
);

END exercicios;
ARCHITECTURE behavior OF exercicios IS
BEGIN
Y <= (A XOR B);
END behavior;
------------------------------------------------------------------porta xnor
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios IS
PORT(

A: IN STD_LOGIC;
B: IN STD_LOGIC;
Y: OUT STD_LOGIC
);

END exercicios;
ARCHITECTURE behavior OF exercicios IS
BEGIN
Y <= (A XNOR B);
END behavior;
------------------------------------------------------------------mux

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicios2 IS
PORT
TOR(15 DOWNTO 0);

portas :

IN STD_LOGIC_VEC

sel :

IN STD_LOGIC_VEC

saida :
enable :
);

OUT STD_LOGIC;
IN STD_LOGIC

TOR(3 DOWNTO 0);

END exercicios2;
ARCHITECTURE behavior OF exercicios2 IS
SIGNAL saida_aux : STD_LOGIC;
BEGIN
WITH sel SELECT
saida_aux <=
portas(0) WHEN "0000",
portas(1) WHEN "0001",
portas(2) WHEN "0010",
portas(3) WHEN "0011",
portas(4) WHEN "0100",
portas(5) WHEN "0101",
portas(6) WHEN "0110",
portas(7) WHEN "0111",
portas(8) WHEN "1000",
portas(9) WHEN "1001",
portas(10) WHEN "1010",
portas(11) WHEN "1011",
portas(12) WHEN "1100",
portas(13) WHEN "1101",
portas(14) WHEN "1110",
portas(15) WHEN "1111";
WITH enable SELECT
saida <=
'0' WHEN '0',
saida_aux WHEN '1';
END behavior;
------------------------------------------------------------------7seg
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY exercicio2 IS
PORT
; --abcdefg

codigo:

IN STD_LOGIC_VECTOR (3 DOWNTO 0)
seg:

OUT STD_LOGIC_VECTOR (6

LT:
RBI:
BI_RBO:
);

IN STD_LOGIC;
IN STD_LOGIC;
IN STD_LOGIC

DOWNTO 0);

END exercicio2;
ARCHITECTURE behavior OF exercicio2 IS
SIGNAL seg_aux :STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
seg<=
"1111111" WHEN BI_RBO = '0' AND codigo = "0000"
AND LT = '0' ELSE
"1111111" WHEN RBI = '0' AND LT = '1' AND codigo
= "0000" ELSE

"0000000" WHEN LT = '0' AND BI_RBO = '1' ELSE

seg_aux WHEN LT = '1' AND BI_RBO = '1' AND RBI =
'1';
WITH codigo SELECT
seg_aux <=

END behavior;

"0000001"
"0110000"
"1101101"
"1111001"
"0110011"
"1011010"
"1011111"
"1110000"
"1111111"
"1111011"
"1111111"

WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN
WHEN

"0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
OTHERS;