Low Power Techniques for VLSI Design
Atin Jain Dhirubhai Ambani Institute of Information and Communication Technologies (DA-IICT), Gandhinagar firstname.lastname@example.org Supervisor: Prof. Amit Bhatt, DA-IICT
In recent years consumer electronics market has witnessed tremendous growth in the PDAs and other hand held devices which ought to provide mobility to the user while providing connectivity and applications. The power consumption is an important factor in all these devices. Longevity is one of the basic and most desired feature in the PDA category. Thus industry today is looking for low power designs and techniques to increase longevity and of the device. This report discusses important issues and techniques employed in the low power VLSI design. This report is in partial fulfillment of the Summer Research Internship done as part of curriculum of B.Tech (ICT), DA-IICT, Gandhinagar, India, under Prof. (Dr.) Amit R. Bhatt, Faculty, DAIICT.
design in mainly three areas Power, Area and Timing. The digital design flow consists of two divisions broad but well defined namely Frontend and Backend. The work described in this report mainly concentrates on the frontend part with late glimpse of the backend techniques and methodologies. My work as the intern was mainly limited to the learning of the tool and understanding the basic criteria and techniques of optimization. The design used for the work is OpenMSP430 which is an open source equivalent Verilog implementation of Texas Instrument’s TM MSP430 and contains all the features of TM MSP430 . The core comes with some peripherals (16x16 Hardware Multiplier, GPIO, TimerA, generic templates) and most notably with a Serial Debug Interface supporting the MSPGCC GNU Debugger (GDB) for in-system software debugging and technology library used is NANGATE open source library.
Keywords Low power, process corners, MOSFET, NANGATE Library, Encounter, RTL Compiler, Synopsis Design Constraints file, TCl scripts, timing closure, placement and routing.
Digital Design Flow
In ASIC Design flow among various tools are used for simulation and synthesis of the designs among them one which is widely used in industry is Cadence RTL Compiler (hereafter rc). RC is used to optimize the and synthesize
Following diagram explains the digital design flow.
determining the most suitable design implementation using the given design constraints such as clock cycle. Performs high level optimization like removing dead code d. After that the GDSII file is generated which can directly be sent to foundry for the production of chip. Infers registers in the design c. RC takes top level design.Tech. optimizes the logic and performs technology mapping. capacitance value are provided. capacitance and interconnects etc. synthesizes the RTL blocks. synthesized netlist and constraint file are provided to SoC encounter tool. Checks semantics After elaboration RC has the internally created data structures for the whole design so that design and optimization constraints can be applied to the design. B.
Figure 2. Synthesize to generic b. power grid routing.
The next step in the digital design flow is the Synthesis. placement cells and metal line routing is done. Timing Constraints. Synthesize to mapped c. Synthesis is the technique of
Image Courtesy: Maullik Padia. Elaboration is the technique of expanding the design into its most generic form using flip flops and generic gates. the design floor plan. input output delays. In SoC. Frontend flow
a.This report is in partial fulfillment of the work done under Summer Internship.lib). also the physical information like resistance. technology library and so on. During elaboration RC performs the following tasks a. size and power consumption. In Back End.Consists of specifying environment specifications like maximum fanout. The library file contains information about the cell delay. There are mainly two types of constraints that the designs are subjected to a. Design Constraints. Mainly three kinds of synthesis options are available In front end Verilog code for the equivalent hardware implementation is provided which is then elaborated and synthesized by the RC. Design Appropriate Low Power Techniques
. Builds data structures b.Consists of mainly clock frequency and slack optimizations and timing closure b. Synthesize to placed The information provided by user here is desired constraints if any and the cell information library (.
The first and foremost optimization is done for the timing closure.
Timing and Delays
Timing closure refers to the state where a design meets all the necessary and applied timing constraints like setup. Slew Rate
Smaller the slew at the input larger is the input transition time and larger is the delay.
IV. Slew rate Image Courtesy: Wikipedia. hold.2 0 0 0 TNS 0 0 0 0 Dyn Pr 2501052 St Pr 52822 Area 38170 Cost I2C C2O C2C I2O
a. clock frequency etc. No optimization technique will ever compromise with the timing constraints and especially with the frequency component of the design. This output slew directly depends upon the load connected to its output. b.
reactance introduced by inter-connects and metal power lines. So the slew rate at output is caused by the load capacitance. 𝑆𝑅 = max � 𝑑𝑉𝑜𝑢𝑡 � 𝑑𝑉𝑖𝑛
The slew rate can be measured using a function generator usually by applying square wave and using oscilloscope to measure slope at the output as shown in figure
Figure3. In the work described in this report the gate delays for all of the gates was fixed at 20% of the clock time-period. Effect of Slew Rate The slew rate of an electronic circuit is defined as the maximum rate of change of the output voltage. These delays are basically due to the charging and discharging effects of the capacitor
Propagation delay is the time gap between change at the input and acceptable change at output. In case of PLE (Placement and Layout Estimation) model interconnects and their relative placement are important. Clock frequency selection
The concept and basic theory of the timing constraints lie in the clock period and various delays and introduced in the working of any module.Tech. there is corresponding output slew at its output pin. After timing closure the appropriate frequency of operation is as below
Clock 1280 WNS 1. In applying timing constraints it is important to specify gate and interconnect delays. If the design is elaborated using WLM model (Wire Load Model) there is no interconnect delay because this model does not take into account the placement and routing.This report is in partial fulfillment of the work done under Summer Internship. B. Larger is the load capacitance larger would be the slew degradation. Propagation Delay and Output Transition
Table 1. This is an approximation towards the worst case operations of the design. Slew rate is usually expressed in units of V/µs. Whenever a slew is applied to a cell's input pin.
. This is the most important constraint because until and unless the policy permits the running frequency or the working frequency of the design is the highest priority constraint.
Thus if a source takes longer to transition from low to high the change at the output will take longer to change. If the input transition rate or slew is more than the time taken for this information to travel through the cell takes longer.Tech. If the supply voltage is increased the propagation delay is reduced because of the more Isat because of the increased mobility and thus rapid (dis)charging of the capacitances. 𝑉𝐷𝐷 2 . 𝑇𝑝𝐻𝐿 = 𝐾. 𝑅𝑒𝑞𝑛 + 𝑘. 𝑉𝐷𝐷 2 . The propagation delay of a CMOS inverter is simply proportional to the time constant of the RC equivalent circuit thus formed taking into consideration the output load capacitance and pull-down resistor in case of High to low transition and pull-up resistor in case of Low to High transition. but keeping it low effects the switching speed of the MOS due to
. 𝑉𝐷𝐷 Thus if the gate switches at the rate of ‘f’ times per second the total power consumed dynamically is 𝑃𝑑𝑦𝑛 = 𝐶𝑙. 𝑉𝐷𝐷.
Thus it can be clearly seen that the dynamic power dissipation depends directly on the Output load capacitance.This report is in partial fulfillment of the work done under Summer Internship. DA-IICT
Output transition is the time taken by the signal to change from one level to another. 𝐶𝑙
Increase in the temperature has adverse effect on the Propagation Delay. 𝑅𝑒𝑞𝑝 2
Since gate is not switched in every cycle dynamic power becomes where ∝ is the switching factor. The energy dissipated during one transition can be written as 𝐸𝑣𝑑𝑑 = 𝐶𝑙 ∗ 𝑉𝐷𝐷 2
This expression can be derived by observing that during low to high transition Cl is loaded with a charge of value 𝐶𝑙. 𝑅𝑒𝑞𝑝. 𝑉𝐷𝐷. 𝑉𝐷𝐷
where Reqp and Reqn are the pull-up and pulldown resistors respectively. For NANGATE library these levels are the 30% and 70% of the VDD Propagation delay depends upon input transition and output capacitance. 𝑅𝑒𝑞𝑛. Dynamic Power Dissipation Dynamic Power is dissipated by the switching activity of the cell. as explained earlier increase in the temperature leads to rapid velocity saturation of charge carriers thus limiting the Isat to a lower value. For providing this charge requires the following energy 𝐸𝑣𝑑𝑑 = 𝐶𝑙.
a. 𝑓 𝐸𝑣𝑑𝑑 = 𝐶𝑙. B. 𝑓
Thus it can be clearly seen that propagation delay depends directly upon the load capacitance and similarly the output transition also depends upon the load capacitance. 𝐶𝑙 𝑇𝑝𝐿𝐻 = 𝑘. Also if the VDD is kept higher the energy consumption increases. 𝑃𝑑𝑦𝑛 =∝. 𝑉𝐷𝐷 2 𝐸𝑣𝑑𝑑 = 𝑄.
𝐾. 𝐶𝑙. Thus propagation delay becomes 𝑇𝑝 = 𝑇𝑝𝐻𝐿 + 𝑇𝑝𝐿𝐻 2
where K and k are the constants.
𝑇𝑝 = 𝐶𝑙.
Effect of Clock Gating
As can be clearly seen since OpenMSP430 is mostly a sequential design Clock gating has significant effect on power reduction. Clock Gating. Power Gating. Static Power Consumption Static Power can be modeled as 𝑃𝑠𝑡𝑎𝑡 = 𝐼𝑠𝑎𝑡. 𝑉𝐷𝐷
change keeps on transitioning is a major cause of dynamic power consumption. 𝑉𝐷𝐷 2 . Flip-Flop Based Clock gating is one of the most effective techniques of power consumption reduction. Since as mentioned earlier most of the power is consumed dynamically while switching. Multi Threshold Voltage. Operand Isolation
. but the timing closure is disturbed and will have detrimental effect on the design’s functioning. Total Power Consumption
Total power consumption is the sum of the power dissipated as Dynamic power and Static power.
Figure 4. a.
VI. It includes Architectural.
Low power Techniques
There are different techniques that can be implemented to reduce both of Dynamic and Static power consumptions. In this report. 𝑉𝐷𝐷
There are variations of Clock Gating techniques in which the gating is done a. Operand Isolation. Latch Based b. Clock Gating Clock gating is the technique of applying clock selectively to the various modules and parts of the design. Latch based clock gating
lower channel current. 𝑓 + 𝐼𝑠𝑎𝑡. since clock is the only module that irrespective of the logic
Table 2.2 -54. The results of applying clock gating to the OpenMSP430 is as follows Cell Without CG With CG Area 38170 40129 Power 2501052 1609652 Slack 1. 𝐶𝑙. B.Tech. Multi Supply Voltage.8
Dynamic power plays a very dominant role in the total power consumption and it usually contributes to the 90% of the power dissipation in a cell.This report is in partial fulfillment of the work done under Summer Internship. and Dynamic Voltage Frequency Scaling. Operand Isolation is done. Thus total power can be written as
𝑃𝑡𝑜𝑡 =∝. Gate Based c. Thus effectively it is a trade-off between power consumption and speed of the cell in consideration. The downside of this technique is that though it can be implemented in both combinational and sequential circuits the power is reduced only in the sequential circuits because of the low penetration of clock in the combinational circuits. Also the area consumed is significantly increased due to the control circuitry introduced by the clock gating technique b. implementation of Clock Gating. b.
Table 3. B. The implementation of Operand Isolation on OpenMSP430 does not significantly reduces power consumption because OpenMSP430 is strongly a sequential design with minimal combinational circuitry Cell Without OI With OI Area 38170 38745 Power 2501052 2359117 Slack 1.This report is in partial fulfillment of the work done under Summer Internship. if during a particular input cycle. M Sreekanth for their everlasting support and help.
. I also thank my colleagues Darshal Patel. Operand Isolation Image Courtesy: Maullik Padia. DA-IICT
Operand Isolation is the technique of isolating the operands if during certain particular transition or logic change the calculation of the operands is futile. Gayatri Rathod. design constraints and tolerances. V S S Ravi Kiran.7
I’m thankful to my mentor Prof. operand isolation is not used all the cells are switched and outputs calculated irrespective of the datapath of the logic. There are several techniques available currently which reduce the power consumption significantly.Tech.
VII. I sincerely thank DA-IICT VLSI Lab for the tools and resources which were indispensable for my work. Amit Bhatt for his continuous guidance.2 0. this renders the circuit to consume more power when there is no need of the combinational execution of many cells. Finally and most gratefully I thank my parents for making me able to this extent.
VIII. the decision for which is dependent upon many factors such as system architecture.
Figure 5. RTL implementation. process corners etc. The intelligent and well informed choice of technique will ensure the best technique for power reduction which seems to be keyword for future drive along with power and speed. Effect of Operand Isolation
As is evident from the table Operand Isolation has minimal effect on the power consumption of the circuitry. Design Appropriate Low Power Techniques
This unnecessary switching can be controlled by simply controlling the execution of the logic at various sites.
Longevity of the battery backup of the portable PDAs has driven the development of Low Power Design techniques and will continue to do so. For instance. The application of Operand Isolation however increases the area due to introduction of the control circuitry. motivation and support.