Q)What do the following term stands for: a:AOCV (Advanced on chip variation) -On-Chip-Variation (OCV) timing analysis uses

a constant derating factor -whereas AOCV applies derated value is a function of path-depth and possibly distance. -It uses intelligent techniques for context specific derating instead of a single global derate value. -Thus reducing the excessive design margins and leading to fewer timing violations. -This represents a more realistic and practical method of margining, alleviating the concerns of overdesign,reduced design performance, and longer timing closure cycles. -The Advanced OCV solution determines derate values as a function of logic depth and/or cell, and net location. -These two variables provide further granularity to the margining methodology by determining how much a specific path in a design is impacted by the process variation. b:SSTA (Statistical static timing analysis) Limitation of normal STA -Cannot easily handle within-die correlation. -Needs many corners to handle all possible cases. -If there are significant random variations, then in order to be conservative at all times, it is too pessimistic to result in competitive products. s is yet another example of how path validity rules can be applied.) -Clock phase rules between source and destination of a path, between inputs of a dynamic logic gate, etc. -Detailed clock skew constraints within and between various regions in a global clock distribution network. -General timing constraints, such as: -Skews at cell inputs -Pulse-widths -Delay of a path segment -Skew between delays of two path segments, etc. -Functional rules -mutual exclusion of drivers at tristate buses, requirement that there should be a default driver on every tristate bus. -mutual exclusion of multiplexer select signals, etc. -False timing path checks based on logic functionality. -Signal coupling checks based on both timing and functional analyses. ########################################## Q)List the files that need to be given for Gate level simulation from STA? -Netlist -SDF (Standard Delay Format)

########################################## Q)Should you or should you not do hold analysis at Pre CTS stage ?Give reason for your answer ? -Hold is fixed after CTS. -Setup timing analysis is done at the stage of placement. -At this stage of placement if there is any setup violations then it is fixed only by making changes on data path. (like inserting buffers,using LVT cells,cell upsizing) -But we don't touch the clock path and at this stage clock is not propagated so,skew and insertion delay doesn't come into exsistance. -So,set up is fixed at the stage of placement and hold is fixed after the CTS as clock is being propogated, skew and insertion delay come into exsistance after CTS. -More Buffers are inserted during CTS, Which relaxes setup but not good for hold. ########################################## Q)Why is Pre Layout STA necessary, what do you look for in this STA ? The difference between pre-layout sta and post-layout sta -The most difference is wire delay calculation. -At the pre layout stage, use wire_load_model provided by library vendor or extracted by ourselves to calculate the wire delay. -At the post layout, first the net RC parameter is extracted to calculate the wire delay based on placement of cells. -So the post layout STA is more accurate. In Pre-layout STA we try solve for setup (zero wireload analysis is also done) -In zero wireload analysis we assume the NET RC values to be zero. -Having zero wireload models we if are not able to solve for setup. -The Architecture itself has to be re-designed.

########################################## Why migrate to SSTA? -SSTA attacks these limitations more or less directly. -First, SSTA uses sensitivities to find correlations among delays. -Then it uses these correlations when computing how to add statistical distributions of delays. c:IR STA -Static IR Drop Analysis calculates an Average voltage drop. -Often used early in the PD design flow process to detect weak Power Delivery. For example, -missing power vias or arrays, high current and high current densities, and power routing

that might be insufficient in size. -It also accurately highlights IR drop and electromigration issues. -A common used analysis to determin overall power delivery robustness. Difference between Static and dynamic analysis STATIC ANALYSIS -Static power rail analysis evaluates the IR drop caused by high average currents flowing through a designs resistive power rails. DYNAMIC ANALYSIS -Dynamic analysis evaluates the IR drop caused when large amounts of circuitry switch simultaneously. -Causing peak current demand on the power rails. -This current demand can be highly localized and brief within a single clock cycle,can result in an IR drop that causes additional setup or hold-time violations. -High IR drop on clock networks causes hold-time violations. -while IR drop on signal nets causes setup-time violations. d:DMSA (Distributed Multi-Scenario Analysis) -The greater design functionality and complexity afforded by today's smaller geometries combined with accompanying physical phenomena. -This has led to an explosion in the number of scenarios which need to be verified. -Verification of a chip design requires analysis of many individual scenarios that represent different operational modes and voltage, temperature and process corners. -Analyzing and managing the analysis of these scenarios is simplified with PrimeTime's Distributed Multi-Scenario Analysis (DMSA) capability. -DMSA allows designers to set up, distribute, run, and perform ECO fixing simultaneously across multiple scenarios, thereby reducing overall turnaround time. -- INSERT -e:Vt Swap (HVT,LVT,SVT) Vt swapping: -LowVt (LVT) is used to close timing on critical paths. -HighVt (HVT) is used to reduce leakage on non-critical paths. -StandardVt (SVT) for other cells. Above techniques affect each other: -Using smaller gate sizes improves the power but increases the delay. -HVT reduces the power but hurts the timing. -We can use large gate sizes and less LVTs, or smaller gate sizes and more LVTs, etc. We may use gate sizing to help Vt-swapping. f:CRPR (Clock Re-convergence Pessimism Removal) -It creates the worst case scenario.

-Analyzing setup timing using slow corner for lanunching clock path, and fast corner for capturing clock path. -The issue is these clock paths share the common path way upstream of the clock trees and OCV applies the different delay for those clock buffers on the common path. -In reality, it is not possible that a single instance has both of slow and fast corner characteristics. -CRPR forces those cells common to both of launch and capture clock path to use the same delay. -CRPR can be used to remove this pessimism. g:Node Slack -Compute the slack = RAT AAT for each node. -RAT is the required arrival time, latest time signal can transition. -AAT is the actual arrival time, latest possible transition time. -By convention, AAT is defined at the output of every node. -Negative slack at any output means the circuit does not meet timing. -Positive slack at all outputs means the circuit meets timing.

########################################## Q)How do you check if the timing constraints cover the entire design or not ? SDAs static design constraint verifier The following are examples of typical rules and constraints that can be verified exhaustively using SDA: -Cell usage rules, which can verify rules related to input and output pins of cells: -Functional relationships -Timing phase relationships -Timing skew -Load limits -Connectivity rules at inputs or outputs of a cell. -Path validity rules, which can be coded in detail to verify the existence of paths which run between and through specific points in the design (and meet specific logic properties) -The nonexistence of invalid paths. -Exclusive paths between specific points. -The paths can be combinational, or they can be sequential paths that pass through multiple flip-flops or latches. -Testability rules, such as: -Scan chain connectivity -Controllability/observability logic -Test clock schemes -Mutual exclusion conditions to avoid logic conflicts. (This is an example of how path validity rules can be used in particular applications.) -Clock gating/buffering and clock distribution rules. (This is yet another example of how path validity rules can be applied.)

-Clock phase rules between source and destination of a path, between inputs of a dynamic logic gate, etc. -Detailed clock skew constraints within and between various regions in a global clock distribution network. -General timing constraints, such as: -Skews at cell inputs -Pulse-widths -Delay of a path segment -Skew between delays of two path segments, etc. -Functional rules -mutual exclusion of drivers at tristate buses, requirement that there should be a default driver on every tristate bus. -mutual exclusion of multiplexer select signals, etc. -False timing path checks based on logic functionality. -Signal coupling checks based on both timing and functional analyses. ########################################## Q)List the files that need to be given for Gate level simulation from STA? -Netlist -SDF (Standard Delay Format) ########################################## Q)Should you or should you not do hold analysis at Pre CTS stage ?Give reason for your answer ? -Hold is fixed after CTS. -Setup timing analysis is done at the stage of placement. -At this stage of placement if there is any setup violations then it is fixed only by making changes on data path. (like inserting buffers,using LVT cells,cell upsizing) -But we don't touch the clock path and at this stage clock is not propagated so,skew and insertion delay doesn't come into exsistance. -So,set up is fixed at the stage of placement and hold is fixed after the CTS as clock is being propogated, skew and insertion delay come into exsistance after CTS. -More Buffers are inserted during CTS, Which relaxes setup but not good for hold. ########################################## Q)Why is Pre Layout STA necessary, what do you look for in this STA ? The difference between pre-layout sta and post-layout sta -The most difference is wire delay calculation. -At the pre layout stage, use wire_load_model provided by library vendor or extracted by ourselves to calculate the wire delay.

)Why is Pre Layout STA necessary, what do you look for in this STA ? The difference between pre-layout sta and post-layout sta -The most difference is wire delay calculation. -At the pre layout stage, use wire_load_model provided by library vendor or extracted by ourselves to calculate the wire delay. -At the post layout, first the net RC parameter is extracted to calculate the wire delay based on placement of cells. -So the post layout STA is more accurate. In Pre-layout STA we try solve for setup (zero wireload analysis is also done) -In zero wireload analysis we assume the NET RC values to be zero. -Having zero wireload models we if are not able to solve for setup. -The Architecture itself has to be re-designed.

########################################## ) Prepare a basic script file for doing STA using Cadence ETS. ###################Read the timing libraries to be used during setup or hold. read_lib max max.lib min min.lib ##################Read the verilog file. read_verilog design.v ###################Set the top module for analysis. set_top_module top ###################Read the timing constraints. read_sdc design.sdc ###################Set the analysis mode to setup. set_analysis_mode setup ##################Set the operating condition for setup analysis. set_op_cond WCCOM library slowlib #################################