A Single-Inductor Dual-Output Integrated DC/DC Boost Converter for Variable Voltage Scheduling

Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui and Philip K. T. Mok

Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology Clear Water Bay, Hong Kong SAR, China Fax: (852)-2358-1485 E-mail: eemds@ee.ust.hk
Abstract | An integrated boost DC/DC converter that provides two di erent outputs with a 1.8V input using only one inductor is presented. The converter works in discontinuous conduction mode and employs time division multiplexing in switching the inductor current to the two outputs. Synchronous recti cation for high e ciency is implemented. Techniques for current sensing, inductor ringing suppression and controller design are discussed. At an oscillator frequency of 1MHz, the conversion e ciency reaches 90% at 350mW.
Ring Suppression Vx
L

Current Sensor A

PMOS1 D1a,D1b NMOS Over Current Sensing D2a Couta Rloada

Voa

A
Current Sensor B

Vg

Vob PMOS2 D2b Coutb Rloadb

B
Dead Time Control Buffer
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CHa

EAa

Vrefa

ITH the proliferation of battery-operated portable applications, power dissipation plays an important Fig. 1. Schematic of the Proposed Converter role in evaluating the performance of a system. For a digital processor, one e ective way to reduce power consumption is to employ a variable voltage scheme. A DC/DC converter is required to provide the variable output voltage to the processing elements 1]. For system-on-chip (SOC) applications, di erent optimal voltages are required for di erent processor cores and a DC/DC converter that provides multiple output voltages, of which the values can be changed according to speed and power requirement, is very desirable. In this research, a DC/DC converter with a single inductor and two output voltages is presented. A single-inductor multiple-output DC/DC boost converter is discussed in 2] recently. Two timing schemes were suggested, but the controller was not discussed and no experimental results were shown. Besides, the conFig. 2. Timing Diagram of the Proposed Converter verter needs 2N+1 power devices for N outputs, which is detrimental to the e ciency of the converter, especially T ip- op the clock signal of which comes from an on-chip for outputs with low voltages. oscillator. These control signals decide which output node the current should ow to in each period. D2a and D2b are II. Converter Architecture determined by the outputs of the error ampli ers and the A. Circuit topology and control scheme current sensing signals of the converter. Fig.2 shows the Fig.1 shows the block diagram of the proposed timing diagram of the converter. The topology can easily single-inductor dual-output DC/DC boost converter. The be extended to generate multiple output voltages. For a two sub-converters A and B both work in discontinuous conventional design, if N output voltages are needed, N conduction mode (DCM) with a xed switching frequency inductors and 2N power devices are required. For the proof fs and a period of T. The control scheme is one form posed topology, only one inductor and N+1 power devices of time division multiplexing (TDM). For converter A, are used, and saves N power devices as compared to the the ramp-up time of the inductor current is D1a T and converter proposed in 2]. Of course, the inductor and the the ramp-down time is D2a T . The duration of zero cur- main power switch have to sustain larger current stress. rent is thus (1-D1a-D2a )T. Similar de nitions for D1b and D2b can be applied to converter B. For the converter to B. Circuit design consideration work properly, the conditions that D1a +D2a < 0.5 and Synchronous recti cation is a technique to replace D1b +D2b < 0.5 have to be imposed, so that the inductor free-wheeling diodes by transistors with low on-resistance, works in discontinuous conduction mode. Two comple- and emulate the diodes by switching o the transistors mentary control signals PHa and PHb are generated by a when the currents attempt to ow in the reverse direction.
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I. Introduction

CONTROLLER
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COMP

EAb CHb Ramp

Vrefb

PHa

D1a

D2a

PHb

D1b

D2b

il

By implementing a slight modi cation of this feature in the controller to direct the power ow, those diodes in 2] that are connected in series with power transistors can be eliminated 3]. The present design uses PMOS power transistors as switches to pass energy from the inductor to the outputs. For a boost converter, the two output voltages are both higher than the supply voltage. The substrate of the switches and the supply voltage of the dead-time control bu er (used to drive the switching transistors) are connected to the highest DC voltage in the system, so that both switches can be fully turned on and o . To implement synchronous recti cation, consider that once a switch is turned on, the current can ow in either direction. To prevent the inductor current from owing back to the source, zero (inductor) current detection is needed. To enhance e ciency and to reduce pin-count, current sensing is done by transistor scaling 4] rather than using external sensing resistor. Since the inductor works in DCM, there are time intervals that all switches are o . The inductor and the ltering capacitor then forms an oscillatory circuit, with damping only controlled by the load resistance. Very often, large ringing occurs at node Vx , causing electromagnetic interference and results in reduced e ciency. Our design incorporates a ringing suppression circuit ( 5]) to short the inductor when all the power transistors are o . (See Fig.1) The converter was designed and fabricated using HP 0.5 m CMOS process from MOSIS. Fig. 3 is a microphotograph of the chip. Fig. 4 show the waveforms of the inductor current and the voltage of node Vx respectively. Fig. 5 shows the two outputs of the converter in the steady state with reference to the inductor current. Table I summaries the testing results of the converter. With an inductor resistance of 125m and capacitor ESRs of 150m , the converter achieves an e ciency of 90% when delivering a total power of 350mW. The ltering capacitors of the two outputs are 47 F and 44 F respectively.
The experimental results of the converter
supply voltage inductor die area conversion efficiency output voltages switching frequency maximum loading currents 1.8V 1 H 2 2.4 90% 3.0V 3.45V 500kHz 500kHz 50mA 50mA

NMOS

NMOS

PMOS1 Predriverm

PMOS2

Controller

Fig. 3. Microphotograph of the converter

III. Experimental results

Fig. 4. Inductor current and voltage of Vx

TABLE I

Fig. 5. Outputs of the Converter

mm

and power devices are reduced signi cantly for the present design, which is very desirable for SOC applications.
1] 2] 3]

In this paper, a single-inductor dual-output DC/DC boost converter and its control schemes are dis- 4] cussed. Experimental results show the validity of the controller with high e ciency. An obvious extension of 5] the topology is easily made for more outputs. Compared with conventional converters, the numbers of inductors 2

IV. Conclusion

References V. Gutnik and A.P. Chandrakasan, An e cient controller for variable supply-voltage low power processing, IEEE Symp. on VLSI Circuits., pp.158-159, 1996. T. Li, Single inductor multiple output boost regulator, US Patent 6,075,295, June 13, 2000. W-H Ki, D.S. Ma, C-Y Tsui, and P. Mok, Single-inductor multioutput DC/DC converter with synchronous recti cation, Invention Disclosure, HKUST, Oct., 2000. W-H Ki, Current sensing technique using MOS transistors scaling with matched bipolar current sources, U.S. Patent 5,757,174, May 26, 1998. S-H Jung, N-S Jung, J-T Hwang and G-H Cho, An integrated CMOS DC-DC converter for battery-operated systems, IEEE Power Elec. Specialists Conf., pp.43-47, 1999.