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"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.

The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACTFloorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2003 Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

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About This Guide


The Libraries Guide is part of the ISE documentation collection.

Guide Contents
This guide contains the following: Discussion of the Xilinx Unified Libraries Slice Count information for FPGAs A listing of the various Functional Categories of design elements Architecture Specific Information chapters Individual chapters for each of the Design Elements

Additional Resources
For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.
Resource Tutorials Description/URL Tutorials covering Xilinx design flows, from design entry to verification and debugging

http://support.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser

Database of Xilinx solution records http://support.xilinx.com/xlnx/xil_ans_browser.jsp

Application Notes Data Book

Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm


Pages from The Programmable Logic Data Book, which contains devicespecific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging

http://support.xilinx.com/partinfo/databook.htm
Problem Solvers Tech Tips Interactive tools that allow you to troubleshoot your design issues

http://support.xilinx.com/support/troubleshoot/psolvers.htm
Latest news, design tips, and patch information for the Xilinx design environment

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

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About This Guide

Conventions
This document uses the following conventions. An example illustrates each convention.

Typographical
The following typographical conventions are used in this document:
Convention Courier font Courier bold Meaning or Use Messages, prompts, and program files that the system displays Example speed grade: - 100

Literal commands that you enter in ngdbuild design_name a syntactical statement Commands that you select from a menu Keyboard shortcuts

Helvetica bold

File Open Ctrl+C

Italic font

Variables in a syntax statement for ngdbuild design_name which you must supply values References to other manuals See the Development System Reference Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. ngdbuild [option_name] design_name

Emphasis in text

Square brackets [ ]

An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required. A list of items from which you must choose one or more Separates items in a list of choices Repetitive material that has been omitted

Braces

{ }

lowpwr ={on|off} lowpwr ={on|off} IOB #1: Name = QOUT IOB #2: Name = CLKIN . . . allow block block_name loc1 loc2 ... locn;

Vertical bar | Vertical ellipsis . . . Horizontal ellipsis . . .

Repetitive material that has been omitted

Online Document
The following conventions are used in this document:
Convention Blue text Red text Meaning or Use Example

Cross-reference link to a location See the section Additional in the current document Resources for details. Cross-reference link to a location See Figure 2-5 in the Virtex-II in another document Handbook. Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.

Blue, underlined text

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Whats New in This Release

Whats New in This Release


The following design elements have been removed from the current release:
GT10_3GIO_n MUXF8_D MUXF8_L

The following design elements have been added to the current release: IBUFDS_DIFF_OUT

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Table of Contents
About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Whats New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Xilinx Unified Libraries


Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applicable Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Attributes and Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 18 18 18 18 19 19

19 Spartan-II, Spartan-IIE, Virtex, and Virtex-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3 . . . . . . . . . . . . . . . . . . . . . . . . . 20

Flip-Flop, Counter, and Register Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20


Unconnected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Slice Count
About Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Slice Count for FPGA Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Architecture Specific Information


Spartan-II and Spartan-IIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex and Virtex-E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtex-II, Virtex-II Pro, Virtex-II Pro X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9500/XV/XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CoolRunner XPLA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CoolRunner-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39 41 45 47 51 53 55

Functional Categories
Arithmetic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Input Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Input/Output Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Input/Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Logic Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Map Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Memory Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Design Elements
ACC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACC4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADSU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADSU4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRLSHFT4, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BSCAN_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUF4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGDLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGMUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGMUX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFGSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107 111 119 121 127 131 137 145 149 153 155 157 159 161 163 165 167 171 173 175 177 179 181 183 185

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BUFGTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CAPTURE_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2CE, CB4CE, CB8CE, CB16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2CLE, CB4CLE, CB8CLE, CB16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2CLED, CB4CLED, CB8CLED, CB16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2RE, CB4RE, CB8RE, CB16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2RLE, CB4RLE, CB8RLE, CB16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2X1, CB4X1, CB8X1, CB16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CB2X2, CB4X2, CB8X2, CB16X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2CE, CBD4CE, CBD8CE, CBD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED . . . . . . . . . . . . . . . . . . . . . . . CBD2RE, CBD4RE, CBD8RE, CBD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2X1, CBD4X1, CBD8X1, CBD16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CBD2X2, CBD4X2, CBD8X2, CBD16X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8CE, CC16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8CLE, CC16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8CLED, CC16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC8RE, CC16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD4RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CDD4RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJ4CE, CJ5CE, CJ8CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJ4RE, CJ5RE, CJ8RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJD4CE, CJD5CE, CJD8CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CJD4RE, CJD5RE, CJD8RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16RSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV2,4,6,8,10,12,14,16SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKDLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKDLLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

187 189 193 195 197 199 201 207 213 219 223 227 233 239 243 247 253 257 261 265 271 277 283 289 295 299 303 307 313 317 321 325 331 335 339 343 347 349 351 353 355 359

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CLKDLLHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMP2, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMPM2, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMPMC8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CR8CE, CR16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRD8CE, CRD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D2_4E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D3_8E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D4_16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEC_CC4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DECODE4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DECODE32, 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD4CE, FD8CE, FD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD4RE, FD8RE, FD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDC_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD4,8,16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD4CE, FDD8CE, FDD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDD4RE, FDD8RE, FDD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

363 367 371 377 381 385 389 391 395 399 409 411 415 417 421 423 425 429 433 437 441 445 449 453 457 461 465 469 471 473 477 481 485 489 493 497 501 503 507 509 513 517

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FDDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDDSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDR_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRS_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDRSE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDS_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FJKSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FMAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTCPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FTDCLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

519 521 523 525 527 531 535 539 543 547 551 555 559 563 567 571 575 579 583 587 591 595 599 601 603 607 611 615 619 623 627 631 635 637 641 645 649 653 657 659 663 665

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FTDCLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 FTDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 FTDRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 FTDRSLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 FTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 FTPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 FTPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689 FTRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 FTRSLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 FTSRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 FTSRLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 GT_AURORA_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 GT_CUSTOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 GT_ETHERNET_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 GT_FIBRE_CHAN_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 GT_INFINIBAND_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 GT_XAUI_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 GT10_AURORA_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 GT10_AURORAX_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 GT10_CUSTOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 GT10_INFINIBAND_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 GT10_XAUI_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897 GT10_10GE_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 GT10_10GFC_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 GT10_OC48_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955 GT10_OC192_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 GT10_PCI_EXPRESS_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 IBUF, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013 IBUF_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 IBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 IBUFG, IBUFG_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 IBUFGDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 IBUFGDS_DIFF_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 ICAP_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043 IFD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 IFD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049 IFDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 IFDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 IFDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059 IFDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 IFDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063

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IFDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IFDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ILDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INV, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOBUF, IOBUF_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAGPPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KEEPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDC_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LD4CE, LD8CE, LD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDCPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDG4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDP_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LDPE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LUT1, 2, 3, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LUT1_D, LUT2_D, LUT3_D, LUT4_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LUT1_L, LUT2_L, LUT3_L, LUT4_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1067 1069 1071 1073 1077 1079 1081 1083 1087 1089 1091 1093 1095 1101 1103 1105 1107 1109 1111 1115 1117 1121 1125 1129 1133 1137 1141 1145 1149 1153 1157 1161 1165 1167 1169 1173 1177 1181 1185 1191 1197 1203

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M2_1B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2_1B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M2_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M4_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M8_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M16_1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULT_AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULT18X18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULT18X18S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXCY_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXCY_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF5_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF5_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF6_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF6_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF7_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF7_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MUXF8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUF, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUF_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFT_selectIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OBUFTDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRTCPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDDRTRSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDE, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDE_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1205 1207 1209 1211 1213 1217 1221 1223 1225 1227 1229 1231 1233 1235 1237 1239 1241 1243 1245 1247 1249 1251 1253 1259 1263 1271 1275 1279 1285 1287 1291 1295 1301 1305 1311 1313 1315 1319 1323 1327 1331 1333

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OFDI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDT, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDT_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDX, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDX_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFDXI_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPAD, 4, 8, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ORCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PPC405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PULLDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PULLUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X2D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X4D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X4S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X8D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM16X8S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X4S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM32X8S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1D_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM64X2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM128X1S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAM128X1S_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB4_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB4_Sm_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB16_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAMB16_Sm_Sn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1337 1339 1343 1345 1349 1351 1353 1355 1357 1363 1367 1369 1385 1387 1389 1393 1397 1399 1403 1405 1409 1413 1417 1421 1425 1429 1433 1435 1439 1443 1447 1453 1457 1461 1465 1469 1473 1477 1481 1487 1497 1515

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ROC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROCBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM16X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM32X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM64X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM128X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM256X1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOP3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4CE, SR8CE, SR16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4CLE, SR8CLE, SR16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4CLED, SR8CLED, SR16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4RE, SR8RE, SR16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4RLE, SR8RLE, SR16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SR4RLED, SR8RLED, SR16RLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4CE, SRD8CE, SRD16CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4CLE, SRD8CLE, SRD16CLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4CLED, SRD8CLED, SRD16CLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4RE, SRD8RE, SRD16RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4RLE, SRD8RLE, SRD16RLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRD4RLED, SRD8RLED, SRD16RLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRL16E_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRLC16E_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTBUF_architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_SPARTAN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_SPARTAN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_VIRTEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARTUP_VIRTEX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOCBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XNOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XORCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XORCY_D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XORCY_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1557 1559 1561 1563 1565 1567 1569 1571 1573 1577 1581 1587 1591 1595 1601 1605 1609 1613 1617 1621 1625 1629 1633 1637 1641 1645 1647 1651 1655 1657 1659 1663 1667 1671 1673 1675 1677 1679 1685 1691 1693 1695

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Xilinx Unified Libraries


This chapter describes the Unified Libraries and the applicable device architectures for each library. It also briefly discusses the contents of the other chapters, the general naming conventions, and performance issues. This chapter consists of the following major sections. Overview Applicable Architectures Functional Categories Design Elements Schematic Examples Naming Conventions Attributes and Constraints Carry Logic Flip-Flop, Counter, and Register Performance Unconnected Pins

Overview
Xilinx maintains software libraries with thousands of functional design elements (primitives and macros) for different device architectures. New functional elements are assembled with each release of development system software. The catalog of design elements is known as the Unified Libraries. Elements in these libraries are common to all Xilinx device architectures. This unified approach means that you can use your circuit design created with unified library elements across all current Xilinx device architectures that recognize the element you are using. Elements that exist in multiple architectures look and function the same, but their implementations might differ to make them more efficient for a particular architecture. A separate library still exists for each architecture (or architectural group) and common symbols are duplicated in each one, which is necessary for simulation (especially board level) where timing depends on a particular architecture. If you have active designs that were created with former Xilinx library primitives or macros, you may need to change references to the design elements that you were using to reflect the Unified Libraries elements. The Libraries Guide describes the primitive and macro logic elements available in the Unified Libraries for the Xilinx FPGA and CPLD devices. Common logic functions can be implemented with these elements and more complex functions can be built by combining macros and primitives. Several hundred design elements (primitives and

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Xilinx Unified Libraries

macros) are available across multiple device architectures, providing a common base for programmable logic designs. This libraries guide provides a functional selection guide and describes the design elements.

Applicable Architectures
Design elements for the Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex -II, Virtex-II Pro, Virtex-II Pro X, XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II libraries are included in the Xilinx Unified Libraries. Each library supports specific device architectures. For detailed information on the architectural families referenced below and the devices in each, see the current version of The Programmable Logic Data Book (an online version is available from the Xilinx web site, http://support.xilinx.com).

Functional Categories
The functional categories list the available elements in each category along with a brief description of each element and an applicability table identifying which libraries (Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex -II, Virtex-II Pro, Virtex-II Pro X, XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II) contain the element.

Design Elements
Design elements are organized in alphanumeric order, with all numeric suffixes in ascending order. For example, FDR precedes FDRS, and ADD4 precedes ADD8, which precedes ADD16. The following information is provided for each library element, where applicable: Graphic symbol Applicability table (with primitive versus macro identification) Functional description Truth table Schematic for macros VHDL and Verilog instantiation and inference code Commonly used constraints

Schematic Examples
Schematics are included for each library if the implementation differs. Design elements with bussed or multiple I/O pins (2-, 4-, 8-, 16-bit versions) typically include just one schematic -- generally the 8-bit version. When only one schematic is included, implementation of the smaller and larger elements differs only in the number of sections. In cases where an 8-bit version is very large, an appropriate smaller element serves as the schematic example.

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Naming Conventions

Naming Conventions
Examples of the general naming conventions for the unified library elements are shown in the following figures.
Example 1 FUNCTION
Counter, Binary

SIZE
4-Bit

CONTROL PINS
Clear (Asynchronous)
Load

Clock Enable Bi-Directional

CB4CLED
Precedence of Control Pins

Example 2 FUNCTION
Flip-Flop, D-type

SIZE
16-Bit

CONTROL PINS
Reset (Synchronous) Clock Enable

FD16RE
X7764 Precedence of Control Pins

Naming Conventions
AND3B2
Logic Function Number of Inputs Inverting (Bubble) Inputs Number of Inverting Inputs

X4316

Combinatorial Naming Conventions

Attributes and Constraints


Attributes and constraints are instructions placed on components or nets to indicate their placement, implementation, naming, directionality, and so forth. The Constraints Guide provides information on all attributes and constraints.

Carry Logic
The Spartan-II, Spartan-IIE, Virtex, and Virtex-II architectures include dedicated carry logic components.

Spartan-II, Spartan-IIE, Virtex, and Virtex-E


Carry Logic for Spartan-II, Spartan-IIE, Virtex, and Virtex-E is a simple structure associated with each look-up table. The design entry library contains the following dedicated carry logic primitives: MULT_AND, MUXCY, MUXCY_D, MUXCY_L, XORCY, XORCY_D, and XORCY_L. The function performed is determined by their

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connectivity and the contents of the look-up table. For an example of how to use carry logic, see CC8CE, CC16CE. For detailed information on Carry Logic in Virtex and Spartan-II, see The Programmable Logic Data Book available on the Xilinx web site, http:// support.xilinx.com.

Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3


The dedicated carry logic primitives for Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3 are MULT_AND, MUXCY, MUXCY_D, MUXCY_L, XORCY, XORCY_D, and XORCY_L. ORCY can only be used exclusively with Virtex-II, Virtex-II Pro, and Virtex-II Pro X. For detailed information on Carry Logic in Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3, see The Programmable Logic Data Book available on the Xilinx web site, http:/ /support.xilinx.com.

Flip-Flop, Counter, and Register Performance


All counter, register, and storage functions derived from the flip-flops are available in the Configurable Logic Blocks (CLBs). The D flip-flop is the basic building block for all architectures. Differences occur from the availability of asynchronous Clear (CLR) and Preset (PRE) inputs, and the source of the synchronous control signals, such as Clock Enable (CE), Clock (C), Load enable (L), synchronous Reset (R), and synchronous Set (S). The basic flip-flop configuration for each architecture follows. The basic XC9000 flip-flops have both Clear and Preset inputs.
PRE

FDCP
Q

CLR X4397

Virtex and Spartan-II have two basic flip-flop types. One has both Clear and Preset inputs and one has both asynchronous and synchronous control functions.
PRE

D CE C

FDCPE
Q

CLR X4389

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Flip-Flop, Counter, and Register Performance

D CE C

FDRSE

X3732

The asynchronous and synchronous control functions, when used, have a priority that is consistent across all devices and architectures. These inputs can be either activeHigh or active-Low as defined by the macro. The priority, from highest to lowest, is as follows. Asynchronous Clear (CLR) Asynchronous Preset (PRE) Synchronous Set (S) Synchronous Reset (R) Clock Enable (CE)

Note: The asynchronous CLR and PRE inputs, by definition, have priority over all the synchronous control and clock inputs. For FPGA families, the Clock Enable (CE) function is implemented using two different methods in the Xilinx Unified Libraries; both are shown in the following figure. In method 1, CE is implemented by connecting the CE pin of the macro directly to the dedicated Enable Clock (EC) pin of the internal Configurable Logic Block (CLB) flip-flop. This allows one CE per CLB. CE takes precedence over the L, S, and R inputs. All flip-flops with asynchronous clear or preset use this method. In method 2, CE is implemented using function generator logic. This allows two CEs per CLB. CE has the same priority as the L, S, and R inputs. All flip-flops with synchronous set or reset use this method.

The method used in a particular macro is indicated by the inclusion of asynchronous clear, asynchronous preset, synchronous set, or synchronous reset in the macro's description.

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CE

C1 C1 C2
Function Generator

X Function Generator

D C

D EC C

C2 CE

X=(CE * C2)+(CE * C1)

C1 C2
Function Generator

D EC C

C1 C2 CE
Function Generator

D C

Y=(CE * C1)+(CE * C2)

Method 1
CE implemented using dedicated EC pin.

Method 2
CE implemented as a function generator input. X4675

Clock Enable Implementation Methods

Unconnected Pins
Xilinx recommends that you always connect input pins in your designs. This ensures that front end simulation functionally matches back end timing simulation. If an input pin is left unconnected, mapper errors may result. If an output pin is left unconnected in your design, the corresponding function is trimmed. If the component has only one output, the entire component is trimmed. If the component has multiple outputs, the portion that drives the output is trimmed. As an example of the latter case, if the overflow pin (OFL) in an adder macro is unconnected, the logic that generates that term is trimmed, but the rest of the adder is retained (assuming all of the sum outputs are connected).

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Slice Count
This chapter contains the following sections. About Configurable Logic Blocks (CLBs) Slice Count for FPGA Components

About Configurable Logic Blocks (CLBs)


Configurable Logic Blocks (CLBs) implement most of the logic in an FPGA. Each Virtex, Virtex-E and Spartan-II, Spartan-IIE CLB contains two slices. Each Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X CLB contains four slices. In the following table, the numbers for Spartan-II, Spartan-IIE, Virtex, Virtex-E, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X are the number of slices required to implement the component. The Slice Count table lists FPGA design elements in alphanumeric order with the number of CLBs or slices needed for their implementation in each applicable library. Note: This information is for reference only. The actual count could vary, depending upon the switch settings of the implementation tools; for example, the effort level in PAR (Place and Route) or usage of the components with other components. The asterisk for the RAM16X1D and RAM16X1D_1 in the Spartan-3, Virtex-II, VirtexII Pro, and Virtex-II Pro X columns indicates that these design elements consume 1/2 of two slices. The double asterisks for design elements indicate that these primitives cannot be used by themselves. However, there is only one available per slice.

Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name ACC4 ACC8 ACC16 ADD4 ADD8 ADD16 ADSU4 ADSU8 ADSU16 5 9 17 3 5 9 3 5 9 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 6 10 18 3 5 9 3 5 9 5 9 17 3 5 9 3 5 9 6 10 18 3 5 9 3 5 9

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Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name AND2 AND3 AND4 AND5 AND6 AND7 AND8 AND9 AND12 AND16 BRLSHFT4 BRLSHFT8 BSCAN_SPARTAN2 BSCAN_VIRTEX BSCAN_VIRTEX2 BUF BUF4 BUF8 BUF16 BUFCF BUFE BUFE4 BUFE8 BUFE16 BUFG BUFGCE BUFGCE_1 BUFGDLL BUFGMUX BUFGMUX_1 BUFGP BUFT BUFT4 BUFT8 BUFT16 CAPTURE_SPARTAN2 CAPTURE_VIRTEX 1 1 1 1 1 1 2 2 2 2 8 12 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 1 1 1 1 2 2 2 2 4 12 1 1 1 1 1 1 2 2 2 2 8 12 1 1 1 1 1 1 2 2 2 2 4 12 -

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Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name CAPTURE_VIRTEX2 CB2CE CB2CLE CB2CLED CB2RE CB4CE CB4CLE CB4CLED CB4RE CB8CE CB8CLE CB8CLED CB8RE CB16CE CB16CLE CB16CLED CB16RE CC8CE CC8CLE CC8CLED CC8RE CC16CE CC16CLE CC16CLED CC16RE CD4CE CD4CLE CD4RE CD4RLE CJ4CE CJ4RE CJ5CE CJ5RE CJ8CE CJ8RE CLKDLL CLKDLLE 2 3 3 2 3 5 6 3 6 9 12 6 13 18 24 13 8 9 9 9 16 17 17 17 3 5 3 7 2 2 3 3 4 4 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 3 3 3 3 4 5 7 4 7 10 12 7 14 19 25 14 5 9 17 9 9 17 33 17 4 5 4 7 4 4 5 5 4 4 2 3 3 2 3 5 6 3 6 9 12 6 13 18 24 13 8 9 9 9 16 17 17 17 3 5 3 7 2 2 3 3 4 4 3 3 3 3 4 5 7 4 7 10 12 7 14 19 25 14 5 9 17 9 9 17 33 17 4 5 4 7 4 4 5 5 4 4 -

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Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name CLKDLLHF COMP2 COMP4 COMP8 COMP16 COMPM2 COMPM4 COMPM8 COMPM16 COMPMC8 COMPMC16 CR8CE CR16CE D2_4E D3_8E D4_16E DCM DEC_CC4 DEC_CC8 DEC_CC16 DECODE4 DECODE8 DECODE16 DECODE32 DECODE64 FD FD_1 FD4CE FD4RE FD8CE FD8RE FD16CE FD16RE FDC FDC_1 FDCE FDCE_1 1 2 3 6 1 5 11 24 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 2 2 4 4 8 8 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 2 4 9 2 5 13 32 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 4 4 4 4 8 8 1 1 1 1 1 2 3 6 1 5 11 24 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 2 2 4 4 8 8 1 1 1 1 1 2 4 9 2 5 13 32 8 16 8 16 2 4 16 1 1 2 1 2 2 4 8 1 1 4 4 4 4 8 8 1 1 1 1

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Slice Count for FPGA Components

Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name FDCP FDCP_1 FDCPE FDCPE_1 FDDRCPE FDDRRSE FDE FDE_1 FDP FDP_1 FDPE FDPE_1 FDR FDR_1 FDRE FDRE_1 FDRS FDRS_1 FDRSE FDRSE_1 FDS FDS_1 FDSE FDSE_1 FJKC FJKCE FJKP FJKPE FJKRSE FJKSRE FMAP FTC FTCE FTCLE FTCLEX FTP FTPE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Spartan-II, Spartan-IIE Name FTPLE FTRSE FTRSLE FTSRE FTSRLE GND GT_AURORA_n GT_CUSTOM_n GT_ETHERNET_n GT_FIBRE_CHAN_n GT_INFINIBAND_n GT_XAUI_n GT10_AURORA_n GT10_AURORAX_n GT10_CUSTOM_n GT10_INFINIBAND_n GT10_XAUI_n GT10_10GE_n GT10_10GFC_n GT10_OC48_n GT10_OC192_n IBUF IBUF4 IBUF8 IBUF16 IBUF_selectIO IBUFDS IBUFG IBUFG_selectIO IBUFGDS IBUFGDS_DIFF_OUT ICAP_VIRTEX2 IFD IFD_1 IFD4 IFD8 IFD16 1 1 2 1 2 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 1 1 2 1 1 2 1 2 1 1 1 1 2 -

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Slice Count for FPGA Components

Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name IFDDRCPE IFDDRRSE IFDI IFDI_1 IFDX IFDX4 IFDX8 IFDX16 IFDX_1 IFDXI IFDXI_1 ILD ILD_1 ILD4 ILD8 ILD16 ILDI ILDI_1 ILDX ILDX4 ILDX8 ILDX16 ILDX_1 ILDXI ILDXI_1 INV INV4 INV8 INV16 IOBUF IOBUF_selectIO IOPAD IOPAD4 IOPAD8 IOPAD16 IPAD IPAD4 1 1 2 4 8 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 2 4 8 1 1 1 1 1 1 2 4 8 1 1 1 1 1 1 2 4 8 1 1 1 1 -

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Spartan-II, Spartan-IIE Name IPAD8 IPAD16 JTAGPPC KEEPER LD LD_1 LD4 LD8 LD16 LD4CE LD8CE LD16CE LDC LDC_1 LDCE LDCE_1 LDCP LDCP_1 LDCPE LDCPE_1 LDE LDE_1 LDP LDP_1 LDPE LDPE_1 LUT1 LUT2 LUT3 LUT4 LUT1_D LUT2_D LUT3_D LUT4_D LUT1_L LUT2_L LUT3_L 1 1 2 4 8 2 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 4 4 8 4 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 8 2 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 8 4 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Slice Count for FPGA Components

Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name LUT4_L M2_1 M2_1B1 M2_1B2 M2_1E M4_1E M8_1E M16_1E MULT_AND ** MULT18X18 MULT18X18S MUXCY ** MUXCY_D ** MUXCY_L ** MUXF5 ** MUXF5_D ** MUXF5_L ** MUXF6 ** MUXF6_D ** MUXF6_L ** MUXF7 ** MUXF7_D ** MUXF7_L ** MUXF8 ** MUXF8_D ** MUXF8_L ** NAND2 NAND3 NAND4 NAND5 NAND6 NAND7 NAND8 NAND9 NAND12 NAND16 NOR2 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 2 5 1 1 1 1 1 1 2 2 2 2 1

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Spartan-II, Spartan-IIE Name NOR3 NOR4 NOR5 NOR6 NOR7 NOR8 NOR9 NOR12 NOR16 OBUF OBUF4 OBUF8 OBUF16 OBUF_selectIO OBUFDS OBUFE OBUFE4 OBUFE8 OBUFE16 OBUFT OBUFT4 OBUFT8 OBUFT16 OBUFT_selectIO OBUFTDS OFD OFD_1 OFD4 OFD8 OFD16 OFDDRCPE OFDDRRSE OFDDRTCPE OFDDRTRSE OFDE OFDE_1 OFDE4 1 1 1 1 1 2 2 2 2 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 1 1 1 2 2 2 2 1 1 1 1 1 2 2 2 2 1 1 1 1 1 2 2 2 2 -

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Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name OFDE8 OFDE16 OFDI OFDI_I OFDT OFDT_1 OFDT4 OFDT8 OFDT16 OFDX OFDX4 OFDX8 OFDX16 OFDX_1 OFDXI OFDXI_I OPAD OPAD4 OPAD8 OPAD16 OR2 OR3 OR4 OR5 OR6 OR7 OR8 OR9 OR12 OR16 ORCY ** PPC405 PULLDOWN PULLUP RAM16X1D RAM16X1D_1 RAM16X1S 1 1 1 1 1 1 2 2 2 2 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 1 1 1 1 2 2 2 2 2* 2* 1 1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 2 2 2 2 2* 2* 1

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Slice Count

Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name RAM16X1S_1 RAM16X2D RAM16X2S RAM16X4D RAM16X4S RAM16X8D RAM16X8S RAM32X1D RAM32X1D_1 RAM32X1S RAM32X1S_1 RAM32X2S RAM32X4S RAM32X8S RAM64X1D RAM64X1D_1 RAM64X1S RAM64X1S_1 RAM64X2S RAM128X1S RAM128X1S_1 RAMB4_Sn RAMB4_Sm_Sn RAMB16_Sn RAMB16_Sm_Sn ROM16X1 ROM32X1 ROM64X1 ROM128X1 ROM256X1 SOP3 SOP4 SR4CE SR4CLE SR4CLED SR4RE SR4RLE 1 2 2 4 4 8 8 1 1 2 8 1 1 2 1 1 2 3 5 2 3 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 4 2 8 3 16 5 2 2 1 1 2 3 6 4 4 2 2 4 4 4 1 1 2 4 8 1 1 4 3 5 4 3 1 2 2 4 4 8 8 1 1 2 8 1 1 2 1 1 2 3 5 2 3 1 4 2 8 3 16 5 2 2 1 1 2 3 6 4 4 2 2 4 4 4 1 1 2 4 8 1 1 4 3 5 4 3

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Slice Count for FPGA Components

Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name SR4RLED SR8CE SR8CLE SR8CLED SR8RE SR8RLE SR8RLED SR16CE SR16CLE SR16CLED SR16RE SR16RLE SR16RLED SRL16 SRL16_1 SRL16E SRL16E_1 SRLC16 SRLC16_1 SRLC16E SRLC16E_1 STARTUP_SPARTAN2 STARTUP_VIRTEX STARTUP_VIRTEX2 UPAD VCC XNOR2 XNOR3 XNOR4 XNOR5 XNOR6 XNOR7 XNOR8 XNOR9 XOR2 XOR3 XOR4 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 5 4 5 9 4 5 9 8 9 17 8 9 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1

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Slice Count

Slice Count for FPGA Components


Spartan-II, Spartan-IIE Name XOR5 XOR6 XOR7 XOR8 XOR9 XORCY ** XORCY_D ** XORCY_L ** 1 1 1 2 2 Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X

Number of Slices to Implement 1 1 1 2 2 1 1 1 2 2 1 1 1 2 2 -

* The RAM16X1D and RAM16X1D_1 consume 1/2 of two slices. ** These primitives cannot be used by themselves. However, there is only one available per slice.

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Architecture Specific Information


The following sections list the design elements that can be used with supported architectures. Spartan-II and Spartan-IIE Spartan-3 Virtex and Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500/XV/XL CoolRunner XPLA3 CoolRunner-II

To access lists of the constraints associated with each of these architectures, see "Architecture Specific Constraints," in the Xilinx Constraints Guide.

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Architecture Specific Information

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Spartan-II and Spartan-IIE


The following table indicates the supported design elements for Spartan-II and Spartan-IIE. For a complete description of these architectures, see the Product Data Sheets (http://www.xilinx.com/partinfo/databook.htm#spartan). Spartan-II, Spartan-IIE Design Elements
ACC4, 8, 16 AND2-9 BSCAN_SPARTAN2 BUFE, 4, 8, 16 BUFGP CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE CLKDLLHF COMPMC8, 16 D3_8E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDE_1 FDPE FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE IBUF, 4, 8, 16 IFD, 4, 8, 16 IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16 ADD4, 8, 16 AND12, 16 BUF BUFG BUFT, 4, 8, 16 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDP FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE IBUF_selectIO IFD_1 IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1 ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGDLL CAPTURE_SPARTAN2 CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLE, CC16CLE CD4CE CD4RLE CLKDLL, CLKDLLE (Spartan-IIE only) COMPM2, 4, 8, 16 D2_4E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDE FDP_1 FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND IBUFG, IBUFG_selectIO IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ILDXI

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Spartan-II, Spartan-IIE Design Elements


ILDXI_1 IOPAD, 4, 8, 16 LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MUXCY_D MUXF5_D MUXF6_D NAND12, 16 OBUF, 4, 8, 16 OBUFT, 4, 8, 16 OFD_1 OFDI OFDT_1 OFDXI OR2-9 PULLUP RAM16X1S RAM16X2S RAM16X8D RAM32X1S_1 RAM32X8S ROC ROM32X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 STARTBUF_architecture TOCBUF XNOR2-9 XORCY_D INV, 4, 8, 16 IPAD, 4, 8, 16 LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY_L MUXF5_L MUXF6_L NOR2-9 OBUF_selectIO OBUFT_selectIO OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 RAM16X1D RAM16X1S_1 RAM16X4D RAM16X8S RAM32X2S RAMB4_Sn ROCBUF SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E STARTUP_SPARTAN2 UPAD XOR2-9 XORCY_L IOBUF, IOBUF_selectIO KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MUXCY MUXF5 MUXF6 NAND2-9 NOR12, 16 OBUFE, 4, 8, 16 OFD, 4, 8, 16 OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 PULLDOWN RAM16X1D_1 RAM16X2D RAM16X4S RAM32X1S RAM32X4S RAMB4_Sm_Sn ROM16X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 TOC VCC XORCY

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Spartan-3
The table below indicates the supported design elements for Spartan-3. Spartan-3 Design Elements
ACC4, 8, 16 AND2-9 BSCAN_SPARTAN3 BUFG BUFGDLL BUFGP CB2RE, CB4RE, CB8RE, CB16RE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE COMPMC8, 16 D3_8E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDDRCPE FDE_1 FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE IBUFDS IFD, 4, 8, 16 IFDDRRSE IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1 ADD4, 8, 16 AND12, 16 BUF BUFGCE BUFGMUX CAPTURE_SPARTAN3 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CLE, CC16CLE CD4CE CD4RLE COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDDRRSE FDP FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND IBUFG, IBUFG_selectIO IFD_1 IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ILDXI ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGCE_1 BUFGMUX_1 CB2CE, CB4CE, CB8CE, CB16CE CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D2_4E DCM DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDE FDP_1 FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE IBUF, 4, 8, 16 IBUFGDS IFDDRCPE IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16

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Spartan-3 Design Elements


ILDXI_1 IOBUFDS LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY MUXF5 MUXF6 MUXF7 MUXF8 NOR2-9 OBUF_selectIO OBUFTDS OFDDRCPE OFDDRTRSE OFDI OFDT_1 OFDXI OR2-9 PULLUP RAM16X1S RAM16X4S RAM32X1S_1 RAM64X1S_1 ROC ROM32X1 ROM256X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 SRLC16 SRLC16E_1 TOC INV, 4, 8, 16 KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MULT18X18 MUXCY_D MUXF5_D MUXF6_D MUXF7_D NAND2-9 NOR12, 16 OBUFDS OFD, 4, 8, 16 OFDDRRSE OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 RAM16X1D RAM16X1S_1 RAM16X8S RAM32X2S RAMB16_Sn ROCBUF ROM64X1 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E SRLC16_1 STARTBUF_architecture TOCBUF IOBUF, IOBUF_selectIO LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MULT18X18S MUXCY_L MUXF5_L MUXF6_L MUXF7_L NAND12, 16 OBUF, 4, 8, 16 OBUFT, 4, 8, 16 OFD_1 OFDDRTCPE OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 PULLDOWN RAM16X1D_1 RAM16X2S RAM32X1S RAM64X1S RAMB16_Sm_Sn ROM16X1 ROM128X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 SRLC16E STARTUP_SPARTAN3 VCC

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Spartan-3 Design Elements


XNOR2-9 XORCY_D XOR2-9 XORCY_L XORCY

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Virtex and Virtex-E


The table below indicates the supported design elements for Virtex and Virtex-E. For a complete description, see the Product Data Sheets (http://www.xilinx.com/partinfo/ databook.htm#virtex). Virtex, Virtex-E Design Elements
ACC4, 8, 16 AND2-9 BSCAN_VIRTEX BUFE, 4, 8, 16 BUFGP CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE CLKDLLE COMPM2, 4, 8, 16 D2_4E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDE FDP_1 FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND IBUFG, IBUFG_selectIO IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ADD4, 8, 16 AND12, 16 BUF BUFG BUFT, 4, 8, 16 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE CLKDLLHF COMPMC8, 16 D3_8E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDE_1 FDPE FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE IBUF, 4, 8, 16 IFD, 4, 8, 16 IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16 ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGDLL CAPTURE_VIRTEX CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLE, CC16CLE CD4CE CD4RLE CLKDLL COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDP FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE IBUF_selectIO IFD_1 IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1

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Virtex, Virtex-E Design Elements


ILDXI IOBUF, IOBUF_selectIO KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MUXCY MUXF5 MUXF6 NAND2-9 NOR12, 16 OBUFE, 4, 8, 16 OFD, 4, 8, 16 OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 PULLDOWN RAM16X1D_1 RAM16X2D RAM16X4S RAM32X1S RAM32X4S RAMB4_Sm_Sn ROM16X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 TOC VCC XORCY ILDXI_1 IOPAD, 4, 8, 16 LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MUXCY_D MUXF5_D MUXF6_D NAND12, 16 OBUF, 4, 8, 16 OBUFT, 4, 8, 16 OFD_1 OFDI OFDT_1 OFDXI OR2-9 PULLUP RAM16X1S RAM16X2S RAM16X8D RAM32X1S_1 RAM32X8S ROC ROM32X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 STARTBUF_architecture TOCBUF XNOR2-9 XORCY_D INV, 4, 8, 16 IPAD, 4, 8, 16 LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY_L MUXF5_L MUXF6_L NOR2-9 OBUF_selectIO OBUFT_selectIO OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 RAM16X1D RAM16X1S_1 RAM16X4D RAM16X8S RAM32X2S RAMB4_Sn ROCBUF SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E STARTUP_VIRTEX UPAD XOR2-9 XORCY_L

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Virtex-II, Virtex-II Pro, Virtex-II Pro X


The table below indicates the supported design elements for Virtex-II, Virtex-II Pro, and Virtex-II Pro X. For a complete description of Virtex-II, see the Product Data Sheets (http://www.xilinx.com/partinfo/databook.htm#vtwo). Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements
ACC4, 8, 16 AND2-9 BSCAN_VIRTEX2 BUFE, 4, 8, 16 BUFGCE_1 BUFGMUX_1 CAPTURE_VIRTEX2 CB2CLED, CB4CLED, CB8CLED, CB16CLED CC8CLE, CC16CLE CD4CE CD4RLE COMP2, 4, 8, 16 CR8CE, CR16CE D4_16E DECODE4, 8, 16 FD_1 FDC FDCE_1 FDCPE FDDRRSE FDP FDPE_1 FDRE FDRS_1 FDS FDSE_1 FJKP FJKSRE FTCE FTP FTRSE FTSRLE GT_CUSTOM (Virtex-II Pro only) GT10_AURORAX_n (Virtex-II Pro X only) ADD4, 8, 16 AND12, 16 BUF BUFG BUFGDLL BUFGP CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CC8CLED, CC16CLED CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D2_4E DCM DECODE32, 64 FD4CE, FD8CE, FD16CE FDC_1 FDCP FDCPE_1 FDE FDP_1 FDR FDRE_1 FDRSE FDS_1 FJKC FJKPE FMAP FTCLE FTPE FTRSLE GND GT_ETHERNET_n (Virtex-II Pro only) GT10_CUSTOM (Virtex-II Pro X only) ADSU4, 8, 16 BRLSHFT4, 8 BUFCF BUFGCE BUFGMUX BUFT, 4, 8, 16 CB2CLE, CB4CLE, CB8CLE, CB16CLE CC8CE, CC16CE CC8RE, CC16RE CD4RE CJ4RE, CJ5RE, CJ8RE COMPMC8, 16 D3_8E DEC_CC4, 8, 16 FD FD4RE, FD8RE, FD16RE FDCE FDCP_1 FDDRCPE FDE_1 FDPE FDR_1 FDRS FDRSE_1 FDSE FJKCE FJKRSE FTC FTCLEX FTPLE FTSRE GT_AURORA_n (Virtex-II Pro only) GT_FIBRE_CHAN_n (Virtex-II Pro only) GT10_AURORA_n (Virtex-II Pro X only) GT10_INFINIBAND_n (Virtex-II Pro X only)

GT_INFINIBAND_n (Virtex-II Pro only) GT_XAUI_n (Virtex-II Pro only)

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Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements


GT10_XAUI_n (Virtex-II Pro X only) GT10_OC48_n (Virtex-II Pro X only) IBUF_selectIO IBUFGDS IFD, 4, 8, 16 IFDDRRSE IFDX, 4, 8, 16 IFDXI_1 ILDI ILDX_1 INV, 4, 8, 16 IOPAD, 4, 8, 16 KEEPER LD4, 8, 16 LDCE LDCP LDCPE_1 LDP LDPE_1 LUT1_L, LUT2_L, LUT3_L, LUT4_L M2_1B2 M8_1E MULT18X18 MUXCY_D MUXF5_D MUXF6_D MUXF7_D NAND2-9 NOR2-9 OBUF_selectIO OBUFT, 4, 8, 16 OFD, 4, 8, 16 OFDDRRSE OFDE, 4, 8, 16 OFDI_1 OFDX, 4, 8, 16 OFDXI_1 OR12, 16 PULLDOWN RAM16X1D_1 GT10_10GE_n (Virtex-II Pro X only) GT10_OC192_n (Virtex-II Pro X only) IBUFDS IBUFGDS_DIFF_OUT IFD_1 IFDI IFDX_1 ILD, 4, 8, 16 ILDI_1 ILDXI IOBUF, IOBUF_selectIO IPAD, 4, 8, 16 LD LDC LDCE_1 LDCP_1 LDE LDP_1 LUT1, 2, 3, 4 M2_1 M2_1E M16_1E MULT18X18S MUXCY_L MUXF5_L MUXF6_L MUXF7_L NAND12, 16 NOR12, 16 OBUFDS OBUFT_selectIO OFD_1 OFDDRTCPE OFDE_1 OFDT, 4, 8, 16 OFDX_1 OPAD, 4, 8, 16 ORCY PULLUP RAM16X1S OBUF, 4, 8, 16 OBUFE, 4, 8, 16 OBUFTDS OFDDRCPE OFDDRTRSE OFDI OFDT_1 OFDXI OR2-9 PPC405 (Virtex-II Pro only) RAM16X1D RAM16X1S_1 GT10_10GFC_n (Virtex-II Pro X only) IBUF, 4, 8, 16 IBUFG, IBUFG_selectIO ICAP_VIRTEX2 IFDDRCPE IFDI_1 IFDXI ILD_1 ILDX, 4, 8, 16 ILDXI_1 IOBUFDS JTAGPPC (Virtex-II Pro only) LD_1 LDC_1 LD4CE, LD8CE, LD16CE LDCPE LDE_1 LDPE LUT1_D, LUT2_D, LUT3_D, LUT4_D M2_1B1 M4_1E MULT_AND MUXCY MUXF5 MUXF6 MUXF7 MUXF8

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Virtex-II, Virtex-II Pro, Virtex-II Pro X Design Elements


RAM16X2D RAM16X4S RAM32X1D RAM32X1S_1 RAM32X8S RAM64X1S RAM128X1S RAMB16_Sm_Sn ROM16X1 ROM128X1 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRL16 SRL16E_1 SRLC16E STARTUP_VIRTEX2 UPAD XOR2-9 XORCY_L RAM16X2S RAM16X8D RAM32X1D_1 RAM32X2S RAM64X1D RAM64X1S_1 RAM128X1S_1 ROC ROM32X1 ROM256X1 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRL16_1 SRLC16 SRLC16E_1 TOC VCC XORCY RAM16X4D RAM16X8S RAM32X1S RAM32X4S RAM64X1D_1 RAM64X2S RAMB16_Sn ROCBUF ROM64X1 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRL16E SRLC16_1 STARTBUF_architecture TOCBUF XNOR2-9 XORCY_D

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XC9500/XV/XL
The table below indicates the supported design elements for XC95000/XV/XL. For a complete description, see the Product Data Sheets (http://www.xilinx.com/partinfo/ databook.htm#cpld). XC9500/XV/XL Design Elements
ACC1 ADD4, 8, 16 AND2-9 BUF4, 8, 16 BUFGSR CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CB2X2, CB4X2, CB8X2, CB16X2 CD4RE CJ4RE, CJ5RE, CJ8RE CR8CE, CR16CE D4_16E FD4CE, FD8CE, FD16CE FDCE FDP FDRE FDS FDSRE FJKCP FJKPE FTC FTCP FTDCP FTPLE FTSRE IBUF, 4, 8, 16 IPAD, 4, 8, 16 LDC M2_1 M2_1E M16_1E OBUF, 4, 8, 16 OPAD, 4, 8, 16 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE VCC ACC4, 8, 16 ADSU1 BRLSHFT4, 8 BUFE, 4, 8, 16 BUFGTS CB2CLE, CB4CLE, CB8CLE, CB16CLE CB2RLE, CB4RLE, CB8RLE, CB16RLE CD4CE CD4RLE COMP2, 4, 8, 16 D2_4E FD FD4RE, FD8RE, FD16RE FDCP FDPE FDRS FDSE FJKC FJKCPE FJKRSE FTCE FTCPE FTP FTRSE FTSRLE INV, 4, 8, 16 LD LDCP M2_1B1 M4_1E NAND2-9 OBUFE, 4, 8, 16 OR2-9 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE XNOR2-9 ADD1 ADSU4, 8, 16 BUF BUFG BUFT, 4, 8, 16 CB2CLED, CB4CLED, CB8CLED, CB16CLED CB2X1, CB4X1, CB8X1, CB16X1 CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D3_8E FD4, 8, 16 FDC FDCPE FDR FDRSE FDSR FJKCE FJKP FJKSRE FTCLE FTCPLE FTPE FTRSLE GND IOPAD, 4, 8, 16 LD4, 8, 16 LDP M2_1B2 M8_1E NOR2-9 OBUFT, 4, 8, 16 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED XOR2-9

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CoolRunner XPLA3
The table below indicates the supported design elements for CoolRunner XPLA3. For a complete description, see the Product Data Sheets (http://www.xilinx.com/ partinfo/databook.htm#coolrunner). CoolRunner XPLA3 Design Elements
ACC1 ADD4, 8, 16 AND2-9 BUF4, 8, 16 BUFT, 4, 8, 16 CB2CLED, CB4CLED, CB8CLED, CB16CLED CB2X1, CB4X1, CB8X1, CB16X1 CD4CLE CJ4CE, CJ5CE, CJ8CE COMPM2, 4, 8, 16 D3_8E FD4, 8, 16 FDC FDCPE FDR FDRSE FDSR FJKCE FJKP FJKSRE FTCLE FTCPLE FTPE FTRSLE GND IOPAD, 4, 8, 16 LD4, 8, 16 LDP M2_1B2 M8_1E NOR2-9 OBUFT, 4, 8, 16 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED XOR2-9 ACC4, 8, 16 ADSU1 BRLSHFT4, 8 BUFE, 4, 8, 16 CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CB2X2, CB4X2, CB8X2, CB16X2 CD4RE CJ4RE, CJ5RE, CJ8RE CR8CE, CR16CE D4_16E FD4CE, FD8CE, FD16CE FDCE FDP FDRE FDS FDSRE FJKCP FJKPE FTC FTCP FTDCP FTPLE FTSRE IBUF, 4, 8, 16 IPAD, 4, 8, 16 LDC M2_1 M2_1E M16_1E OBUF, 4, 8, 16 OPAD, 4, 8, 16 SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE VCC ADD1 ADSU4, 8, 16 BUF BUFG CB2CLE, CB4CLE, CB8CLE, CB16CLE CB2RLE, CB4RLE, CB8RLE, CB16RLE CD4CE CD4RLE COMP2, 4, 8, 16 D2_4E FD FD4RE, FD8RE, FD16RE FDCP FDPE FDRS FDSE FJKC FJKCPE FJKRSE FTCE FTCPE FTP FTRSE FTSRLE INV, 4, 8, 16 LD LDCP M2_1B1 M4_1E NAND2-9 OBUFE, 4, 8, 16 OR2-9 SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE XNOR2-9

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CoolRunner-II
The table below indicates the supported design elements for CoolRunner-II. For a complete description of CoolRunner-II, see the Product Data Sheets (http:// www.xilinx.com/partinfo/databook.htm#cooltwo). CoolRunner-II Design Elements
ACC1 ADD4, 8, 16 AND2-9 BUF4, 8, 16 BUFGTS CB2CLED, CB4CLED, CB8CLED, CB16CLED CB2X1, CB4X1, CB8X1, CB16X1 CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE CD4CE CD4RLE CDD4RE CJ4RE, CJ5RE, CJ8RE CLK_DIV2,4,6,8,10,12,14,16 CLK_DIV2,4,6,8,10,12,14,16SD CR8CE, CR16CE D3_8E FD4, 8, 16 FDC FDCPE FDD4CE, FDD8CE, FDD16CE FDDCE FDDP FDDRE FDDS FDDSRE FDR FDRSE FDSR FJKCE FJKP FJKSRE FTCLE FTCPLE FTDCLEX ACC4, 8, 16 ADSU1 BRLSHFT4, 8 BUFG CB2CE, CB4CE, CB8CE, CB16CE CB2RE, CB4RE, CB8RE, CB16RE CB2X2, CB4X2, CB8X2, CB16X2 CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED CBD2X1, CBD4X1, CBD8X1, CBD16X1 CD4CLE CDD4CE CDD4RLE CJD4CE, CJD5CE, CJD8CE CLK_DIV2,4,6,8,10,12,14,16R COMP2, 4, 8, 16 CRD8CE, CRD16CE D4_16E FD4CE, FD8CE, FD16CE FDCE FDD FDD4RE, FDD8RE, FDD16RE FDDCP FDDPE FDDRS FDDSE FDP FDRE FDS FDSRE FJKCP FJKPE FTC FTCP FTDCE FTDCP ADD1 ADSU4, 8, 16 BUF BUFGSR CB2CLE, CB4CLE, CB8CLE, CB16CLE CB2RLE, CB4RLE, CB8RLE, CB16RLE CBD2CE, CBD4CE, CBD8CE, CBD16CE CBD2RE, CBD4RE, CBD8RE, CBD16RE CBD2X2, CBD4X2, CBD8X2, CBD16X2 CD4RE CDD4CLE CJ4CE, CJ5CE, CJ8CE CJD4RE, CJD5RE, CJD8RE CLK_DIV2,4,6,8,10,12,14,16RSD COMPM2, 4, 8, 16 D2_4E FD FD4RE, FD8RE, FD16RE FDCP FDD4,8,16 FDDC FDDCPE FDDR FDDRSE FDDSR FDPE FDRS FDSE FJKC FJKCPE FJKRSE FTCE FTCPE FTDCLE FTDRSE

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FTDRSLE FTPLE FTSRE IBUF, 4, 8, 16 IPAD, 4, 8, 16 LD4, 8, 16 LDG M2_1 M2_1E M16_1E OBUF, 4, 8, 16 OPAD, 4, 8, 16 PULLUP SR4CLE, SR8CLE, SR16CLE SR4RLE, SR8RLE, SR16RLE SRD4CLE, SRD8CLE, SRD16CLE SRD4RLE, SRD8RLE, SRD16RLE XNOR2-9 FTP FTRSE FTSRLE INV, 4, 8, 16 KEEPER LDC LDG4, 8, 16 M2_1B1 M4_1E NAND2-9 OBUFE, 4, 8, 16 OR2-9 SOP3-4 SR4CLED, SR8CLED, SR16CLED SR4RLED, SR8RLED, SR16RLED SRD4CLED, SRD8CLED, SRD16CLED SRD4RLED, SRD8RLED, SRD16RLED XOR2-9 FTPE FTRSLE GND IOPAD, 4, 8, 16 LD LDCP LDP M2_1B2 M8_1E NOR2-9 OBUFT, 4, 8, 16 PULLDOWN SR4CE, SR8CE, SR16CE SR4RE, SR8RE, SR16RE SRD4CE, SRD8CE, SRD16CE SRD4RE, SRD8RE, SRD16RE VCC

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Functional Categories
This section categorizes, by function, the logic elements that are described in detail in the Design Elements sections. Each category is briefly described. Tables under each category identify all the available elements for the function and indicate which architectures are supported by each.
Arithmetic Functions Buffers Comparators Counters Decoders Edge Decoders Flip-Flops General Input Latches Input/Output Flip-Flops Input/Output Functions Latches Logic Primitives Map Elements Memory Elements Multiplexers Shifters Shift Registers

Elements are listed in alphanumeric order under each category. See the Xilinx Unified Libraries chapter for information on the specific device families that use each library. "No" column means that the element does not apply. The Xilinx libraries contain three types of elements. Primitives are basic logical elements such as AND2 and OR2 gates. Soft macros are schematics made by combining primitives and sometimes other soft macros. Relationally placed macros (RPMs) are soft macros that contain relative location constraint (RLOC) information, carry logic symbols, and FMAP symbols, where appropriate.

The last item mentioned above, RPMs, applies only to FPGA families. The relationally placed macro (RPM) library uses RLOC constraints to define the order and structure of the underlying design primitives. Because these macros are built upon standard schematic parts, they do not have to be translated before simulation. The components that are implemented as RPMs are listed in the Slice Count section. Designs created with RPMs can be functionally simulated. RPMs can, but need not, include all the following elements. FMAPs and CLB-grouping attributes to control mapping. FMAPs have pin-lock attributes, which allow better control over routing. Relative location (RLOC) constraints to provide placement structure. They allow positioning of elements relative to each other. Carry logic primitive symbols.

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The RPM library offers the functionality and precision of the hard macro library with added flexibility. You can optimize RPMs and merge other logic within them. The elements in the RPM library allow you to access carry logic easily and to control mapping and block placement. Because RPMs are a superset of ordinary macros, you can design them in the normal design entry environment. They can include any primitive logic. The macro logic is fully visible to you and can be easily backannotated with timing information.

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Arithmetic Functions
There are three types of arithmetic functions: accumulators (ACC), adders (ADD), and adder/subtracters (ADSU). With an ADSU, either unsigned binary or twoscomplement operations cause an overflow. If the result crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-out boundary, a carry-out is generated. The following figure shows the ADSU carry-out and overflow boundaries.
Overflow
-127
D

127 127
TW

128

NE

OS

SIG

CO

UN

ED BINAR Y IGN

E N T OR

MPL EMENT O R

SIGN
ED BIN

LEM

AR

MP

NS

CO

SI

0 0

-1

Carry-Out
X4720

ADSU Carry-Out and Overflow Boundaries


Design Element ACC1 Description 1-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 4-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 8-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 16-Bit Loadable Cascadable Accumulator with Carry-In, CarryOut, and Synchronous Reset 1-Bit Full Adder with Carry-In and Carry-Out 4-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow 8-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow 16-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow 1-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow 8-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow Spartan-II, IIE No No Spartan3 Virtex, E No Virtex II, Pro, Pro X No XC9500/XV/ XL Macro CR XPLA3 Macro CR-II Macro

ACC4

Macro

Macro

Macro

ACC8

Macro

Macro

Macro

ACC16

Macro

Macro

Macro

ADD1 ADD4 ADD8 ADD16 ADSU1 ADSU4

No Macro Macro Macro No Macro

No Macro Macro Macro No Macro

No Macro Macro Macro No Macro

ADSU8

Macro

Macro

Macro

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ED

255

TW

Macro

Macro

Macro

Macro

Macro

Macro

Macro

Macro

Macro

Macro

Macro

Macro

No Macro Macro Macro No Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro

Macro

Macro

Macro

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Functional Categories

Design Element ADSU16

Description 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow 18 x 18 Signed Multiplier 18 x 18 Signed Multiplier -- Registered Version

Spartan-II, IIE Macro

Spartan3 Macro

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

MULT18X18 MULT18X18S

No No

Primitive Primitive

No No

Primitive Primitive

No No

No No

No No

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Buffers
The buffers in this section route high fanout signals, 3-state signals, and clocks inside a PLD device. The Input/Output Functions section covers off-chip interfaces.
Design Element BUF BUF4 BUF8 BUF16 BUFCF BUFE BUFE4 BUFE8 BUFE16 BUFG BUFGCE Description General Purpose Buffer 4-Bit General Purpose Buffer 8-Bit General Purpose Buffer 16-Bit General Purpose Buffer Fast Connect Buffer Internal 3-State Buffer with Active High Enable. Internal 3-State Buffer with Active High Enable. Internal 3-State Buffer with Active High Enable. Internal 3-State Buffer with Active High Enable. Global Clock Buffer Global Clock MUX with Clock Enable and Output State 0 Global Clock MUX Buffer with Clock Enable and Output State 1 Clock Delay Locked Loop Buffer Global Clock MUX Buffer with Output State 0 Global Clock MUX with Output State 1 Primary Global Buffer for Driving Clocks or Longlines (Four per PLD Device) Global Set/Reset Input Buffer Global 3-State Input Buffer Internal 3-State Buffer with Active-Low Enable. Internal 3-State Buffer with Active-Low Enable. Internal 3-State Buffer with Active-Low Enable. Internal 3-State Buffer with Active-Low Enable. Spartan-II, IIE Primitive No No No Primitive Primitive Macro Macro Macro Primitive No Spartan3 Primitive No No No Primitive No No No No Primitive Primitive Virtex, E Primitive No No No Primitive Primitive Macro Macro Macro Primitive No Virtex II, Pro, Pro X Primitive No No No Primitive Primitive Macro Macro Macro Primitive Primitive XC9500 /XV/XL Primitive Macro Macro Macro No Primitive Macrob Macroc Macrod Primitive No
a

CR XPLA3 Primitive Macro Macro Macro No No No No No Primitive No

CR-II Primitive Macro Macro Macro No No No No No Primitive No

BUFGCE_1

No

Primitive

No

Primitive

No

No

No

BUFGDLL BUFGMUX BUFGMUX_1 BUFGP

Primitive No No Primitive

Primitive Primitive Primitive Primitive

Primitive No No Primitive

Primitive Primitive Primitive Primitive

No No No No

No No No No

No No No No

BUFGSR BUFGTS BUFT BUFT4 BUFT8 BUFT16

No No Primitive Macro Macro Macro

No No No No No No

No No Primitive Macro Macro Macro

No No Primitive Macro Macro Macro

Primitive Primitive Primitivee Macrof Macrog Macroh

Primitive Primitive No No No No

Primitive Primitive No No No No

a.Not supported for XC9500XL and XC9500XV devices. b.Not supported for XC9500XL and XC9500XV devices. c.Not supported for XC9500XL and XC9500XV devices. d.Not supported for XC9500XL and XC9500XV devices. e.Not supported for XC9500XL and XC9500XV devices. f.Not supported for XC9500XL and XC9500XV devices.

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g.Not supported for XC9500XL and XC9500XV devices. h.Not supported for XC9500XL and XC9500XV devices.

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Comparators
Following is a list of comparators.
Design Element COMP2 COMP4 COMP8 COMP16 COMPM2 COMPM4 COMPM8 COMPM16 COMPMC8 COMPMC16 Description 2-Bit Identity Comparator 4-Bit Identity Comparator 8-Bit Identity Comparator 16-Bit Identity Comparator 2-Bit Magnitude Comparator 4-Bit Magnitude Comparator 8-Bit Magnitude Comparator Spartan-II, IIE Macro Macro Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro XC9500/XV/ XL Macro Macro Macro Macro Macro Macro Macro Macro No No CR XPLA3 Macro Macro Macrob Macro Macro Macro Macro Macro No No CR-II Macro Macro Macro Macro Macro Macro Macro Macro No No

16-Bit Magnitude Comparator Macro 8-Bit Magnitude Comparator Macro

16-Bit Magnitude Comparator Macro

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Counters
There are six types of counters with various synchronous and asynchronous inputs. The name of the counter defines the modulo or bit size, the counter type, and which control functions are included. The counter naming convention is shown in the following figure.

CB16CLED
Counter Binary (B) BCD (D) Binary, Carry Logic (C) Johnson (J) Ripple (R) Modulo (Bit Size) Synchronous Reset (R) Asynchronous Clear (C) Loadable Clock Enable Directional

X4577

Counter Naming Convention A carry-lookahead design accommodates large counters without extra gating. On TTL 7400-type counters with trickle clock enable (ENT), parallel clock enable (ENP), and ripple carry-out (RCO), both the ENT and ENP inputs must be High to count. ENT is propagated forward to enable RCO, which produces a High output with the approximate duration of the QA output. The following figure illustrates a carrylookahead design.

RCO ENP ENT

RCO ENP ENT

Vcc ENP ENT

RCO

Vcc RCO ENP CE ENT

X4719

Carry-Lookahead Design

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The RCO output of the first stage of the ripple carry is connected to the ENP input of the second stage and all subsequent stages. The RCO output of the second stage and all subsequent stages is connected to the ENT input of the next stage. The ENT of the second stage is always enabled/tied to VCC. CE is always connected to the ENT input of the first stage. This cascading method allows the first stage of the ripple carry to be built as a prescaler. In other words, the first stage is built to count very fast. Note: For counters, do not use TC (or any other gated signal) as a clock. Possible glitches may not always allow for a proper setup time when using gated signals.
Design Element CB2CE Description 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 4-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset Spartan-II, IIE Macro Spartan-3 Macro Virtex, E Macro Virtex II, Pro, Pro X Macro XC9500/XV/ XL Macro CR XPLA3 Macro CR-II Macro

CB4CE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB8CE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB16CE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CB2CLE

No

No

No

No

Macro

Macro

Macro

CB4CLE

No

No

No

No

Macro

Macro

Macro

CB8CLE

No

No

No

No

Macro

Macro

Macro

CB16CLE

No

No

No

No

Macro

Macro

Macro

CB2CLED

No

No

No

No

Macro

Macro

Macro

CB4CLED

No

No

No

No

Macro

Macro

Macro

CB8CLED

No

No

No

No

Macro

Macro

Macro

CB16CLED

No

No

No

No

Macro

Macro

Macro

CB2RE

Macro

Macro

Macro

Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

CB4RE

Macro

Macro

Macro

Macro

CB8RE

Macro

Macro

Macro

Macro

CB16RE

Macro

Macro

Macro

Macro

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Design Element CB2RLE

Description 2-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Synchronous Reset 2-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asyn-chronous Clear 2-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 4-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchro-nous Reset 2-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear

Spartan-II, IIE No

Spartan-3 No

Virtex, E No

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

CB4RLE

No

No

No

Macro

Macro

Macro

Macro

CB8RLE

No

No

No

Macro

Macro

Macro

Macro

CB16RLE

No

No

No

Macro

Macro

Macro

Macro

CB2X1

No

No

No

Macro

Macro

Macro

Macro

CB4X1

No

No

No

Macro

Macro

Macro

Macro

CB8X1

No

No

No

Macro

Macro

Macro

Macro

CB16X1

No

No

No

Macro

Macro

Macro

Macro

CB2X2

No

No

No

Macro

Macro

Macro

Macro

CB4X2

No

No

No

Macro

Macro

Macro

Macro

CB8X2

No

No

No

Macro

Macro

Macro

Macro

CB16X2

No

No

No

Macro

Macro

Macro

Macro

CBD2CE

No

No

No

No

No

No

Macro

CBD4CE

No

No

No

No

No

No

Macro

CBD8CE

No

No

No

No

No

No

Macro

CBD16CE

No

No

No

No

No

No

Macro

CBD2CLE

No

No

No

No

No

No

Macro

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Design Element CBD4CLE

Description 4-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 16-Bit Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 2-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear

Spartan-II, IIE No

Spartan-3 No

Virtex, E No

Virtex II, Pro, Pro X No

XC9500/XV/ XL No

CR XPLA3 No

CR-II Macro

CBD8CLE

No

No

No

No

No

No

Macro

CBD16CLE

No

No

No

No

No

No

Macro

CBD2CLED

No

No

No

No

No

No

Macro

CBD4CLED

No

No

No

No

No

No

Macro

CBD8CLED

No

No

No

No

No

No

Macro

CBD16CLED

No

No

No

No

No

No

Macro

CBD2RE

No

No

No

No

No

No

Macro

CBD4RE

No

No

No

No

No

No

Macro

CBD8RE

No

No

No

No

No

No

Macro

CBD16RE

No

No

No

No

No

No

Macro

CBD2RLE

No

No

No

No

No

No

Macro

CBD4RLE

No

No

No

No

No

No

Macro

CBD8RLE

No

No

No

No

No

No

Macro

CBD16RLE

No

No

No

No

No

No

Macro

CBD2X1

No

No

No

No

No

No

Macro

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Functional Categories

Design Element CBD4X1

Description 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Asynchronous Clear 2-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counter with Clock Enable and Synchronous Reset 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear

Spartan-II, IIE No

Spartan-3 No

Virtex, E No

Virtex II, Pro, Pro X No

XC9500/XV/ XL No

CR XPLA3 No

CR-II Macro

CBD8X1

No

No

No

No

No

No

Macro

CBD16X1

No

No

No

No

No

No

Macro

CBD2X2

No

No

No

No

No

No

Macro

CBD4X2

No

No

No

No

No

No

Macro

CBD8X2

No

No

No

No

No

No

Macro

CBD16X2

No

No

No

No

No

No

Macro

CC8CE

Macro

Macro

Macro

Macro

No

No

No

CC16CE

Macro

Macro

Macro

Macro

No

No

No

CC8CLE

Macro

Macro

Macro

Macro

No

No

No

CC16CLE

Macro

Macro

Macro

Macro

No

No

No

CC8CLED

Macro

Macro

Macro

Macro

No

No

No

CC16CLED

Macro

Macro

Macro

Macro

No

No

No

CC8RE

Macro

Macro

Macro

Macro

No

No

No

CC16RE

Macro

Macro

Macro

Macro

No

No

No

CD4CE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CD4CLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CDD4CE

No

No

No

No

No

No

Macro

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Design Element CD4RE

Description 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable BCD Counter with Clock Enable And Synchronous Reset 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear 4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset 5-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset 8-Bit Dual Edge Triggered Johnson Counter with Clock Enable and Synchronous Reset 4-Bit Johnson Counter with Clock Enable and Synchronous Reset 5-Bit Johnson Counter with Clock Enable and Synchronous Reset 8-Bit Johnson Counter with Clock Enable and Synchronous Reset 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear

Spartan-II, IIE Macro

Spartan-3 Macro

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

CD4RLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CDD4CLE

No

No

No

No

No

No

Macro

CDD4RE

No

No

No

No

No

No

Macro

CDD4RLE

No

No

No

No

No

No

Macro

CD4RE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CD4RLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

CJ4CE CJ5CE CJ8CE CJD4CE

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro Macro

CJD5CE

No

No

No

No

No

No

Macro

CJD8CE

No

No

No

No

No

No

Macro

CJD4RE

No

No

No

No

No

No

Macro

CJD5RE

No

No

No

No

No

No

Macro

CJD8RE

No

No

No

No

No

No

Macro

CJ4RE CJ5RE CJ8RE CR8CE

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

CR16CE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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69

Functional Categories

Design Element CRD8CE

Description 8-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear 16-Bit Dual-Edge Triggered Binary Ripple Counter with Clock Enable and Asynchronous Clear

Spartan-II, IIE No

Spartan-3 No

Virtex, E No

Virtex II, Pro, Pro X No

XC9500/XV/ XL No

CR XPLA3 No

CR-II Macro

CRD16CE

No

No

No

No

No

No

Macro

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Decoders
Decoder names, shown in the following figure, indicate the number of inputs and outputs and whether or not an enable is available. Decoders with an enable can be used as multiplexers.

D2_4E
Decoder Number of Inputs Number of Outputs Output Enable

X4619

Decoder Naming Convention


Design Element D2_4E D3_8E D4_16E DEC_CC4 DEC_CC8 DEC_CC16 Description 2- to 4-Line Decoder/ Demultiplexer with Enable 3- to 8-Line Decoder/ Demultiplexer with Enable 4- to 16-Line Decoder/ Demultiplexer with Enable 4-Bit Active Low Decoder 8-Bit Active Low Decoder 16-Bit Active Low Decoder Spartan-II, IIE Macro Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro XC9500/XV/ XL Macro Macro Macro No No No CR XPLA3 Macro Macro Macro No No No CR-II Macro Macro Macro No No No

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Functional Categories

Edge Decoders
Edge decoders are open-drain wired AND gates that are available in different bit sizes.
Design Element DECODE4 DECODE8 DECODE16 DECODE32 DECODE64 Description 4-Bit Active-Low Decoder 8-Bit Active-Low Decoder 16-Bit Active-Low Decoder 32-Bit Active-Low Decoder 64-Bit Active-Low Decoder Spartan-II, IIE Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro No No No No No XC9500/XV/ XL CR XPLA3 No No No No No CR-II No No No No No

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Flip-Flops
There are three types of flip-flops (D, J-K, toggle) with various synchronous and asynchronous inputs. Some are available with inverted clock inputs and/or the ability to set in response to global set/reset rather than reset. The naming convention shown in the following figure provides a description for each flip-flop. D-type flip-flops are available in multiples of up to 16 in one macro.

FDPE_1
Flip-Flop D-Type (D) JK-Type (JK) Toggle-Type (T) Asynchronous Preset (P) Asynchronous Clear (C) Synchronous Set (S) Synchronous Reset (R) Clock Enable Inverted Clock

X4579

Design Element FD FD_1 FD4 FD8 FD16 FD4CE FD8CE FD16CE FD4RE FD8RE FD16RE FDC FDC_1 FDCE FDCE_1

Description D Flip-Flop D Flip-Flop with Negative-Edge Clock Multiple D Flip-Flop Multiple D Flip-Flop Multiple D Flip-Flop 4-Bit Data Register with Clock Enable and Asynchronous Clear 8-Bit Data Register with Clock Enable and Asynchronous Clear 16-Bit Data Register with Clock Enable and Asynchronous Clear 4-Bit Data Register with Clock Enable and Synchronous Reset 8-Bit Data Register with Clock Enable and Synchronous Reset 16-Bit Data Register with Clock Enable and Synchronous Reset D Flip-Flop with Asynchronous Clear D Flip-Flop with Negative-Edge Clock and Asynchronous Clear D Flip-Flop with Clock Enable and Asynchronous Clear D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Clear D Flip-Flop with Asynchronous Preset and Clear D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and Clear

Spartan-II, IIE Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive

Spartan-3 Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive

Virtex, E Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive

Virtex II, Pro, Pro X Primitive Primitive No No No Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive

XC9500/XV/ XL Macro No Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro No Primitive No

CR XPLA3 Macro No Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro No Primitive No

CR-II Macro No Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro No Primitive No

FDCP FDCP_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive No

Primitive No

Primitive No

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Functional Categories

Design Element FDCPE

Description D Flip-Flop with Clock Enable and Asynchronous Preset and Clear D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop Multiple Dual Edge Triggered D Flip-Flop Multiple Dual Edge Triggered D Flip-Flop Multiple Dual Edge Triggered D Flip-Flop 4-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear 8-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear 16-Bit Dual Edge Triggered Data Register with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset 8-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset 16-Bit Dual Edge Triggered Data Register with Clock Enable and Synchronous Reset D Dual Edge Triggered Flip-Flop with Asynchronous Clear Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear Dual Edge Triggered D Flip-Flop Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop with Asynchronous Preset Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset Dual Edge Triggered D Flip-Flop with Synchronous Reset Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Edge Triggered D Flip-Flop with Clock Enable and Synchronous Reset Dual Data Rate D Flip-Flop with Clock Enable and Synchronous Reset and Set Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set

Spartan-II, IIE Primitive

Spartan-3 Primitive

Virtex, E Primitive

Virtex II, Pro, Pro X Primitive

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Primitive

FDCPE_1

Primitive

Primitive

Primitive

Primitive

No

No

No

FDD FDD4 FDD8 FDD16 FDD4CE

No No No No No

No No No No No

No No No No No

No No No No No

No No No No No

No No No No No

Macro Macro Macro Macro Macro

FDD8CE

No

No

No

No

No

No

Macro

FDD16CE

No

No

No

No

No

No

Macro

FDD4RE

No

No

No

No

No

No

Macro

FDD8RE

No

No

No

No

No

No

Macro

FDD16RE

No

No

No

No

No

No

Macro

FDDC FDDCE

No No

No No

No No

No No

No No

No No

Macro Primitive

FDDCP FDDCPE

No No

No No

No No

No No

No No

No No

Primitive Primitive

FDDP FDDPE

No No

No No

No No

No No

No No

No No

Macro Primitive

FDDR FDDRCPE

No No

No Primitive

No No

No Primitive

No No

No No

Macro No

FDDRE

No

No

No

No

No

No

Macro

FDDRRSE

No

Primitive

No

Primitive

No

No

No

FDDRS

No

No

No

No

No

No

Macro

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Design Element FDDRSE

Description Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set and Clock Enable Dual Edge Triggered D Flip-Flop with Synchronous Set D Flip-Flop with Clock Enable and Synchronous Set Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset and Clock Enable D Flip-Flop with Clock Enable D Flip-Flop with Negative-Edge Clock and Clock Enable D Flip-Flop with Asynchronous Preset D Flip-Flop with Negative-Edge Clock and Asynchronous Preset D Flip-Flop with Clock Enable and Asynchronous Preset D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset D Flip-Flop with Synchronous Reset D Flip-Flop with Negative-Edge Clock and Synchronous Reset D Flip-Flop with Clock Enable and Synchronous Reset D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset D Flip-Flop with Synchronous Reset and Set D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set D Flip-Flop with Synchronous Reset and Set and Clock Enable D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set, and Clock Enable D Flip-Flop with Synchronous Set D Flip-Flop with Negative-Edge Clock and Synchronous Set D Flip-Flop with Clock Enable and Synchronous Set D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set D Flip-Flop with Synchronous Set and Reset D Flip-Flop with Synchronous Set and Reset and Clock Enable J-K Flip-Flop with Asynchronous Clear

Spartan-II, IIE No

Spartan-3 No

Virtex, E No

Virtex II, Pro, Pro X No

XC9500/XV/ XL No

CR XPLA3 No

CR-II Macro

FDDS FDDSE FDDSR FDDSRE

No No No No

No No No No

No No No No

No No No No

No No No No

No No No No

Macro Macro Macro Macro

FDE FDE_1 FDP FDP_1 FDPE FDPE_1

Primitive Primitive Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive Primitive Primitive

No No Macro No Primitive No

No No Macro No Primitive No

No No Macro No Primitive No

FDR FDR_1 FDRE FDRE_1

Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive

Macro No Macro No

Macro No Macro No

Macro No Macro No

FDRS FDRS_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

Macro No

Macro No

Macro No

FDRSE FDRSE_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

Macro No

Macro No

Macro No

FDS FDS_1 FDSE FDSE_1

Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive

Primitive Primitive Primitive No

Macro No Macro No

Macro No Macro No

Macro No Macro No

FDSR FDSRE FJKC

No No Macro

No No Macro

No No Macro

No No Macro

Macro Macro Macro

Macro Macro Macro

Macro Macro Macro

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Functional Categories

Design Element FJKCE FJKCP FJKCPE

Description J-K Flip-Flop with Clock Enable and Asynchronous Clear J-K Flip-Flop with Asynchronous Clear and Preset J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable J-K Flip-Flop with Asynchronous Preset J-K Flip-Flop with Clock Enable and Asynchronous Preset J-K Flip-Flop with Clock Enable and Synchronous Reset and Set J-K Flip-Flop with Clock Enable and Synchronous Set and Reset Toggle Flip-Flop with Toggle Enable and Asynchronous Clear Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset Loadable Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset

Spartan-II, IIE Macro No No

Spartan-3 Macro No No

Virtex, E Macro No No

Virtex II, Pro, Pro X Macro No No

XC9500/XV/ XL Macro Macro Macro

CR XPLA3 Macro Macro Macro

CR-II Macro Macro Macro

FJKP FJKPE FJKRSE FJKSRE FTC FTCE

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

FTCLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTCLEX

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTCP

No

No

No

No

Primitive

Primitive

Primitive

FTCPE

No

No

No

No

Macro

Macro

Macro

FTCPLE

No

No

No

No

Macro

Macro

Macro

FTDCE

Dual Edge Triggered Toggle Flip- No Flop with Toggle and Clock Enable and Asynchronous Clear Dual Edge Triggered Toggle/ Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Dual Edge Triggered Toggle/ Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset No

No

No

No

No

No

Macro

FTDCLE

No

No

No

No

No

Macro

FTDCLEX

No

No

No

No

No

No

Macro

FTDCP

No

No

No

No

Primitive

Primitive

Primitive

FTDRSE

Dual Edge Triggered Toggle Flip- No Flop with Toggle and Clock Enable and Synchronous Reset and Set Dual Edge Triggered Toggle/ Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set Macro

No

No

No

No

No

Macro

FTDRSLE

Macro

Macro

Macro

Macro

Macro

Macro

FTP FTPE

Toggle Flip-Flop with Toggle Macro Enable and Asynchronous Preset Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Preset Macro

Macro Macro

Macro Macro

Macro Macro

Macro Macro

Macro Macro

Macro Macro

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Design Element FTPLE

Description Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Preset Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset

Spartan-II, IIE Macro

Spartan-3 Macro

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

FTRSE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTRSLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTSRE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

FTSRLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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Functional Categories

General
General elements include FPGA configuration functions, oscillators, boundary scan logic, and other functions not classified in other sections.
Design Element BSCAN_SPARTAN2 BSCAN_SPARTAN3 BSCAN_VIRTEX BSCAN_VIRTEX2 CAPTURE_SPARTA N2 CAPTURE_SPARTA N3 CAPTURE_VIRTEX Description Spartan-II Boundary Scan Logic Control Circuit. Spartan-3 Boundary Scan Logic Control Circuit Virtex Boundary Scan Logic Control Circuit. Virtex2 Boundary Scan Logic Control Circuit Spartan-II Register State Capture for Bitstream Readback Spartan-3 Register State Capture for Bitstream Readback Virtex Register State Capture for Bitstream Readback Virtex-II Register State Capture for Bitstream Readback Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Spartan-II, IIE Primitivea No Primitiveb No Primitive No Primitive No No No Spartan3 Virtex, E No No Primitive No No Virtex II, Pro, Pro X No No No Primitive No No No No No No XC9500/XV/ XL CR XPLA3 No No No No No CR-II No No No No No

No

Primitive

No

No

No

No

No

No

No

Primitive

No

No

No

No

CAPTURE_VIRTEX2

No

No

No

Primitive

No

No

No

CLK_DIV2 CLK_DIV4 CLK_DIV6 CLK_DIV8 CLK_DIV10 CLK_DIV12 CLK_DIV14 CLK_DIV16 CLK_DIV2R CLK_DIV4R CLK_DIV6R CLK_DIV8R CLK_DIV10R CLK_DIV12R CLK_DIV14R CLK_DIV16R CLK_DIV2RSD

No No No No No No No No No No No No No No No No No

No No No No No No No No No No No No No No No No No

No No No No No No No No No No No No No No No No No

No No No No No No No No No No No No No No No No No

No No No No No No No No No No No No No No No No No

No No No No No No No No No No No No No No No No No

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive

CLK_DIV4RSD

No

No

No

No

No

No

Primitive

78

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Design Element CLK_DIV6RSD

Description Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Synchronous Reset and Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Global Clock Divider with Start Delay Clock Delay Locked Loop. Clock Delay Locked Loop with Expanded Output. High Frequency Clock Delay Locked Loop. Digital Clock Manager Ground-Connection Signal Tag User Interface to Virtex-II Internal Configuration Access Port JTAG Primitive for the Power PC. KEEPER Symbol 1-Bit Look-Up-Table with General Output 2-Bit Look-Up-Table with General Output 3-Bit Look-Up-Table with General Output 4-Bit Look-Up-Table with General Output 1-Bit Look-Up-Table with Dual Output

Spartan-II, IIE No

Spartan3 No

Virtex, E No

Virtex II, Pro, Pro X No

XC9500/XV/ XL No

CR XPLA3 No

CR-II Primitive

CLK_DIV8RSD

No

No

No

No

No

No

Primitive

CLK_DIV10RSD

No

No

No

No

No

No

Primitive

CLK_DIV12RSD

No

No

No

No

No

No

Primitive

CLK_DIV14RSD

No

No

No

No

No

No

Primitive

CLK_DIV16RSD

No

No

No

No

No

No

Primitive

CLK_DIV2SD CLK_DIV4SD CLK_DIV6SD CLK_DIV8SD CLK_DIV10SD CLK_DIV12SD CLK_DIV14SD CLK_DIV16SD CLKDLL CLKDLLE CLKDLLHF DCM GND ICAP_VIRTEX2

No No No No No No No No Primitive Primitivec Primitive No Primitive No

No No No No No No No No No No No Primitive Primitive No

No No No No No No No No Primitive Primitived Primitivee No Primitive No

No No No No No No No No No No No Primitive Primitive Primitive

No No No No No No No No No No No No Primitive No

No No No No No No No No No No No No Primitive No

Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitive No No No No Primitive No

JTAGPPC KEEPER LUT1 LUT2 LUT3 LUT4 LUT1_D

No Primitive Primitive Primitive Primitive Primitive Primitive

No Primitive Primitive Primitive Primitive Primitive Primitive

No Primitive Primitive Primitive Primitive Primitive Primitive

Primitivef Primitive Primitive Primitive Primitive Primitive Primitive

No Nog No No No No No

No No No No No No No

No Primitive No No No No No

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Functional Categories

Design Element LUT2_D LUT3_D LUT4_D LUT1_L LUT2_L LUT3_L LUT4_L PPC405 PULLDOWN PULLUP

Description 2-Bit Look-Up-Table with Dual Output 3-Bit Look-Up-Table with Dual Output 4-Bit Look-Up-Table with Dual Output 1-Bit Look-Up-Table with Local Output 2-Bit Look-Up-Table with Local Output 3-Bit Look-Up-Table with Local Output 4-Bit Look-Up-Table with Local Output Primitive for the Power PC Core. Resistor to GND for Input Pads Resistor to VCC for Input PADs, Open-Drain, and 3State Outputs Reset On Configuration VHDL Simulation of FPGA Designs Spartan-II User Interface to Global Clock, Reset, and 3State Controls. Spartan-3 User Interface to Global Clock, Reset, and 3State Controls Virtex User Interface to Global Clock, Reset, and 3State Controls. Virtex-II User Interface to Global Clock, Reset, and 3State Controls Three-State On Configuration Three-State On Configuration Buffer VCC-Connection Signal Tag

Spartan-II, IIE Primitive Primitive Primitive Primitive Primitive Primitive Primitive No Primitive Primitive

Spartan3 Primitive Primitive Primitive Primitive Primitive Primitive Primitive No Primitive Primitive

Virtex, E Primitive Primitive Primitive Primitive Primitive Primitive Primitive No Primitive Primitive

Virtex II, Pro, Pro X Primitive Primitive Primitive Primitive Primitive Primitive Primitive Primitiveh Primitive Primitive

XC9500/XV/ XL No No No No No No No No No No

CR XPLA3 No No No No No No No No No Primitive

CR-II No No No No No No No No No Primitive

ROC STARTBUF_ architecture STARTUP_SPARTA N2 STARTUP_SPARTA N3 STARTUP_VIRTEX

Primitive Primitive Primitivei

Primitive Primitive No

Primitive Primitive No

Primitive Primitive No

No No No

No No No

No No No

No

Primitive

No

No

No

No

No

Primitivej

No

Primitive

No

No

No

No

STARTUP_VIRTEX2

No

No

No

Primitive

No

No

No

TOC TOCBUF VCC

Primitive Primitive Primitive

Primitive Primitive Primitive

Primitive Primitive Primitive

Primitive Primitive Primitive

No No Primitive

No No Primitive

No No Primitive

a.Primitive is supported for Spartan-II, but not for Spartan-IIE, which is supported by BSCAN_VIRTEX b.Primitive is supported for Spartan-IIE, but not for Spartan-II, which is supported by BSCAN_SPARTAN2. c. Supported for Spartan-IIE and Virtex-E devices only. d. Supported for Spartan-IIE and Virtex-E devices only. e.For Virtex E, use CLKDLLHF in HF mode. In LF mode, both the separate CLKDLLE and CLKDLL primitive can be used. f.Not supported for Virtex-II. Supported for Virtex-II PRO only. g.Under XC9500, the Primitive implementation applies only to XC9500XL/XV. h.The Primitive in the Virtex-II field is supported for Virtex-II PRO only. i.The Primitive in the field marked Spartan IIE is supported only for Spartan-II but not for Spartan-IIE, the latter of which is supported by STARTUP_VIRTEX. j.The Primitive in the Spartan IIE field is supported for Spartan-IIE, but not for Spartan-II, which is supported by STARTUP_SPARTAN2.

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Input Latches
Single and multiple input latches can hold transient data entering a chip. Input latches use the same naming convention as I/O flip-flops.
Design Element ILD ILD4 ILD8 ILD16 ILD_1 ILDI Description Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch with Inverted Gate Transparent Input Data Latch (Asynchronous Preset) Transparent Input Data Latch with Inverted Gate (Asynchronous Preset) Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch Transparent Input Data Latch with Inverted Gate Transparent Input Data Latch (Asynchronous Preset) Transparent Input Data Latch with Inverted Gate (Asynchronous Preset) Spartan-II, IIE Macro Macro Macro Macro Macro Macro Spartan-3 Macro Macro Macro Macro Macro Macro Virtex, E Macro Macro Macro Macro Macro Macro Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro No No No No No No XC9500/XV/ XL CR XPLA3 No Nob No No No No CR-II No No No No No No

ILDI_1

Macro

Macro

Macro

Macro

No

No

No

ILDX ILDX4 ILDX8 ILDX16 ILDX_1 ILDXI

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro Macro

No No No No No No

No No No No No No

No No No No No No

ILDXI_1

Macro

Macro

Macro

Macro

No

No

No

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Functional Categories

Input/Output Flip-Flops
Input/Output flip-flops are configured in IOBs. They include flip-flops whose outputs are enabled by 3-state buffers, flip-flops that can be set upon global set/reset rather than reset, and flip-flops with inverted clock inputs. The naming convention specifies each flip-flop function and is illustrated in the following figure.

OFDEI_1
Output (O), Input (I) Flip-Flop D-Type Active High Enable (E) Active Low Enable (T) Inverse of Normal Initial State Inverted Clock

X4580

Input/Output Flip-Flop Naming Convention


Design Element IFD IFD_1 IFD4 IFD8 IFD16 IFDDRCPE Description Single- and Multiple-Input D Flip-Flop Input D Flip-Flop with Inverted Clock Single- and Multiple-Input D Flip-Flop Single- and Multiple-Input D Flip-Flop Single- and Multiple-Input D Flip-Flop Dual Data Rate Input D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Data Rate Input D Flip-Flop with Synchronous Reset and Set and Clock Enable Input D Flip-Flop (Asynchronous Preset) Input D Flip-Flop with Inverted Clock (Asynchronous Preset) Single- and Multiple-Input D Flip-Flop with Clock Enable Input D Flip-Flop with Inverted Clock and Clock Enable Single- and Multiple-Input D Flip-Flop with Clock Enable Single- and Multiple-Input D Flip-Flop with Clock Enable Single- and Multiple-Input D Flip-Flops with Clock Enable Spartan-II, IIE Macro Macro Macro Macro Macro No Spartan3 Macro Macro Macro Macro Macro Primitive Virtex, E Macro Macro Macro Macro Macro No Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Primitive No No No No No No XC9500/XV/ XL CR XPLA3 No No No No No No CR-II No No No No No No

IFDDRRSE

No

Primitive

No

Primitive

No

No

No

IFDI IFDI_1

Macro Macro

Macro Macro

Macro Macro

Macro Macro

No No

No No

No No

IFDX

Macro

Macro

Macro

Macro

No

No

No

IFDX_1

Macro

Macro

Macro

Macro

No

No

No

IFDX4

Macro

Macro

Macro

Macro

No

No

No

IFDX8

Macro

Macro

Macro

Macro

No

No

No

IFDX16

Macro

Macro

Macro

Macro

No

No

No

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Design Element IFDXI

Description Input D Flip-Flop with Clock Enable (Asynchronous Preset) Single- and MultipleOutput D Flip-Flops Single- and MultipleOutput D Flip-Flops Single- and MultipleOutput D Flip-Flops Single- and MultipleOutput D Flip-Flops Output D Flip-Flop with Inverted Clock Dual Data Rate Output D Flip-Flop with Clock Enable and Asynchronous Preset and Clear Dual Data Rate Output D Flip-Flop with Synchronous Reset and Set and Clock Enable Dual Data Rate D Flip-Flop with Active-Low 3--State Output Buffer, Clock Enable, and Asynchro-nous Preset and Clear Dual Data Rate D Flip-Flop with Active -Low 3-State Output Buffer, Synchronous Reset and Set, and Clock Enable

Spartan-II, IIE Macro

Spartan3 Macro

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL No

CR XPLA3 No

CR-II No

OFD OFD4 OFD8 OFD16 OFD_1 OFDDRCPE

Macro Macro Macro Macro Macro No

Macro Macro Macro Macro Macro Primitive

Macro Macro Macro Macro Macro No

Macro Macro Macro Macro Macro Primitive

No No No No No No

No No No No No No

No No No No No No

OFDDRRSE

No

Primitive

No

Primitive

No

No

No

OFDDRTCPE

No

Primitive

No

Primitive

No

No

No

OFDDRTRSE

No

Primitive

No

Primitive

No

No

No

OFDE OFDE4 OFDE8 OFDE16 OFDE_1

D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveMacro High Enable Output Buffers D Flip-Flop with ActiveHigh Enable Output Buffer and Inverted Clock Output D Flip-Flop (Asynchronous Preset) Output D Flip-Flop with Inverted Clock (Asynchronous Preset) Single and Multiple D FlipFlop with Active-Low 3State Output Buffers Single and Multiple D FlipFlop with Active-Low 3State Output Buffers Single and Multiple D FlipFlop with Active-Low 3State Output Buffers Single and Multiple D FlipFlop with Active-Low 3State Output Buffers D Flip-Flop with ActiveLow 3-State Output Buffer and Inverted Clock Macro

Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro

Macro Macro Macro Macro Macro

No No No No No

No No No No No

No No No No No

OFDI OFDI_1

Macro Macro

Macro Macro

Macro Macro

Macro Macro

No No

No No

No No

OFDT

Macro

Macro

Macro

Macro

No

No

No

OFDT4

Macro

Macro

Macro

Macro

No

No

No

OFDT8

Macro

Macro

Macro

Macro

No

No

No

OFDT16

Macro

Macro

Macro

Macro

No

No

No

OFDT_1

Macro

Macro

Macro

Macro

No

No

No

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Functional Categories

Design Element OFDX

Description Single- and MultipleOutput D Flip-Flop with Clock Enable Single- and MultipleOutput D Flip-Flop with Clock Enable Single- and MultipleOutput D Flip-Flop with Clock Enable Single- and MultipleOutput D Flip-Flop with Clock Enable Output D Flip-Flop with Inverted Clock and Clock Enable Output D Flip-Flop with Clock Enable (Asynchronous Preset) Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)

Spartan-II, IIE Macro

Spartan3 Macro

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL No

CR XPLA3 No

CR-II No

OFDX4

Macro

Macro

Macro

Macro

No

No

No

OFDX8

Macro

Macro

Macro

Macro

No

No

No

OFDX16

Macro

Macro

Macro

Macro

No

No

No

OFDX_1

Macro

Macro

Macro

Macro

No

No

No

OFDXI

Macro

Macro

Macro

Macro

No

No

No

OFDXI_1

Macro

Macro

Macro

Macro

No

No

No

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Input/Output Functions
Input/Output Block (IOB) resources are configured into various I/O primitives and macros for convenience, such as output buffers (s) and output buffers with an enable (OBUFEs). Pads used to connect the circuit to PLD device pins are also included. Virtex, Virtex-E, Spartan-II, Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro, and VirtexII Pro X have multiple variants (Primitives) to choose from for each SelectIO buffer. The I/O interface for each variant corresponds to a specific I/O standard.
Design Element GT_AURORA_n GT_CUSTOM GT_ETHERNET_n GT_FIBRE_CHAN_n GT_INFINIBAND_n GT_XAUI_n GT10_10GE_n GT10_10GFC_n GT10_AURORA_n GT10_AURORAX_n GT10_CUS-TOM GT10_OC48_n GT10_OC192_n GT10_PCI_EXPRESS_n GT10_XAUI_n IBUF IBUF4 IBUF8 IBUF16 IBUF_ selectIO IBUFDS Description Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. 10-Gigabit Transceiver for High-Speed I/O. Single- and MultipleInput Buffer Single- and MultipleInput Buffer Single- and MultipleInput Buffer Single- and MultipleInput Buffer Single Input Buffer with Selectable I/O Interface (multiple primitives) Differential Signaling Input Buffer with Selectable I/O Interface Dedicated Input Buffer with Selectable I/O Interface Spartan-II, IIE No No No No No No No No No No No No No No No Primitive Macro Macro Macro Primitive Spartan-3 No No No No No No No No No No No No No No No Primitive No No No Primitive Virtex, E No No No No No Primitive No Primitive No No No No No Primitive No Primitive Macro Macro Macro Primitive Virtex II, Pro, Pro X Primitive Primitive Primitive Primitive Primitive No Primitive No Primitive Primitive Primitive Primitive Primitive No Primitive Primitive Macro Macro Macro Primitive No No No No No No No No No No No No No No No Primitive Macro Macro Macro No XC9500/XV/ XL CR XPLA3 No No No No No No No No No No No No No No No Primitive Macro Macro Macro No CR-II No No No No No No No No No No No No No No No Primitive Macro Macro Macro No

No

Primitive

No

Primitive

No

No

No

IBUFG

Primitive

Primitive

Primitive

Primitive

No

No

No

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Functional Categories

Design Element IBUFG_selectIO

Description Dedicated Input Buffer with Selectable I/O Interface (multiple primitives) Dedicated Differential Signaling Input Buffer with Selectable I/O Interface Differential I/O Input Buffer with Differential Outputs Bi-Directional Buffer with Selectable I/0 Interface (multiple primitives) Bi-Directional Buffer with Selectable I/0 Interface (multiple primitives) 3-State Differential Signaling I/O Buffer with Active Low Output Enable Single- and MultipleInput/Output Pad Single- and MultipleInput/Output Pad Single- and MultipleInput/Output Pad Single- and MultipleInput/Output Pad Single- and MultipleInput Pad Single- and MultipleInput Pad Single- and MultipleInput Pad Single- and MultipleInput Pad Single 3-State Output Buffer with Active-Low Output Enable and Selectable I/O Interface (multiple primitives) Single- and MultipleOutput Buffer Single- and MultipleOutput Buffer Single- and MultipleOutput Buffer Single- and MultipleOutput Buffer Differential Signaling Output Buffer with Selectable I/O Interface 3-State Output Buffers with Active-High Output Enable 3-State Output Buffers with Active-High Output Enable

Spartan-II, IIE Primitive

Spartan-3 Primitive

Virtex, E Primitive

Virtex II, Pro, Pro X Primitive

XC9500/XV/ XL No

CR XPLA3 No

CR-II No

IBUFGDS

No

Primitive

No

Primitive

No

No

No

IBUFGDS_DIFF_OUT

No

Primitive

No

Primitive

No

No

No

IOBUF

Primitive

Primitive

Primitive

Primitive

No

No

No

IOBUF_selectIO

Primitive

Primitive

Primitive

Primitive

No

No

No

IOBUFDS

No

Primitive

No

Primitive

No

No

No

IOPAD IOPAD4 IOPAD8 IOPAD16 IPAD IPAD4 IPAD8 IPAD16 OBUF_selectIO

Primitive Macro Macro Macro Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro Primitive Macro Macro Macro No

Primitive Macro Macro Macro Primitive Macro Macro Macro No

Primitive Macro Macro Macro Primitive Macro Macro Macro No

OBUF OBUF4 OBUF8 OBUF16 OBUFDS

Primitive Macro Macro Macro No

Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro No

Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro No

Primitive Macro Macro Macro No

Primitive Macro Macro Macro No

OBUFE

Macro

No

Macro

Macro

Primitive

Primitive

Primitive

OBUFE4

Macro

No

Macro

Macro

Macro

Macro

Macro

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Design Element OBUFE8

Description 3-State Output Buffers with Active-High Output Enable 3-State Output Buffers with Active-High Output Enable Single and Multiple 3State Output Buffer with Active Low Output Enable Single 3-State Output Buffer with Active-Low Output Enable and Selectable I/O Interface (multiple primitives) Single and Multiple 3State Output Buffer with Active Low Output Enable Single and Multiple 3State Output Buffer with Active Low Output Enable Single and Multiple 3State Output Buffer with Active Low Output Enable 3-State Output Buffer with Differential Signaling, Active-Low Output Enable, and Selectable I/O Interface Single- and MultipleOutput Pad Multiple-Output Pad Multiple-Output Pad Multiple-Output Pad Connects the I/O Node of an IOB to the Internal PLD Circuit

Spartan-II, IIE Macro

Spartan-3 No

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

OBUFE16

Macro

No

Macro

Macro

Macro

Macro

Macro

OBUFT

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OBUFT_selectIO

Primitive

Primitive

Primitive

Primitive

No

No

No

OBUFT4

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUFT8

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUFT16

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OBUFTDS

No

Primitive

No

Primitive

No

No

No

OPAD OPAD4 OPAD8 OPAD16 UPAD

Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro Primitive

Primitive Macro Macro Macro No

Primitive Macro Macro Macro No

Primitive Macro Macro Macro No

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Functional Categories

Latches
Latches (LD) are available for all architectures.
Design Element LD LD_1 LD4 LD8 LD16 LD4CE Description Transparent Data Latch Transparent Data Latch with Inverted Gate Multiple Transparent Data Latch Multiple Transparent Data Latch Multiple Transparent Data Latch Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear Transparent Data Latch with Asynchronous Clear and Inverted Gate Transparent Data Latch with Asynchronous Clear and Gate Enable Transparent Data Latch with Asynchronous Clear, Gate Enable, and Inverted Gate Transparent Data Latch with Asynchronous Clear and Preset Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate Spartan-II, IIE Primitive Primitive Macro Macro Macro Macro Spartan-3 Primitive Primitive Macro Macro Macro Macro Virtex, E Primitive Primitive Macro Macro Macro Macro Virtex II, Pro, Pro X Primitive Primitive Macro Macro Macro Macro XC9500/XV/ XL Macro No Macro Macro Macro No CR XPLA3 Primitive No Macro Macro Macro No CR-II Primitive No Macro Macro Macro No

LD8CE

Macro

Macro

Macro

Macro

No

No

No

LD16CE

Macro

Macro

Macro

Macro

No

No

No

LDC LDC_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

Macro No

Primitive No

Primitive No

LDCE

Primitive

Primitive

Primitive

Primitive

No

No

No

LDCE_1

Primitive

Primitive

Primitive

Primitive

No

No

No

LDCP

Primitive

Primitive

Primitive

Primitive

Macro

Primitive

Primitive

LDCP_1

Primitive

Primitive

Primitive

Primitive

No

No

No

LDCPE

Transparent Data Latch Primitive with Asynchronous Clear and Preset and Gate Enable Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable, and Inverted Gate Transparent Data Latch with Gate Enable Transparent Data Latch with Gate Enable and Inverted Gate Primitive

Primitive

Primitive

Primitive

No

No

No

LDCPE_1

Primitive

Primitive

Primitive

No

No

No

LDE LDE_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

No No

No No

No No

LDG LDG4 LDG8 LDG16

Transparent Datagate Latch No Multiple Transparent Datagate Latch Multiple Transparent Datagate Latch Multiple Transparent Datagate Latch No No No

No No No No

No No No No

No No No No

No No No No

No No No No

Primitive Macro Macro Macro

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Design Element LDP LDP_1

Description Transparent Data Latch with Asynchronous Preset Transparent Data Latch with Asynchronous Preset and Inverted Gate Transparent Data Latch with Asynchronous Preset and Gate Enable Transparent Data Latch with Asynchronous Preset, Gate Enable, and Inverted Gate

Spartan-II, IIE Primitive Primitive

Spartan-3 Primitive Primitive

Virtex, E Primitive Primitive

Virtex II, Pro, Pro X Primitive Primitive

XC9500/XV/ XL Macro No

CR XPLA3 Macro No

CR-II Macro No

LDPE

Primitive

Primitive

Primitive

Primitive

No

No

No

LDPE_1

Primitive

Primitive

Primitive

Primitive

No

No

No

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Functional Categories

Logic Primitives
Combinatorial logic gates that implement the basic Boolean functions are available in all architectures with up to five inputs in all combinations of inverted and noninverted inputs, and with six to nine inputs non-inverted.
Design Element AND2 Description 2-Input AND Gate with Inverted and Non-Inverted Inputs 2-Input AND Gate with Inverted and Non-Inverted Inputs 2-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 3-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 4-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs 5-Input AND Gate with Inverted and Non-Inverted Inputs Spartan-II, IIE Primitive Spartan-3 Primitive Virtex, E Primitive Virtex II, Pro, Pro X Primitive XC9500/XV/ XL Primitive CR XPLA3 Primitive CR-II Primitive

AND2B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND2B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND3

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

AND3B1

Macro

Macro

Macro

Macro

Macro

Macro

Macro

AND3B2

Macro

Macro

Macro

Macro

Macro

Macro

Macro

AND3B3

Macro

Macro

Macro

Macro

Macro

Macro

Macro

AND4

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

AND4B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND4B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND4B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND4B4

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

AND5B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B4

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

AND5B5

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

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Design Element AND6

Description 6-Input AND Gate with Inverted and Non-Inverted Inputs 7-Input AND Gate with Inverted and Non-Inverted Inputs 8-Input AND Gate with Inverted and Non-Inverted Inputs 9-Input AND Gate with Inverted and Non-Inverted Inputs 12- Input AND Gate with Non-Inverted Inputs 16- Input AND Gate with Non-Inverted Inputs

Spartan-II, IIE Macro

Spartan-3 Macro

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL Primitive

CR XPLA3 Primitive

CR-II Primitive

AND7

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

AND8

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

AND9

Macro

Macro

Macro

Macro

Primitive

Primitive

Primitive

AND12 AND16 INV INV4 INV8 INV16 MULT_AND NAND2

Macro Macro

Macro Macro Primitive Macro Macro Macro Primitive Primitive

Macro Macro Primitive Macro Macro Macro Primitive Primitive

Macro Macro Primitive Macro Macro Macro Primitive Primitive

No No Primitive Macro Macro Macro No Primitive

No No Primitive Macro Macro Macro No Primitive

No No Primitive Macro Macro Macro No Primitive

Single and Multiple Inverters Primitive Single and Multiple Inverters Macro Single and Multiple Inverters Macro Single and Multiple Inverters Macro Fast Multiplier AND 2-Input NAND Gate with Inverted and Non-Inverted Inputs. 2-Input NAND Gate with Inverted and Non-Inverted Inputs. 2-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 3-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 4-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. Primitive Primitive

NAND2B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND2B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND3

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NAND3B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND3B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND3B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NAND4B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND4B4

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

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Functional Categories

Design Element NAND5B1

Description 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 5-Input NAND Gate with Inverted and Non-Inverted Inputs. 6-Input NAND Gate with Inverted and Non-Inverted Inputs. 7-Input NAND Gate with Inverted and Non-Inverted Inputs. 8-Input NAND Gate with Inverted and Non-Inverted Inputs. 9-Input NAND Gate with Inverted and Non-Inverted Inputs. 12- Input NAND Gate with Non-Inverted Inputs. 16- Input NAND Gate with Non-Inverted Inputs. 2- Input NOR Gate with Inverted and Non-Inverted Inputs. 3- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 6- Input NOR Gate with Inverted and Non-Inverted Inputs 7- Input NOR Gate with Inverted and Non-Inverted Inputs 8- Input NOR Gate with Inverted and Non-Inverted Inputs 9- Input NOR Gate with Inverted and Non-Inverted Inputs 12-Input NOR Gate with Non-Inverted Inputs 16-Input NOR Gate with Non-Inverted Inputs 2- Input NOR Gate with Inverted and Non-Inverted Inputs

Spartan-II, IIE Primitive

Spartan-3 Primitive

Virtex, E Primitive

Virtex II, Pro, Pro X Primitive

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

NAND5B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5B4

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND5B5

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NAND6

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND7

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND8

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND9

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NAND12 NAND16 NOR2

Macro Macro Primitive

Macro Macro Primitive

Macro Macro Primitive

Macro Macro Primitive

No No Primitive

No No Primitive

No No Primitive

NOR3

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NOR4

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NOR5

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

NOR6

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR7

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR8

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR9

Macro

Macro

Macro

Macro

Macro

Macro

Macro

NOR12 NOR16 NOR2B1

Macro Macro Primitive

Macro Macro Primitive

Macro Macro Primitive

Macro Macro Primitive

No No Macro

No No Macro

No No Macro

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Design Element NOR2B2

Description 2- Input NOR Gate with Inverted and Non-Inverted Inputs 3- Input NOR Gate with Inverted and Non-Inverted Inputs 3- Input NOR Gate with Inverted and Non-Inverted Inputs 3- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 4- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 5- Input NOR Gate with Inverted and Non-Inverted Inputs 2-Input OR Gate with Inverted and Non-Inverted Inputs 2-Input OR Gate with Inverted and Non-Inverted Inputs 2-Input OR Gate with Inverted and Non-Inverted Inputs 3-Input OR Gate with Inverted and Non-Inverted Inputs 3-Input OR Gate with Inverted and Non-Inverted Inputs 3-Input OR Gate with Inverted and Non-Inverted Inputs 3Input OR Gate with Inverted and Non-Inverted Inputs 4-Input OR Gate with Inverted and Non-Inverted Inputs

Spartan-II, IIE Primitive

Spartan-3 Primitive

Virtex, E Primitive

Virtex II, Pro, Pro X Primitive

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

NOR3B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR3B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR3B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR4B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR4B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR4B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR4B4

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B4

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

NOR5B5

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR2

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR2B1

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR2B2

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3B1

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3B2

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR3B3

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR4

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

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Design Element OR4B1

Description 4-Input OR Gate with Inverted and Non-Inverted Inputs 4-Input OR Gate with Inverted and Non-Inverted Inputs 4-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 12-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 5-Input OR Gate with Inverted and Non-Inverted Inputs 6-Input OR Gate with Inverted and Non-Inverted Inputs 6-Input OR Gate with Inverted and Non-Inverted Inputs 8-Input OR Gate with Inverted and Non-Inverted Inputs 9-Input OR Gate with Inverted and Non-Inverted Inputs 12-Input OR Gate with Inverted and Non-Inverted Inputs 16-Input OR Gate with Inverted and Non-Inverted Inputs OR with Carry Logic Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products Sum of Products 2-Input XNOR Gate with Non-Inverted Inputs

Spartan-II, IIE Primitive

Spartan-3 Primitive

Virtex, E Primitive

Virtex II, Pro, Pro X Primitive

XC9500/XV/ XL Primitive

CR XPLA3 Primitive

CR-II Primitive

OR4B2

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR4B3

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

Primitive

OR5B1

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B2

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B3

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B4

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR5B5

Primitive

Primitive

Primitive

Primitive

Macro

Macro

Macro

OR6

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR7

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR8

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR9

Macro

Macro

Macro

Macro

Macro

Macro

Macro

OR12

Macro

Macro

Macro

Macro

No

No

No

OR16

Macro

Macro

Macro

Macro

No

No

No

ORCY SOP3 SOP3B1A SOP3B1B SOP3B2A SOP3B2B SOP3B3 SOP4 SOP4B3 SOP4B4 SOP4B1 SOP4B2A SOP4B2B XNOR2

Primitive Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Primitive

Primitive Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Primitive

Primitive Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Primitive

Primitive Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Macro Primitive

No No No No No No No No No No No No No Primitive

No No No No No No No No No No No No No Primitive

No No No No No No No No No No No No No Primitive

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Design Element XNOR3 XNOR4 XNOR5 XNOR6 XNOR7 XNOR8 XNOR9 XOR2 XOR3 XOR4 XOR5 XOR6 XOR7 XOR8 XOR9 XORCY XORCY_D XORCY_L

Description 3-Input XNOR Gate with Non-Inverted Inputs 4-Input XNOR Gate with Non-Inverted Inputs 5-Input XNOR Gate with Non-Inverted Inputs 6-Input XNOR Gate with Non-Inverted Inputs 7-Input XNOR Gate with Non-Inverted Inputs 8-Input XNOR Gate with Non-Inverted Inputs 9-Input XNOR Gate with Non-Inverted Inputs 2-Input XOR Gate with NonInverted Inputs 3-Input XOR Gate with NonInverted Inputs 4-Input XOR Gate with NonInverted Inputs 5-Input XOR Gate with NonInverted Inputs 6-Input XOR Gate with NonInverted Inputs 7-Input XOR Gate with NonInverted Inputs 8-Input XOR Gate with NonInverted Inputs 9-Input XOR Gate with NonInverted Inputs XOR for Carry Logic with General Output XOR for Carry Logic with Dual Output XOR for Carry Logic with Local Output

Spartan-II, IIE Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive

Spartan-3 Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive

Virtex, E Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive

Virtex II, Pro, Pro X Primitive Primitive Primitive Primitive Primitive Primitive Macro Macro Macro Primitive Primitive Macro Macro Primitive Macro Primitive Primitive Primitive

XC9500/XV/ XL Primitive Primitive Macro Macro Macro Macro Macro Primitive Primitive Primitive Macro Macro Macro Macro Macro No No No

CR XPLA3 Primitive Primitive Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro Macro No No No

CR-II Primitive Primitive Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro Macro No No No

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Functional Categories

Map Elements
Map elements are used in conjunction with logic symbols to constrain the logic to particular CLBs or particular F function generators.
Design Element FMAP Description F Function Generator Partitioning Control Symbol Spartan-II, IIE Primitive Spartan-3 Primitive Virtex, E Primitive Virtex II, Pro, Pro X Primitive XC9500/XV/ XL No CR XPLA3 No CR-II No

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Memory Elements
In the Virtex, Virtex-E, Spartan-II, and Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X architectures, a number of static RAMs are defined as primitives. These 16- or 32-word RAMs are 1, 2, 4, and 8 bits wide. The Virtex, Virtex-E, Spartan-II, and Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X architectures have dedicated blocks of on-chip 4096-bit single-port and dual-port synchronous RAM. Each port is configured to a specific data width. There are five single-port block RAM primitives and 30 dual-port block RAM primitives.
Design Element RAM16X1D RAM16X1D_1 Description 16-Deep by 1-Wide Static Dual Port Synchronous RAM 16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock 16-Deep by 1-Wide Static Synchronous RAM 16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 16-Deep by 2-Wide Static Dual Port Synchronous RAM 16-Deep by 2-Wide Static Synchronous RAM 16-Deep by 4-Wide Static Dual Port Synchronous RAM 16-Deep by 4-Wide Static Synchronous RAM 16-Deep by 8-Wide Static Dual Port Synchronous RAM 16-Deep by 8-Wide Static Synchronous RAM 32-Deep by 1-Wide Static Dual Static Port Synchronous RAM 32-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock 32-Deep by 1-Wide Static Synchronous RAM 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 32-Deep by 2-Wide Static Synchronous RAM 32-Deep by 4-Wide Static Synchronous RAM 32-Deep by 8-Wide Static Synchronous RAM 64-Deep by 1-Wide Dual Port Static Synchronous RAM 64-Deep by 1-Wide Dual Port Static Synchronous RAM with Negative-Edge Clock 64-Deep by 1-Wide Static Synchronous RAM Spartan-II, IIE Primitive Primitive Spartan-3 Primitive Primitive Virtex, E Primitive Primitive Virtex II, Pro, Pro X Primitive Primitive No No XC9500/XV/ XL CR XPLA3 No No CR-II No No

RAM16X1S RAM16X1S_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

No No

No No

No No

RAM16X2D RAM16X2S RAM16X4D RAM16X4S RAM16X8D RAM16X8S RAM32X1D RAM32X1D_1

Macro Macro Macro Macro Macro Macro No No

No Primitive No Primitive No No No No

Macro Macro Macro Macro Macro Macro No No

Macro Primitive Macro Primitive Macro Primitive Primitive Primitive

No No No No No No No No

No No No No No No No No

No No No No No No No No

RAM32X1S RAM32X1S_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

No No

No No

No No

RAM32X2S RAM32X4S RAM32X8S RAM64X1D RAM64X1D_1

Macro Macro Macro No No

Primitive No No No No

Macro Macro Macro No No

Primitive Primitive Primitive Primitive Primitive

No No No No No

No No No No No

No No No No No

RAM64X1S

No

Primitive

No

Primitive

No

No

No

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Functional Categories

Design Element RAM64X1S_1

Description 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 64-Deep by 2-Wide Static Synchronous RAM 128-Deep by 1-Wide Static Synchronous RAM 128-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock 4096-Bit Dual-Port Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 8, or 16 Bits 4096-Bit Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 8, or 16 Bits

Spartan-II, IIE No

Spartan-3 Primitive

Virtex, E No

Virtex II, Pro, Pro X Primitive

XC9500/XV/ XL No

CR XPLA3 No

CR-II No

RAM64X2S RAM128X1S RAM128X1S_1

No No No

No No No

No No No

Primitive Primitive Primitive

No No No

No No No

No No No

RAMB4_Sm_Sn

Primitive

No

Primitive

No

No

No

No

RAMB4_Sn

Primitive

No

Primitive

No

No

No

No

RAMB16_Sm_Sn

16384-Bit Data Memory and No 2048-Bit Parity Memory, DualPort Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 9, 18, or 36 Bits 16384-Bit Data Memory and 2048-Bit Parity Memory, Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 9, 18, or 36 Bits Reset On Configuration No

Primitive

No

Primitive

No

No

No

RAMB16_Sn

Primitive

No

Primitive

No

No

No

ROC ROCBUF ROM16X1 ROM32X1 ROM64X1 ROM128X1 ROM256X1

Primitive

Primitive Primitive Primitive Primitive Primitive Primitive Primitive

Primitive Primitive Primitive Primitive No No No

Primitive Primitive Primitive Primitive Primitive Primitive Primitive

No No No No No No No

No No No No No No No

No No No No No No No

Reset On Configuration Buffer Primitive 16-Deep by 1-Wide ROM 32-Deep by 1-Wide ROM 64-Deep by 1-Wide ROM 128-Deep by 1-Wide ROM 256-Deep by 1-Wide ROM Primitive Primitive No No No

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Multiplexers
The multiplexer naming convention shown in the following figure indicates the number of inputs and outputs and whether or not an enable is available.

M8_1E
Multiplexer Number of Inputs Number of Outputs Output Enable
X4620

Multiplexer Naming Convention


Design Element M2_1 M2_1B1 M2_1B2 M2_1E M4_1E M8_1E M16_1E MUXCY MUXCY_D MUXCY_L MUXF5 Description 2-to-1 Multiplexer 2-to-1 Multiplexer with D0 Inverted 2-to-1 Multiplexer with D0 and D1 Inverted 2-to-1 Multiplexer with Enable 4-to-1 Multiplexer with Enable 8-to-1 Multiplexer with Enable 16-to-1 Multiplexer with Enable 2-to-1 Multiplexer for Carry Logic with General Output 2-to-1 Multiplexer for Carry Logic with Dual Output 2-to-1 Multiplexer for Carry Logic with Local Output 2-to-1 Lookup Table Multiplexer with General Output 2-to-1 Lookup Table Multiplexer with Dual Output 2-to-1 Lookup Table Multiplexer with Local Output 2-to-1 Lookup Table Multiplexer with General Output 2-to-1 Lookup Table Multiplexer with Dual Output 2-to-1 Lookup Table Multiplexer with Local Output 2-to-1 Lookup Table Multiplexer with General Output 2-to-1 Lookup Table Multiplexer with Dual Output 2-to-1 Lookup Table Multiplexer with Local Output 2-to-1 Lookup Table Multiplexer with General Output Spartan-II, IIE Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Spartan-3 Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Virtex, E Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Virtex II, Pro, Pro X Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive XC9500/XV/ XL Macro Macro Macro Macro Macro Macro Macro No No No No CR XPLA3 Macro Macro Macro Macro Macro Macro Macro No No No No CR-II Macro Macro Macro Macro Macro Macro Macro No No No No

MUXF5_D MUXF5_L MUXF6

Primitive Primitive Primitive

Primitive Primitive Primitive

Primitive Primitive Primitive

Primitive Primitive Primitive

No No No

No No No

No No No

MUXF6_D MUXF6_L MUXF7

Primitive Primitive No

Primitive Primitive Primitive

Primitive Primitive No

Primitive Primitive Primitive

No No No

No No No

No No No

MUXF7_D MUXF7_L MUXF8

No No No

Primitive Primitive Primitive

No No No

Primitive Primitive Primitive

No No No

No No No

No No No

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Shifters
Shifters are barrel shifters (BRLSHFT) of four and eight bits.
Design Element BRLSHFT4 BRLSHFT8 Description 4-Bit Barrel Shifter 8-Bit Barrel Shifter Spartan-II, IIE Macro Macro Spartan-3 Macro Macro Virtex, E Macro Macro Virtex II, Pro, Pro X Macro Macro XC9500/XV/ XL Macro Macro CR XPLA3 Macro Macro CR-II Macro Macro

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Shift Registers
Shift registers are available in a variety of sizes and capabilities. The naming convention shown in the following figure illustrates available features.

SR8RLED
Shift Register Bit Size Synchronous Reset (R) Asynchronous Clear (C) Loadable Clock Enable Directional

X4578

Shift Register Naming Convention


Design Element SR4CE Description 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear 4-Bit Shift Register with Clock Enable and Asynchronous Clear 8-Bit Shift Register with Clock Enable and Asynchronous Clear 16-Bit Shift Register with Clock Enable and Asynchronous Clear 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset Spartan-II, IIE Macro Spartan-3 Macro Virtex, E Macro Virtex II, Pro, Pro X Macro XC9500/XV/ XL Macro CR XPLA3 Macro CR-II Macro

SR8CE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16CE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4CLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR8CLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16CLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4CLED SR8CLED SR16CLED SR4RE

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

Macro Macro Macro Macro

SR8RE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR16RE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4RLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

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Functional Categories

Design Element SR8RLE

Description 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset 4-Bit Shift Register with Clock Enable and Synchronous Reset 8-Bit Shift Register with Clock Enable and Synchronous Reset 16-Bit Shift Register with Clock Enable and Synchronous Reset 4-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 8-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 4-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 8-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 4-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 8-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 16-Bit Dual Edge Triggered Shift Register with Clock Enable and Asynchronous Clear 4-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 8-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Serial-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 4-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset

Spartan-II, IIE Macro

Spartan-3 Macro

Virtex, E Macro

Virtex II, Pro, Pro X Macro

XC9500/XV/ XL Macro

CR XPLA3 Macro

CR-II Macro

SR16RLE

Macro

Macro

Macro

Macro

Macro

Macro

Macro

SR4RLED SR8RLED SR16RLED SRD4CE

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro No

Macro Macro Macro Macro

SRD8CE

No

No

No

No

No

No

Macro

SRD16CE

No

No

No

No

No

No

Macro

SRD4CLE

No

No

No

No

No

No

Macro

SRD8CLE

No

No

No

No

No

No

Macro

SRD16CLE

No

No

No

No

No

No

Macro

SRD4CLED

No

No

No

No

No

No

Macro

SRD8CLED

No

No

No

No

No

No

Macro

SRD16CLED

No

No

No

No

No

No

Macro

SRD4RE

No

No

No

No

No

No

Macro

SRD8RE

No

No

No

No

No

No

Macro

SRD16RE

No

No

No

No

No

No

Macro

SRD4RLE

No

No

No

No

No

No

Macro

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Design Element SRD8RLE

Description 8-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Loadable Serial/Parallel-In Parallel-Out Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 4-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 8-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Dual Edge Triggered Shift Register with Clock Enable and Synchronous Reset 16-Bit Shift Register Look-UpTable (LUT) 16-Bit Shift Register Look-UpTable (LUT) with Negative-Edge Clock 16-Bit Shift Register Look-UpTable (LUT) with Clock Enable 16-Bit Shift Register Look-UpTable (LUT) with Negative-Edge Clock and Clock Enable 16-Bit Shift Register Look-UpTable (LUT) with Carry 16-Bit Shift Register Look-UpTable (LUT) with Carry and Negative-Edge Clock 16-Bit Shift Register Look-UpTable (LUT) with Carry and Clock Enable

Spartan-II, IIE No

Spartan-3 No

Virtex, E No

Virtex II, Pro, Pro X No

XC9500/XV/ XL No

CR XPLA3 No

CR-II Macro

SRD16RLE

No

No

No

No

No

No

Macro

SRD4RLED

No

No

No

No

No

No

Macro

SRD8RLED

No

No

No

No

No

No

Macro

SRD16RLED

No

No

No

No

No

No

Macro

SRL16 SRL16_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

No No

No No

No No

SRL16E SRL16E_1

Primitive Primitive

Primitive Primitive

Primitive Primitive

Primitive Primitive

No No

No No

No No

SRLC16 SRLC16_1

No No

Primitive Primitive

No No

Primitive Primitive

No No

No No

No No

SRLC16E

No

Primitive

No

Primitive

No

No

No

SRLC16E_1

16-Bit Shift Register Look-UpNo Table (LUT) with Carry, NegativeEdge Clock, and Clock Enable

Primitive

No

Primitive

No

No

No

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Functional Categories

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Design Elements
The remaining sections in this book describe each design element that can be used with the supported architectures. Design elements are organized in alphanumeric order, with all numeric suffixes in ascending order. For example, FDR precedes FDRS, and ADD4 precedes ADD8, which precedes ADD16. The following information is provided for each library element, where applicable Graphic symbol Applicability table (with primitive versus macro identification) Functional description Truth table Schematic for macros VHDL and Verilog instantiation and inference code Commonly used constraints

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Design Elements

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ACC1

ACC1
1-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
Architectures Supported
ACC1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CI B0 D0 L ADD CE C

ACC1

Q0 CO

X3862

ACC1 can add or subtract a 1-bit unsigned-binary word to or from the contents of a 1bit data register and store the results in the register. The register can be loaded with a 1-bit word. The synchronous reset (R) has priority over all other inputs and, when High, causes the output to go to logic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clock enable (CE) is Low. The accumulator is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Load
When the load input (L) is High, CE is ignored and the data on the input D0 is loaded into the 1-bit register during the Low-to-High clock (C) transition.

Add
When control inputs ADD and CE are both High, the accumulator adds a 1-bit word (B0) and carry-in (CI) to the contents of the 1-bit register. The result is stored in the register and appears on output Q0 during the Low-to-High clock transition. The carry-out (CO) is not registered synchronously with the data output. CO always reflects the accumulation of input B0 and the contents of the register, which allows cascading of ACC1s by connecting CO of one stage to CI of the next stage. In add mode, CO acts as a carry-out, and CO and CI are active-High.

Subtract
When ADD is Low and CE is High, the 1-bit word B0 and CI are subtracted from the contents of the register. The result is stored in the register and appears on output Q0 during the Low-to-High clock transition. The carry-out (CO) is not registered synchronously with the data output. CO always reflects the accumulation of input B0 and the contents of the register, which allows cascading of ACC1s by connecting CO of one stage to CI of the next stage. In subtract mode, CO acts as a borrow, and CO and CI are active-Low.

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107

ACC1

VCC

CE CI ADD L
OR2 GND AND2

INV INV

B0

INV AND6

INV INV INV INV INV AND6

OR4

INV INV INV AND6

INV INV INV AND6

D0 FD
AND3B1 OR2 XOR2 D C Q

Q0

AND3B2

Q0

AND3

AND3

CO
AND3B2 OR5

AND3B2

AND2

X7688

ACC1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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ACC1

Usage
ACC is schematic and inference only-- not instantiated.

VHDL Inference Code


Following is some "basic" code for inference of the ACC modules.
architecture Behavioral of acc1 is begin process(C, R) begin if (R = '1') then Q <= (others => '0'); elsif (C'event and C = '1') then if (L = '1') then Q <= D; elsif (CE = '1') then if (ADD = '1') then Q <= Q + B; else Q <= Q - B; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) end if (ADD) Q <= Q + B; else Q <= Q - B; end

Commonly Used Constraints


None

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ACC1

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ACC4, 8, 16

ACC4, 8, 16
4-, 8-, 16-Bit Loadable Cascadable Accumulators with Carry-In, CarryOut, and Synchronous Reset
Architectures Supported
ACC4, ACC8, ACC16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CI B0 B1 B2 B3 D0 D1 D2 D3 L ADD CE C

ACC4
Q0 Q1 Q2 Q3 CO OFL

ACC4, ACC8, ACC16 can add or subtract a 4-, 8-, 16-bit unsigned-binary, respectively or twos-complement word to or from the contents of a 4-, 8-, 16-bit data register and store the results in the register. The register can be loaded with the 4-, 8-, 16-bit word. The synchronous reset (R) has priority over all other inputs, and when High, causes all outputs to go to logic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clock enable (CE) is Low. The accumulator is asynchronously cleared, outputs Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.

X3863

CI B[7:0] D[7:0] L ADD CE C

ACC8

Q[7:0] CO OFL

Load
X4374

CI B[15:0] D[15:0] L ADD CE C

ACC16

Q[15:0] CO OFL

When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during the Low-to-High clock (C) transition. ACC4 loads the data on inputs D3 D0 into the 4-bit register. ACC8 loads the data on D7 D0 into the 8-bit register. ACC16 loads the data on inputs D15 D0 into the 16-bit register.

Unsigned Binary Versus Twos Complement


ACC4, ACC8, ACC16 can operate, respectively, on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twoscomplement operation is how they determine when overflow occurs. Unsigned

X4375

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ACC4, 8, 16

binary uses CO, while twos complement uses OFL to determine when overflow occurs.

Unsigned Binary Operation


For unsigned binary operation, ACC4 can represent numbers between 0 and 15, inclusive; ACC8 between 0 and 255, inclusive; and ACC16 between 0 and 65535, inclusive. In add mode, CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) is not registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs (B3 B0 for ACC4, B7 B0 for ACC8, B15 B0 for ACC16) and the contents of the register. This allows cascading of ACC4s, ACC8s, or ACC16s by connecting CO of one stage to CI of the next stage. An unsigned binary overflow that is always activeHigh can be generated by gating the ADD signal and CO as follows.
unsigned overflow = CO XOR ADD

Ignore OFL in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ACC4 can represent numbers between -8 and +7, inclusive; ACC8 between -128 and +127, inclusive; ACC16 between -32768 and +32767, inclusive. If an addition or subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is not registered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B3 B0 for ACC4, B7 B0 for ACC8, B15 B0 for ACC16) and the contents of the register, which allows cascading of ACC4s, ACC8s, or ACC16s by connecting OFL of one stage to CI of the next stage. Ignore CO in twos-complement operation.

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ACC4, 8, 16

Q[7:0] CI CI A[7:0] B[7:0] B[7:0] ADD CO ADD RLOC=R0C0 D[7:0] M2_1 S0 D0 D0 D1 S0 O SD0 SD0 AND2B1 R_SD0 D Q CE C CLR FDCE Q0 OFL OFL CO S[7:0] S[7:0]

ADSU8

Q0 FMAP

RLOC=R3C0.S0 FMAP R S3 D3 L M2_1 I4 I3 I2 I1 O R_SD3 S1 D1 D0 D1 S0 O SD1 SD1 AND2B1 R_SD1 D Q CE C CLR FDCE Q1 R S7 D7 L I4 I3 I2 I1

R_SD7

Q1 RLOC=R0C0.S0

RLOC=R2C0.S0 RLOC=R3C0.S0 M2_1 S2 D2 FMAP R S2 D2 L I4 I3 I2 I1 D0 D1 S0 FDCE O SD2 SD2 AND2B1 O R_SD2 RLOC=R2C0.S0 M2_1 S3 D3 D0 D1 S0 O SD3 SD3 AND2B1 FMAP R S1 D1 L I4 I3 I2 I1 M2_1 O R_SD1 S4 D4 D0 D1 S0 O SD4 SD4 AND2B1 RLOC=R3C0.S0 R_SD4 R_SD3 FDCE D Q CE C CLR Q3 R_SD2 D Q CE C CLR Q2

FMAP Q2 R S6 D6 L I4 I3 I2 I1

R_SD6

RLOC=R2C0.S0

RLOC=R0C0.S0

Q3 FMAP R S5 D5 L I4 I3 I2 I1

RLOC=R2C0.S0 FDCE D Q CE C CLR Q4

R_SD5

Q4

RLOC=R1C0.S0

RLOC=R1C0.S0 M2_1 FMAP R S0 D0 L I4 I3 I2 I1 S5 D5 D0 D1 S0 O SD5 SD5 AND2B1 O R_SD0 R_SD5 FDCE D Q CE C CLR Q5 FMAP Q5 R S4 D4 L I4 I3 I2 I1

R_SD4

RLOC=R1C0.S0 M2_1 S6 D6 D0 D1 S0 O SD6 SD6 AND2B1 R_SD6

RLOC=R3C0.S0

FDCE D Q CE C CLR Q6

RLOC=R1C0.S0

Q6

RLOC=R0C0.S0 M2_1 S7 D7 D0 D1 S0 O SD7 SD7 AND2B1 L CE R C OR3 R_L_CE RLOC=R0C0.S0 R_SD7 FDCE D Q CE C CLR Q7

Q7

X8689 GND

ACC8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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ACC4, 8, 16

Q [7:0]

CI

ADSU8
CI A [7:0] S [7:0] S [7:0] B [7:0] OFL CO ADD OFL CO RLOC=X1Y0

B [7:0]

ADD D [7:0]

M2_1
S0 D0 D0 D1 S0 SD0 AND2B1 O SD0 R_SD0 D

FDCE
Q Q0 CE C CLR Q0

M2_1 FMAP
R S3 D3 L I4 I3 I2 I1 O R_SD3 S1 D1 D0 D1 S0 SD1 AND2B1 O SD1 R_SD1

RLOC=X0Y0

FDCE
D CE C CLR Q1 Q Q1 R S7 D7 L I4 I3 I2 I1

FMAP
R_SD7

M2_1
RLOC=X0Y1 S2 D2 D0 D1 S0 SD2 AND2B1 O R_SD2 O SD2 R_SD2

RLOC=X0Y0

FDCE
D CE C R CLR Q2 S6 D6 L Q Q3 Q Q2

RLOC=X0Y3

FMAP
R S2 D2 L I4 I3 I2 I1 RLOC=X0Y1

FMAP
I4 I3 I2 I1 RLOC=X0Y3 O R_SD6

M2_1
S3 D3 D0 D1 S0 SD3 AND2B1 O SD3 R_SD3

RLOC=X0Y1

FDCE
D CE C CLR Q3

FMAP
R S1 D1 L I4 I3 I2 I1 RLOC=X0Y0 O R_SD1 S4 D4 D0 D1 S0 SD4 AND2B1

FMAP
R S5 D5 Q Q4 L I4 I3 I2 I1 RLOC=X0Y2 O R_SD5

M2_1
O SD4 R_SD4

RLOC=X0Y1

FDCE
D CE C CLR Q4

FMAP
R S0 D0 L I4 I3 I2 I1 RLOC=X0Y0 O R_SD0

M2_1
S5 D5 D0 D1 S0 SD5 AND2B1 O SD5 R_SD5

RLOC=X0Y2

FMAP
R I4 I3 I2 I1 RLOC=X0Y2 O R_SD4 Q5 S4 D4 L

FDCE
D CE C CLR Q5 Q

M2_1
S6 D6 D0 D1 S0 SD6 AND2B1 O SD6 R_SD6

RLOC=X0Y2

FDCE
D CE C CLR Q6 Q Q6

M2_1
S7 D7 L CE R C OR3 D0 D1 S0 SD7 AND2B1 R_L_CE O SD7 R_SD7

RLOC=X0Y3

FDCE
D CE C CLR Q7 RLOC=X0Y3 Q Q7

GND

X9301

ACC8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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ACC4, 8, 16

AND4B2 OFL_NEG_ADD CI AND2 CI_0 AND4B1 OFL_OUT OFL OR4 R OR2 R_0 Q3 S3 B3 ADD_1 L_0 OR2 GND VCC CE ADD AND2 AND2 CE_1 ADD_1 NOR2 AND3B2 AND2 Q0
C

AND4B2 OFL_POS_SUB

AND4B3 OFL_NEG_SUB

S0
D

FD
Q0

AND3 D0 AND3B2 AND3 AND3B1 KEEP X0 OR4 NOR2 OR2

S1
D

FD
Q1

NOR2

Q1

AND4B2

B0 XNOR2

AND3 BX0 S2
D

FD
Q2

AND4

OR3

NOR2

Q2

AND4 D1 AND3B2

AND3B1

KEEP X1 OR4 NOR2 AND3

AND4B2

B1 AND4 BX1 XNOR2 OR4 AND5 AND3B2

S3
D

FD
Q3

NOR2

Q3

D2

AND3B1

KEEP X2

AND5

AND4B2

OR4

NOR2 AND3

B2 XNOR2

BX2

AND4

CO AND5 OR5

D3

AND3B2 AND6 AND3B1 KEEP X3 OR4 NOR2

AND4B2

AND6 B3 C XNOR2 BX3

X7607

ACC4 Implementation XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II

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115

ACC4, 8, 16

ACC4X2
CI B0 B1 B2 B[7:0] B3 D0 D1 D2 D3 CI B0 B1 B2 B3 D0 D1 D2 D3 L ADD CE C R QO Q1 Q2 Q3 CO QO Q1 Q2 Q3

Q3_0

C3 Q[7:0]

ACC4
B4 B5 B6 B7 D4 D[7:0] L ADD CE C R D5 D6 D7 CI B0 B1 B2 B3 D0 D1 D2 D3 L ADD CE C R X7766 QO Q1 Q2 Q3 CO Q4 Q5 Q6 Q7 CO OFL

Q7_4 OFL

ACC8 Implementation XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II

Usage
ACC is schematic and inference only -- not instantiated.

VHDL Inference Code (ACC4)


Following is some "basic" code for inference of the ACC modules.
architecture Behavioral of acc4 is begin process(C) begin if (R = '1') then Q <= (others => '0'); elsif (C'event and C = '1') then if (L = '1') then Q <= D; elsif (CE = '1') then if (ADD = '1') then Q <= Q + B; else Q <= Q - B; end if; end if; end if;

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ACC4, 8, 16

end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) end if (ADD) Q <= Q + B; else Q <= Q - B; end

Commonly Used Constraints


None

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ACC4, 8, 16

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ADD1

ADD1
1-Bit Full Adder with Carry-In and Carry-Out
Architectures Supported
ADD1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CI A0 S0 B0 CO X4034

No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

ADD1 is a cascadable 1-bit full adder with carry-in and carry-out. It adds two 1-bit words (A and B) and a carry-in (CI), producing a binary sum (S0) output and a carryout (CO).

Inputs A0 0 1 0 1 0 1 0 1 B0 0 0 1 1 0 0 1 1 CI 0 0 0 0 1 1 1 1 S0 0 1 1 0 1 0 0 1

Outputs CO 0 0 0 1 0 1 1 1

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119

ADD1

A0 B0 CI AND2B1 OR2 AND2B1 XOR2

S0

AND2 CO AND2 OR3

AND2

X7689

ADD1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element is schematic or inference only -- no instantiation.

VHDL Inference Code


architecture Behavioral of ADD is signal sum: std_logic_vector(WIDTH downto 0); signal zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process (CI, A, B, sum) begin sum <= ('0' & A) + ('0' & B) + (zeros & CI); S <= sum(WIDTH-1 downto 0); CO <= sum(WIDTH); end process; end Behavioral;

Verilog Inference Code


always @ (A or B or CI) begin {CO,S} <= A + B + CI; end

Commonly Used Constraints


None

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ADD4, 8, 16

ADD4, 8, 16
4-, 8-, 16-Bit Cascadable Full Adders with Carry-In, Carry-Out, and Overflow
Architectures Supported
ADD4, ADD8, ADD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CI A0 A1 A2 A3 B0 B1 B2 B3

ADD4 S0 S1 S2 S3

ADD4, ADD8, and ADD16 add two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADD4 adds A3 A0, B3 B0, and CI producing the sum output S3 S0 and CO (or OFL). ADD8 adds A7 A0, B7 B0, and CI, producing the sum output S7 S0 and CO (or OFL). ADD16 adds A15 A0, B15 B0 and CI, producing the sum output S15 S0 and CO (or OFL).

OFL CO

Unsigned Binary Versus Twos Complement


ADD4, ADD8, ADD16 can operate on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers, respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twoscomplement operation is how they determine when overflow occurs. Unsigned binary uses CO, while twos-complement uses OFL to determine when overflow occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret the inputs as twos complement, follow the OFL output.

X4376

CI A[7:0] ADD8 B[7:0] OFL CO X4377 S[7:0]

CI A[15:0] ADD16 S[15:0] B[15:0] OFL CO X4378

Unsigned Binary Operation


For unsigned binary operation, ADD4 can represent numbers between 0 and 15, inclusive; ADD8 between 0 and 255, inclusive; ADD16 between 0 and 65535, inclusive. CO is active (High) when the sum exceeds the bounds of the adder. OFL is ignored in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ADD4 can represent numbers between -8 and +7, inclusive; ADD8 between -128 and +127, inclusive; ADD16 between -32768 and +32767, inclusive. OFL is active (High) when the sum exceeds the bounds of the adder. CO is ignored in twos-complement operation.

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121

ADD4, 8, 16

CO OFL
XOR2 O

B7 A7
XOR2

RLOC=R0C0.S1

I7

S MUXCY 0 1 CI DI
LI CI

FMAP
I4

O XORCY

S7

B7 A7

I3 I2 I1

I7

C6

RLOC=R0C0.S1

LO

O 1 CI

B6 A6
XOR2

RLOC=R0C0.S1

I6

MUXCY_D

FMAP
I4

0 DI

LI CI

O XORCY

S6

B6 A6

I3 I2 I1

I6

C5

RLOC=R0C0.S1

LO

B5 A5
XOR2

RLOC=R1C0.S1
1 CI
LI CI

I5

MUXCY_L 0 DI

FMAP
I4

B5 A5
O XORCY

I3 I2 I1

I5

S5

RLOC=R1C0.S1

C4

LO

B4 A4
XOR2

RLOC=R1C0.S1 B4 A4
LI CI

FMAP
I4 I3 I2 I1 0

I4

S MUXCY_L 0 1 CI DI

I4

O XORCY

S4 RLOC=R1C0.S1

C3

LO

B3 A3
XOR2

RLOC=R2C0.S1
1 CI
LI CI

FMAP
I4

I3

MUXCY_L 0 DI

B3 A3
O XORCY

I3 I2 I1

I3

S3

RLOC=R2C0.S1

C2

FMAP
LO

B2 A2
XOR2

RLOC=R2C0.S1
1 CI
LI CI

I2

MUXCY_L 0 DI

I4

B2 A2
O XORCY

I3 I2 I1

I2

S2

RLOC=R2C0.S1

C1

FMAP
LO

B1 A1
XOR2

RLOC=R3C0.S1
1 CI
LI CI

I4

I1

MUXCY_L 0 DI

B1 A1
O XORCY

I3 I2 I1

I1

S1

RLOC=R3C0.S1

C0

FMAP
B0 A0
XOR2

I0

LO MUXCY_L 0 DI 1 CI

RLOC=R3C0.S1 B0 A0
LI CI

I4 I3 I2 I1 0

I0

RLOC=R3C0.S1
O XORCY

A[7:0] B[7:0]

S0 S[7:0]

CI

X8687

ADD8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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ADD4, 8, 16

CO

OFL O B7 I7 A7 XOR2 S RLOC=X0Y3 MUXCY 0 1 DI CI I4 LI O CI C6 C6O XORCY S7 B7 A7 I3 I2 I1 RLOC=X0Y3 LO B6 I6 A6 XOR2 S O RLOC=X0Y3 MUXCY_D 0 1 DI CI LI O CI XORCY C5 LO B5 I5 A5 XOR2 S RLOC=X0Y2 MUXCY_L 0 1 DI CI LI O CI XORCY C4 LO B4 I4 A4 XOR2 S RLOC=X0Y2 MUXCY_L 0 1 DI CI LI O CI XORCY C3 LO B3 I3 A3 XOR2 S RLOC=X0Y1 MUXCY_L 0 1 DI CI LI O CI RLOC=X0Y1 XORCY C2 LO B2 I2 A2 XOR2 S RLOC=X0Y1 MUXCY_L 0 1 DI CI LI O CI XORCY C1 LO B1 I1 A1 XOR2 S RLOC=X0Y0 MUXCY_L 0 1 DI CI LI O CI XORCY C0 LO B0 I0 A0 A [7:0] B [7:0] XOR2 S RLOC=X0Y0 MUXCY_L 0 1 DI CI LI O CI XORCY S [7:0] CI S0 RLOC=X0Y0 B0 A0 I4 I3 I2 I1 O I0 S1 RLOC=X0Y0 B1 A1 I4 I3 I2 I1 O I1 S2 B2 A2 I4 I3 I2 I1 RLOC=X0Y1 O I2 S3 B3 A3 I4 I3 I2 I1 O I3 S4 B4 A4 I4 I3 I2 I1 RLOC=X0Y2 O I4 S5 B5 A5 I4 I3 I2 I1 RLOC=X0Y2 O I5 RLOC=X0Y3 S6 B6 A6 I4 I3 I2 I1 O I6 O I7 XOR2

FMAP

FMAP

FMAP

FMAP

FMAP

FMAP

FMAP

FMAP

X9302

ADD8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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123

ADD4, 8, 16

S3 A3 B3
AND3B2 OR2

OFL

AND3B1

S0
XOR2

S1
AND2 OR2 XOR2

AND2

AND2

S2
AND3 OR3 XOR2

CI
OR2

CI_ORO

AND3 GND

A0 KEEP X0 B0
XOR2 AND3 XOR2 OR4 AND2

S3

A1 KEEP X1 B1
XOR2 AND4 AND4

A2 KEEP X2
XOR2 AND2

B2

AND3

CO
AND4

OR5

A3 KEEP X3
XOR2 AND5

B3

AND5

X7613

ADD4 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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ADD4, 8, 16

S3_0 CI A0 A1 A2 A3 B0 B1 B2 B3

ADD4X2
CI A0 A1 A2 A3 B0 B1 B2 B3

S[7:0]
S0 S1 S2 S3

A[7:0]

S0 S1 S2 S3

B[7:0]

CO

C3

ADD4
CI

A4 A5 A6 A7 B4 B5 B6 B7

A0 A1 A2 A3 B0 B1 B2 B3

S0 S1 S2 S3

S4 S5 S6 S7

CO

CO

OFL CO

X7771

S7_4

ADD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element is schematic or inference only -- no instantiation.

VHDL Inference Code (ADD4)


architecture Behavioral of ADD is signal sum: std_logic_vector(WIDTH-1 downto 0); signal zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process (CI, A, B, sum) begin sum <= ('0' & A) + ('0' & B) + (zeros & CI); S <= sum(WIDTH-1 downto 0); CO <= sum(WIDTH); end process; end Behavioral;

Verilog Inference Code (ADD4)


always @ (A or B or CI) begin {CO,sum} <= A + B + CI; end

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ADD4, 8, 16

Commonly Used Constraints


None

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Libraries Guide ISE 6.li

ADSU1

ADSU1
1-Bit Cascadable Adder/Subtracter with Carry-In and Carry-Out
Architectures Supported
ADSU1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CI A0 S0 B0 ADD CO X4035

No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

When the ADD input is High, two 1-bit words (A0 and B0) are added with a carry-in (CI), producing a 1-bit output (S0) and a carry-out (CO). When the ADD input is Low, B0 is subtracted from A0, producing a result (S0) and borrow (CO). In add mode, CO represents a carry-out, and CO and CI are active-High. In subtract mode, CO represents a borrow, and CO and CI are active-Low. Add Function, ADD=1
Inputs A0 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 CI 0 0 0 0 1 1 1 1 S0 0 1 1 0 1 0 0 1 Outputs CO 0 0 0 1 0 1 1 1

Subtract Function, ADD=0


Inputs A0 0 0 1 1 0 B0 0 1 0 1 0 CI 0 0 0 0 1 S0 1 0 0 1 0 Outputs CO 0 0 1 0 1

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127

ADSU1

Subtract Function, ADD=0


Inputs A0 0 1 1
A0 B0 ADD AND3 CI

Outputs CI 1 1 1 S0 1 1 0 CO 0 1 1

B0 1 0 1

AND3

CO AND3B2 OR5

AND3B2

AND2 SO XOR2

AND3B3

AND3B1

OR4 AND3B1

AND3B1

X8144

ADSU1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of adsu4 is begin

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Libraries Guide ISE 6.li

ADSU1

process (A0,ADD,B0) begin if (ADD='1') then S <= A0 + B0; else S <= A0 - B0; end if; end process; end Behavioral;

Verilog Inference Code


always @ (A0 or ADD or B0) begin if (ADD) S0 <= A0 + B0; else S0 <= A0 - B0; end

VHDL Instantiation Template


-- Component Declaration for ADSU1 should be placed -- after architecture statement but before begin keyword component ADSU1 port (CO : out STD_ULOGIC; S0 : out STD_ULOGIC; A0 : in STD_ULOGIC; ADD: in STD_ULOGIC; B0 : in STD_ULOGIC; CI : in STD_ULOGIC); end component; -- Component Attribute specification for ADSU1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for ADSU1 should be placed -- in architecture after the begin keyword ADSU1_INSTANCE_NAME : ADSU1 -- synthesis translate_off generic map (CDS_ACTION => "string_value") -- synthesis translate_on port map (CO =>user_CO, S0 => user_SO, A0 => user_A0, ADD => user_ADD, B0 => user_B0, CI => user_CI);

Verilog Instantiation Template


ADSU1 instance_name (.CO (user_CO),

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129

ADSU1

.S0 (user_SO), .A0 (user_A0), .ADD(user_ADD), .B0 (user_B0), .CI (user_CI));

Commonly Used Constraints


None

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Libraries Guide ISE 6.li

ADSU4, 8, 16

ADSU4, 8, 16
4-, 8-, 16-Bit Cascadable Adders/Subtracters with Carry-In, Carry-Out, and Overflow
Architectures Supported
ADSU4, ADSU8, ADSU16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CI A0 A1 A2 A3 B0 B1 B2 B3 ADD OFL CO X4379 ADSU4 S0 S1 S2 S3

When the ADD input is High, ADSU4, ADSU8, and ADSU16 add two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow (OFL). ADSU4 adds two 4-bit words (A3 A0 and B3 B0) and a CI, producing a 4-bit sum output (S3 S0) and CO or OFL. ADSU8 adds two 8-bit words (A7 A0 and B7 B0) and a CI producing, an 8-bit sum output (S7 S0) and CO or OFL. ADSU16 adds two 16-bit words (A15 A0 and B15 B0) and a CI, producing a 16-bit sum output (S15 S0) and CO or OFL. When the ADD input is Low, ADSU4, ADSU8, and ADSU16 subtract Bz B0 from Az A0, producing a difference output and CO or OFL. ADSU4 subtracts B3 B0 from A3 A0, producing a 4-bit difference (S3 S0) and CO or OFL. ADSU8 subtracts B7 B0 from A7 A0, producing an 8-bit difference (S7 S0) and CO or OFL. ADSU16 subtracts B15 B0 from A15 A0, producing a 16-bit difference (S15 S0) and CO or OFL. In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High in add and subtract modes. ADSU4, ADSU8, and ADSU16 CI and CO pins do not use the CPLD carry chain.

CI A[7:0] ADSU8 S[7:0] B[7:0] ADD OFL CO X4380

Unsigned Binary Versus Twos Complement


ADSU4, ADSU8, ADSU16 can operate, respectively, on either 4-, 8-, 16-bit unsigned binary numbers or 4-, 8-, 16-bit twos-complement numbers. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputs are interpreted as twos complement, the output can be interpreted as twos complement. The only functional difference between an unsigned binary operation and a twos-complement operation is how they determine when overflow occurs. Unsigned binary uses CO, while twos complement uses OFL to determine when overflow occurs. With adder/subtracters, either unsigned binary or twos-complement operations cause an overflow. If the result crosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-out boundary, a carry-out is generated. The following figure shows the ADSU carry-out and overflow boundaries.

CI A[15:0] ADSU16 B[15:0] OFL ADD CO X4381 S[15:0]

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131

ADSU4, 8, 16

Overflow
-127
E N T OR SIG NE D ED BINAR GN Y SI

127 127
TW

128

OS

CO

UN

MPL EMENT O R

SIGN

ED BIN

LEM

AR

MP

CO

SI
G

0 0

-1

Carry-Out
X4720

ADSU Carry-Out and Overflow Boundaries

Unsigned Binary Operation


For unsigned binary operation, ADSU4 can represent numbers between 0 and 15, inclusive; ADSU8 between 0 and 255, inclusive; ADSU16 between 0 and 65535, inclusive. In add mode, CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is an active-Low borrow-out and goes Low when the difference exceeds the bounds. An unsigned binary overflow that is always active-High can be generated by gating the ADD signal and CO as follows.
unsigned overflow = CO XOR ADD

OFL is ignored in unsigned binary operation.

Twos-Complement Operation
For twos-complement operation, ADSU4 can represent numbers between -8 and +7, inclusive; ADSU8 between -128 and +127, inclusive; ADSU16 between -32768 and +32767, inclusive. If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignored in twos-complement operation.

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ED

255

TW

Libraries Guide ISE 6.li

ADSU4, 8, 16

CO OFL
XOR2 SUB7 O

RLOC=R0C0.S1

B7 A7

INV XOR3

I7

S MUXCY_L 0 1 DI CI LI CI

FMAP
ADD B7 A7
I4 I3 I2 I1 0

I7

S7

C6

XORCY

RLOC=R0C0.S1

SUB6

LO

O 1 CI

RLOC=R0C0.S1 ADD B6 A6

B6 A6

INV XOR3

I6

MUXCY_D

FMAP
I4 I3 I2 I1 0

0 DI

I6

LI CI

S6

C5

XORCY

RLOC=R0C0.S1

SUB5

LO

RLOC=R1C0.S1
1 CI LI CI

B5 A5

INV XOR3

I5

MUXCY_L 0 DI

FMAP
ADD B5 A5
I4 I3 I2 I1 0

I5

S5

RLOC=R1C0.S1

C4

XORCY

SUB4

LO

RLOC=R1C0.S1 ADD B4 A4
LI CI O

FMAP
I4 I3 I2 I1 0

B4 A4

INV XOR3

I4

S MUXCY_L 0 1 CI DI

I4

S4 RLOC=R1C0.S1

C3

XORCY

SUB3

LO

RLOC=R2C0.S1
1 CI LI CI

FMAP
ADD B3 A3
I4 I3 I2 I1 0

B3 A3

INV XOR3

I3

MUXCY_L 0 DI

I3

S3

RLOC=R2C0.S1

C2

XORCY

FMAP
SUB2 LO

RLOC=R2C0.S1
1 CI LI CI

B2 A2

INV XOR3

I2

MUXCY_L 0 DI

ADD B2 A2
O

I4 I3 I2 I1 0

I2

S2

RLOC=R2C0.S1

C1

XORCY

FMAP
SUB1 LO

RLOC=R3C0.S1
1 CI LI CI

B1 A1

INV XOR3

I1

MUXCY_L 0 DI

ADD B1 A1 S1

I4 I3 I2 I1 0

I1

RLOC=R3C0.S1

C0

XORCY

FMAP
SUB0

B0 A0 A[7:0] B[7:0] ADD CI

INV XOR3

I0

LO MUXCY_L 0 DI 1 CI

RLOC=R3C0.S1

ADD B0 A0

I4 I3 I2 I1 0

I0

RLOC=R3C0.S1
LI CI XORCY O

S0 S[7:0]

X8686

ADSU8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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133

ADSU4, 8, 16

CO

OFL XOR2 O SUB7 B7 A7 XOR3 INV I7 S MUXCY 0 1 DI CI I4 LI O CI XORCY C6 C6O RLOC=X1Y3 LO SUB6 B6 A6 XOR3 INV I6 S MUXCY_D 0 1 DI CI LI O CI XORCY C5 S6 ADD B6 A6 I4 I3 I2 I1 RLOC=X1Y3 O I6 O RLOC=X1Y3 S7 ADD B7 A7 I3 I2 I1 O I7 RLOC=X1Y3

FMAP

FMAP

LO SUB5 B5 A5 XOR3 INV I5 S MUXCY_L 0 1 DI CI ADD LI O CI XORCY C4 RLOC=X1Y2 S5 B5 A5 I4 I3 I2 I1 O I5 RLOC=X1Y2

FMAP

LO SUB4 B4 A4 XOR3 INV I4 S MUXCY_L 0 1 DI CI LI O CI XORCY C3 S4 ADD B4 A4 RLOC=X1Y2 I4 I3 I2 I1 RLOC=X1Y2 O I4

FMAP

LO SUB3 B3 A3 XOR3 INV I3 S MUXCY_L 0 1 DI CI LI O CI XORCY C2 S3 ADD B3 A3 RLOC=X1Y1 I4 I3 I2 I1 RLOC=X1Y1 O I3

FMAP

LO SUB2 B2 A2 XOR3 INV I2 S MUXCY_L 0 1 DI CI LI O CI XORCY C1 S2 RLOC=X1Y1 I4 ADD B2 A2 I3 I2 I1

FMAP

I2

RLOC=X1Y1

LO SUB1 B1 A1 XOR3 INV I1 S MUXCY_L 0 1 DI CI LI O CI XORCY C0 S1 RLOC=X1Y0 ADD B1 A1 I4 I3 I2 I1

FMAP

I1

RLOC=X1Y0

FMAP
LO SUB0 B0 A0 XOR3 A [7:0] LI O B [7:0] CI XORCY ADD S [7:0] S0 INV I0 S MUXCY_L 0 1 DI CI RLOC=X1Y0 I4 ADD B0 A0 I3 I2 I1 RLOC=X1Y0 O I0

CI

X9303

ADSU8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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ADSU4, 8, 16

CI A0 B0

ADSU1
CI A0 S0 B0 ADD CO

S0

S0

ADSU1 A1 B1
CI A0 S0 B0 ADD CO

S1

S1

ADSU1 A2 B2
CI A0 S0 B0 ADD CO

S2

OFL_POS_ADD

S2
AND4B2

ADSU1 A3 B3
CI A0 S0 B0 ADD CO

OFL_NEG_ADD OFL_OUT
AND4B1 OR4

S3

OFL

S3

CO
AND4B2

OFL_POS_SUB
ADD
AND4B3

OFL_NEG_SUB
X7615

ADSU4 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II


S3_0 CI A0 A1 A2 A3 B0 B1 B2 B3

ADSU4X2
CI A0 A1 A2 A3 B0 B1 B2 B3 CO ADD

S[7:0]
S0 S1 S2 S3

A[7:0]

S0 S1 S2 S3

B[7:0]

C3

ADSU4
CI

A4 A5 A6 A7 B4 B5 B6 B7 ADD

A0 A1 A2 A3 B0 S0 S1 S2 S3

S4 S5 S6 S7

B1 B2 OFL B3 CO ADD

OFL CO
X7774

S7_4

ADSU8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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ADSU4, 8, 16

Usability
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of adsu4 is begin process (A,ADD,B) begin if (ADD='1') then S <= A + B; else S <= A - B; end if; end process; end Behavioral;

Verilog Inference Code


always @ (A or ADD or B) begin if (ADD) S <= A + B; else S <= A - B; end

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AND2-9

AND2-9
2- to 9-Input AND Gates with Inverted and Non-Inverted Inputs
Architectures Supported
AND2, AND3, AND4, AND5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive Primitive

AND2B1, AND2B2, AND4B1, AND4B2, AND4B3, AND4B4, AND5B1, AND5B2, AND5B3, AND5B4, AND5B5 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II AND3B1, AND3B2, AND3B3, Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II AND6, AND7, AND8, AND9 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Primitive Primitive Primitive Macro Macro Macro Macro Macro Macro Macro Primitive Primitive Primitive Primitive Macro Macro Macro

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137

AND2-9

I1 I0

I2 I1 I0

I3 O I2 I1 I0 O

I4 I3 I2 I1 I0 O

I5 I4 I3 I2 I1 I0 AND5 I6 I5 I4 O I3 I2 I1 I0 O AND6 O

AND2

AND3

AND4

I4 I1 I0 O I2 I1 I0 I3 O I2 I1 I0 O I3 I2 I1 I0

AND2B1

AND3B1

AND4B1 I4 I3 O I2 I1 I0 AND4B2 I3 I4 I3 O I2 I1 I0 AND4B3 I4 I3 O I2 I1 I0 AND4B4

AND5B1

AND7

I1 I0

I2 I1 I0

I3 O I2 I1 I0

O I7 I6 I5 AND5B2 I4 I3 I2 O I1 I0

AND2B2

AND3B2

I2 I1 I0

I2 I1 I0

AND3B3

AND5B3

AND8

I3 I2 I1 I0

O I8 I7 AND5B4 I6 I5 I4 O I3 I2 O I1 I0

I4 I3 I2 I1 I0 AND5B5

AND9 X9461

AND Gate Representations AND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. AND functions of six to nine inputs are available with only noninverting inputs. To make some or all inputs inverting, use external inverters. Because each input uses a CLB resource in Spartan-II, Spartan-3, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X replace functions with unused inputs with functions having the appropriate number of inputs. See AND12, 16 for information on additional AND functions for Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, and Spartan-3.

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AND2-9

FMAP
I4 I3 S1 S0 I7 I6 I5 I4 AND4 I7 O AND2 I3 I2 I1 I0 AND4 S0 I6 I5 I4 S1 I2 I1 RLOC=R0C0.S0 O O

FMAP
I4 I3 I2 I1 RLOC=R0C0.S1 O S1

FMAP
I3 I2 I1 I0 X8702 I4 I3 I2 I1 RLOC=R0C0.S1 O S0

AND8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

FMAP
I4 I7 I6 I5 I4 AND4 O RLOC=X0Y1 S1 S1 S0 I3 I2 I1 O O

FMAP
AND2 I3 I2 I1 I0 AND4 S0 I7 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1

FMAP
I3 I2 I1 I0 I4 I3 I2 I1 RLOC=X0Y0 O S0

X9304

AND8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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AND2-9

Usage
If possible, it is recommended that these design elements be inferred rather than instantiated.

VHDL Inference Code


AND2 example:
process (I0, I1) begin O <= I0 and I1; end process;

AND5B3 example:
process (I0, I1, I2, I3, I4) begin O <= (not I0) and (not I1) and (not I2) and I3 and I4; end process;

Verilog Inference Code


AND2:
always @ (I0 or I1) begin O <= I0 && I1; end

AND5B3:
always @ (I0 or I1 or I2 or I3 or I4) begin O <= !I0 && !I1 && !I2 && I3 && I4; end

VHDL Instantiation Template for AND2, AND2B1, or AND2B2


-- Component Declaration for AND2, AND2B1, or AND2B2 should -- be placed after architecture statement but before begin -- keyword component {AND2|AND2B1|AND2B2} port (O : out STD_ULOGIC; I1 : in STD_ULOGIC; I0 : in STD_ULOGIC); end component; -- Component Attribute specification for AND2, AND2B1, or -- AND2B2 should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here

-- Component Instantiation for AND2, AND2B1, or AND2B2 -- should be placed in architecture after the begin -- keyword

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AND2-9

INSTANCE_NAME : {AND2|AND2B1|AND2B2} port map (O => user_O, I0 => user_I0, I1 => user_I1);

Verilog Instantiation Template for AND2, AND2B1, or AND2B2


ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1));

VHDL Instantiation Template for AND3 Through AND3B3


-- Component Declaration for AND3 through AND3B3 should -- be placed after architecture statement but before begin -- keyword component {AND3|AND3B1|AND3B2|AND3B3} port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC); end component; -- Component Attribute specification for AND3 through AND3B3 -- should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here -- Component Instantiation for AND3 through AND3B3 -- should be placed in architecture after the begin -- keyword INSTANCE_NAME : {AND3|AND3B1|AND3B2|AND3B3} port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2);

Verilog Instantiation Template for AND3 Through AND3B3


ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2));

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AND2-9

VHDL Instantiation Template for AND4 Through AND4B4


-- Component Declaration for AND4 through AND4B4 should -- be placed after architecture statement but before begin -- keyword component {AND4|AND4B1|AND4B2|AND4B3|AND4B4} port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component; -- Component Attribute specification for AND4 through AND4B4 -- should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here -- Component Instantiation for AND4 through AND4B4 -- should be placed in architecture after the begin -- keyword INSTANCE_NAME : AND4_thru_AND4B4 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3);

Verilog Instantiation Template for AND4 through AND4B4


ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3));

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AND2-9

VHDL Instantiation Template for AND5 Through AND5B5


-- Component Declaration for AND5 through AND5B5 should -- be placed after architecture statement but before begin -- keyword component {AND5|AND5B1|AND5B2|AND5B3|AND5B4|AND5B5} port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC; I4 : in STD_ULOGIC); end component; -- Component Attribute specification for AND5 through AND5B5 -- should be placed after architecture declaration -- but before the begin keyword -- Enter attributes here -- Component Instantiation for AND5 through AND5B5 -- should be placed in architecture after the begin -- keyword INSTANCE_NAME : AND5_thru_AND5B5 port map (O => user_O, I0 => user_I0, I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4);

Verilog Instantiation Template for AND5 through AND5B5


ANDn instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4));

Commonly Used Constraints


None

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AND2-9

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AND12, 16

AND12, 16
12- and 16-Input AND Gates with Non-Inverted Inputs
Architectures Supported
AND12, AND16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 AND12

AND12 and AND16 functions are performed in the Configurable Logic Block (CLB) function generator.
O

The 12- and 16-input AND functions are available only with non-inverting inputs. To invert all of some inputs, use external inverters. See AND2-9 for information on more AND functions.
FMAP
S2 S1 S0 I4 I3 I2 I1 RLOC=R0C0.S0 O O

X9459

I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 AND16

I11 I10 I9 I8 AND4 I7 I6 I5 I4 AND4 I3 I2 I1 I0 AND4 S0

FMAP
S2 I11 I10 I9 I8 I4 I3 I2 I1 RLOC=R0C0.S0 O S2

S1 AND3

FMAP
I7 I6 I5 I4 I4 I3 I2 I1 RLOC=R0C0.S1 O S1

X9460

FMAP
I3 I2 I1 I0 X8705 I4 I3 I2 I1 RLOC=R0C0.S1 O S0

AND12 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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AND12, 16

FMAP
I11 I10 I9 I8 AND4 S2 S2 S1 S0 I4 I3 I2 I1 RLOC=X0Y1 O O

FMAP
I11 I7 I6 I5 I4 AND4 AND3 S1 O I10 I9 I8 I4 I3 I2 I1 RLOC=X0Y1 O S2

FMAP
I7 I3 I2 I1 I0 AND4 S0 I6 I5 I4 I4 I3 I2 I1 RLOC=X0Y0 O S1

FMAP
I3 I2 I1 I0 I4 I3 I2 I1 RLOC=X0Y0 X9305 O S0

AND12 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


O

FMAP I15 I14 I13 I12 AND4 RLOC=R0C0.S1 C2 FMAP I11 I10 I9 I8 AND4 RLOC=R0C0.S1 C1 FMAP I7 I6 I5 I4 AND4 C0 RLOC=R1C0.S1 S1 LO MUXCY_L S 0 DI 1 CI I4 RLOC=R1C0.S1 I7 I6 I5 I4 I3 O I2 I1 S1 S2 LO MUXCY_L S 0 DI 1 CI RLOC=R0C0.S1 I11 I10 I9 I8 I4 I3 O I2 I1 S2 S3 S 0 DI 1 CI I12 O MUXCY RLOC=R0C0.S1 I15 I14 I13 I4 I3 O I2 I1 S3

FMAP I3 I2 I1 I0 AND4 S0 LO MUXCY_L S 0 DI 1 CI RLOC=R1C0.S1 I3 I2 I1 I0 I4 I3 O I2 I1 RLOC=R1C0.S1 S0

CIN GND VCC

X8708

AND16 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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AND12, 16

FMAP
I15 I14 I13 I12 AND4 C2 RLOC=X0Y1 S3 S O MUXCY 0 1 DI CI RLOC=X0Y1 I15 I14 I13 I12 I4 I3 I2 I1 O S3

I11 I10 I9 I8 AND4 S2 S

LO MUXCY_L 0 1 DI CI RLOC=X0Y1

FMAP
I11 I10 I9 I8 C1 I4 I3 I2 I1 RLOC=X0Y1 O S2

I7 I6 I5 I4 AND4 S1 S

LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I7 I6 I5 I4 C0

FMAP
I4 I3 I2 I1 RLOC=X0Y0 O S1

I3 I2 I1 I0 AND4 S0 S

LO MUXCY_L 0 1 DI CI RLOC=X0Y0 I3 I2 I1 I0 CIN GND VCC

FMAP
I4 I3 I2 I1 RLOC=X0Y0 O S0

X9306

AND16 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, it is recommended that these design elements be inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of and12 is begin process (I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11) begin O <= I0 and I1 and I2 and I3 and I4 and I5 and I6 and I7 and I8 and I9 and I10 and I11; end process;

end Behavioral;

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AND12, 16

Verilog Inference Code


always @ (I0 or I1 or I2 or I3 or or I6 or I7 or I8 or I9 or I10 begin O <= I0 && I1 && I2 && I3 && I4 && I6 && I7 && I8 && I9 && I10 end I4 or I5 or I11) && I5 && I11;

Commonly Used Constraints


None

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BRLSHFT4, 8

BRLSHFT4, 8
4-, 8-Bit Barrel Shifters
Architectures Supported
BRLSHFT4, BRLSHFT8 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

I0 I1 I2 I3 S0 S1

BRLSHFT4

O0 O1 O2 O3

BRLSHFT4, a 4-bit barrel shifter, can rotate four inputs (I3 I0) up to four places. The control inputs (S1 and S0) determine the number of positions, from one to four, that the data is rotated. The four outputs (O3 O0) reflect the shifted data inputs. BRLSHFT8, an 8-bit barrel shifter, can rotate the eight inputs (I7 I0) up to eight places. The control inputs (S2 S0) determine the number of positions, from one to eight, that the data is rotated. The eight outputs (O7 O0) reflect the shifted data inputs.

X3856

I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2

BRLSHFT8 O0
O1 O2 O3 O4 O5 O6 O7

BRLSHFT4 Truth Table


Inputs S1 0 0 1 1 S0 0 1 0 1 I0 a a a a I1 b b b b I2 c c c c I3 d d d d O0 a b c d Outputs O1 b c d a O2 c d a b O3 d a b c

X3857

BRLSHFT8 Truth Table


Inputs S2 S1 S0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 I0 a a a a a a I1 b b b b b b I2 c c c c c c I3 d d d d d d I4 e e e e e e I5 f f f f f f I6 g g g g g g I7 h h h h h h Outputs O0 O1 O2 O3 O4 O5 O6 O7 a b c d e f b c d e f g c d e f g h d e f g h a e f g h a b f g h a b c g h a b c d h a b c d e

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BRLSHFT4, 8

BRLSHFT8 Truth Table


Inputs S2 S1 S0 1 1 1 1 0 1 I0 a a I1 b b I2 c c I3 d d I4 e e I5 f f I6 g g I7 h h Outputs O0 O1 O2 O3 O4 O5 O6 O7 g h h a a b b c c d d e e f f g

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BRLSHFT4, 8

I0

D0 D1 S0

M2_1
O M01 M01 D0 D1 S0

M2_1
O MO0 MO0 D0 D1 S0

M2_1
O O0 O0

I1

D0 D1 S0

M2_1
O M12 M12 D0 D1 S0

M2_1
O MO1 MO1 D0 D1 S0

M2_1
O O1 O1

I2

D0 D1 S0

M2_1
O M23 M23 D0 D1 S0

M2_1
O MO2 MO2 D0 D1 S0

M2_1
O O2 O2

I3

D0 D1 S0

M2_1
O M34 M34 D0 D1 S0

M2_1
O MO3 MO3 D0 D1 S0

M2_1
O O3 O3

I4

M2_1
D0 D1 S0 O M45 M45 D0 D1 S0

M2_1
O MO4 MO4 D0 D1 S0

M2_1
O O4 O4

I5

D0 D1 S0

M2_1
O M56 M56 D0 D1 S0

M2_1
O MO5 MO5 D0 D1 S0

M2_1
O O5 O5

I6

D0 D1 S0

M2_1
O M67 M67 D0 D1 S0

M2_1
O MO6 MO6 D0 D1 S0

M2_1
O O6 O6

I7 S0 S1 S2

D0 D1 S0

M2_1
O M70 M70 D0 D1 S0

M2_1
O MO7 MO7 D0 D1 S0

M2_1
O O7 X8143 O7

BRLSHFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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BRLSHFT4, 8

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of brlshft4 is begin process (I,S) begin case S is when "00" => O <= I; when "01" => O(3) <= I(0); O(2 downto 0) when "10" => O(3 downto 2) O(1 downto 0) when "11" => O(3 downto 1) O(0) <= I(3); when others => O <= I; end case; end process; end Behavioral;

<= I(3 downto 1); <= I(1 downto 0); <= I(3 downto 2); <= I(2 downto 0);

Verilog Inference Code


always @(I or S) begin case (S) 2'b00 2'b01 2'b10 2'b11 endcase end : : : : O O O O <= <= <= <= I; {I[0],I[3:1]}; {I[1:0],I[3:2]}; {I[2:0],I[3]};

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BSCAN_SPARTAN2

BSCAN_SPARTAN2
Spartan-II Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_SPARTAN2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

* Supported for Spartan-II, but not for SpartanIIE, which is supported by BSCAN_VIRTEX.

BSCAN_SPARTAN2
UPDATE SHIFT RESET TDI SEL1 DRCK1 TDO1 TDO2 SEL2 DRCK2

The BSCAN_SPARTAN2 symbol creates internal boundary scan chains in a Spartan-II device. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Spartan-II. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_SPARTAN2 symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, and SHIFT pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain. Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Book.

X8894

Usage
This design element is supported for instantiation and schematics but not for inference.

VHDL Instantiation Template


-- Component Declaration for BSCAN_SPARTAN2 should be placed -- after architecture statement but before begin keyword component BSCAN_SPARTAN2 port (DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC;

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BSCAN_SPARTAN2

SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC; TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_SPARTAN2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BSCAN_SPARTAN2 should be -- placed in architecture after the begin keyword BSCAN_SPARTAN2_INSTANCE_NAME : BSCAN_SPARTAN2 port map (DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

Verilog Instantiation Template


BSCAN_SPARTAN2 instance_name (.DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

Commonly Used Constraints


None

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BSCAN_SPARTAN3

BSCAN_SPARTAN3
Spartan-3 Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_SPARTAN3 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

BSCAN_SPARTAN3 UPDATE SHIFT RESET TDI SEL1 DRCK1 TD01 TD02 SEL2 DRCK2 CAPTURE

BSCAN_SPARTAN3 provides access to the BSCAN sites on a Spartan-3 device. It is used to create internal boundary scan chains. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Spartan-3. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_SPARTAN3 symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain.

X9930

Usage
This design element is instantiated rather than inferred.

VHDL Instantiation Template


-- Component Declaration for BSCAN_SPARTAN3 should be placed -- after architecture statement but before begin keyword component BSCAN_SPARTAN3 port (CAPTURE : out STD_ULOGIC; DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC;

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BSCAN_SPARTAN3

TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_SPARTAN3 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BSCAN_SPARTAN3 should be -- placed in architecture after the begin keyword BSCAN_SPARTAN3_INSTANCE_NAME : BSCAN_SPARTAN3 port map (CAPTURE => user_CAPTURE, DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

Verilog Instantiation Template


BSCAN_SPARTAN3 instance_name (.CAPTURE (user_CAPTURE), .DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

Commonly Used Constraints


None.

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BSCAN_VIRTEX

BSCAN_VIRTEX
Virtex Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_VIRTEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No Primitive No No No No

* Supported for Spartan-IIE, but not for Spartan-II, which is supported by BSCAN_SPARTAN2.

BSCAN_VIRTEX
UPDATE SHIFT RESET TDI SEL1 DRCK1 TDO1 TDO2 SEL2 DRCK2

The BSCAN_VIRTEX symbol is used to create internal boundary scan chains in a Virtex or Virtex- E device. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Virtex and Virtex-E. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_VIRTEX symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. Note: For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, see BSCAN_VIRTEX2. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, and SHIFT pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain. Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Book.

X8679

Usage
This design element is supported for instantiation and schematics but not for inferrence.

VHDL Instantiation Template


-- Component Declaration for BSCAN_VIRTEX should be placed -- after architecture statement but before begin keyword component BSCAN_VIRTEX port (DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC;

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BSCAN_VIRTEX

RESET : out STD_ULOGIC; SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC; TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_VIRTEX -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BSCAN_VIRTEX should be -- placed in architecture after the begin keyword BSCAN_VIRTEX_INSTANCE_NAME : BSCAN_VIRTEX port map (DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

Verilog Instantiation Template


BSCAN_VIRTEX instance_name (.DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

Commonly Used Constraints


None

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BSCAN_VIRTEX2

BSCAN_VIRTEX2
Virtex-II Boundary Scan Logic Control Circuit
Architectures Supported
BSCAN_VIRTEX2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

BSCAN_VIRTEX2 UPDATE SHIFT RESET TDI SEL1 DRCK1 TD01 TD02 SEL2 DRCK2 CAPTURE

BSCAN_VIRTEX2 provides access to the BSCAN sites on a Virtex-II, Virtex-II Pro, or Virtex-II Pro X device. It is used to create internal boundary scan chains. The 4-pin JTAG interface (TDI, TDO, TCK, and TMS) are dedicated pins in Virtex-II, Virtex-II Pro, and Virtex-II Pro X. To use normal JTAG for boundary scan purposes, just hook up the JTAG pins to the port and go. The pins on the BSCAN_VIRTEX2 symbol do not need to be connected, unless those special functions are needed to drive an internal scan chain. Note: For Virtex and Virtex-E, see BSCAN_VIRTEX. A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; the SEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 access to the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generated by the TAP controller). The RESET, UPDATE, SHIFT, and CAPTURE pins represent the decoding of the corresponding state of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain. Note: For specific information on boundary scan for an architecture, see The Programmable
Logic Data Book.

X9402

Usage
This design element is supported for instantiation and schematics but not for inference.

VHDL Instantiation Template


-- Component Declaration for BSCAN_VIRTEX2 should be placed -- after architecture statement but before begin keyword component BSCAN_VIRTEX2 port (CAPTURE : out STD_ULOGIC; DRCK1 : out STD_ULOGIC; DRCK2 : out STD_ULOGIC; RESET : out STD_ULOGIC;

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BSCAN_VIRTEX2

SEL1 : out STD_ULOGIC; SEL2 : out STD_ULOGIC; SHIFT : out STD_ULOGIC; TDI : out STD_ULOGIC; UPDATE : out STD_ULOGIC; TD01 : in STD_ULOGIC; TD02 : in STD_ULOGIC); end component; -- Component Attribute specification for BSCAN_VIRTEX2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BSCAN_VIRTEX2 should be -- placed in architecture after the begin keyword BSCAN_VIRTEX2_INSTANCE_NAME : BSCAN_VIRTEX2 port map (CAPTURE => user_CAPTURE, DRCK1 => user_DRCK1, DRCK2 => user_DRCK2, RESET => user_RESET, SEL1 => user_SEL1, SEL2 => user_SEL2, SHIFT => user_SHIFT, TDI => user_TDI, UPDATE => user_UPDATE, TD01 => user_TD01, TD02 => user_TD02);

Verilog Instantiation Template


BSCAN_VIRTEX2 instance_name (.CAPTURE (user_CAPTURE), .DRCK1 (user_DRCK1), .DRCK2 (user_DRCK2), .RESET (user_RESET), .SEL1 (user_SEL1), .SEL2 (user_SEL2), .SHIFT (user_SHIFT), .TDI (user_TDI), .UPDATE (user_UPDATE), .TD01 (user_TD01), .TD02 (user_TD02));

Commonly Used Constraints


None

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BUF

BUF
General-Purpose Buffer
Architectures Supported
BUF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

O X9444

BUF is a general purpose, non-inverting buffer. In Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, BUF is usually not necessary and is removed by the partitioning software (MAP). In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUF is usually removed, unless you inhibit optimization by applying the OPT=OFF attribute to the BUF symbol.

Usage
This design is supported in schematics and instantiation but not for inference.

VHDL Instantiation Template


-- Component Declaration for BUF should be placed -- after architecture statement but before begin keyword component BUF port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUF -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUF should be placed -- in architecture after the begin keyword BUF_INSTANCE_NAME : BUF port map (O => user_O, I => user_I);

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BUF

Verilog Instantiation Template


BUF instance_name (.O (user_O), .I (user_I));

Commonly Used Constraints


None

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BUF4, 8, 16

BUF4, 8, 16
General-Purpose Buffers
Architectures Supported
BUF4, BUF8, BUF16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

BUF4

BUF4, 8, 16 are general purpose, non-inverting buffers. In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUF4, BUF8, and BUF16 are usually removed, unless you inhibit optimization by applying the OPT=OFF attribute to the BUF4, BUF8, or BUF16 symbol or by using the LOGIC_OPT=OFF global attribute.
O [7:0] X4614 I0 0 BUF 1 BUF 2 BUF 3 BUF 4 BUF 5 BUF 6 BUF 7 BUF X 7776 O1

BUF8

I1

O1

I2 X4615

O2

I3

O3

I4

O4

BUF16
I5

O5

I6 X4616 I7 I[7:0]

O6

O7

BUF8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
These design elements are schematic only.

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BUF4, 8, 16

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BUFCF

BUFCF
Fast Connect Buffer
Architectures Supported
BUFCF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

O X9444

BUFCF is a single fast connect buffer used to connect the outputs of the LUTs and some dedicated logic directly to the input of another LUT. Using this buffer implies CLB packing. No more than four LUTs may be connected together as a group.

Usage
This design element is supported for schematics and instantiation but not for inferrence.

VHDL Instantiation Template


-- Component Declaration for BUFCF should be placed -- after architecture statement but before begin keyword component BUFCF port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFCF -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFCF should be placed -- in architecture after the begin keyword BUFCF_INSTANCE_NAME : BUFCF port map (O => user_O, I => user_I);

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BUFCF

Verilog Instantiation Template


BUFCF instance_name (.O (user_O), .I (user_I));

Commonly Used Constraints


None

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BUFE, 4, 8, 16

BUFE, 4, 8, 16
Internal 3-State Buffers with Active High Enable
Architectures Supported
BUFE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II BUFE4, BUFE8, BUFE16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro Macro* No No Primitive No Primitive Primitive No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

*Not supported for XC9500XL and XC9500XV devices

BUFE
E

X3790

BUFE, BUFE4, BUFE8, and BUFE16 are single or multiple 3-state buffers with inputs I, I3 I0, I7 I0, and I15 I0, respectively; outputs O, O3 O0, O7 O0, and O15 O0, respectively; and active-High output enable (E). When E is High, data on the inputs of the buffers is transferred to the corresponding outputs. When E is Low, the output is high impedance (Z state or Off). The outputs of the buffers are connected to horizontal longlines in FPGA architectures. The outputs of separate BUFE symbols can be tied together to form a bus or a multiplexer. Make sure that only one E is High at any one time. If none of the E inputs is active-High, a weak-keeper circuit (Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X) keeps the output bus from floating but does not guarantee that the bus remains at the last value driven onto it. For XC9500 devices, BUFE output nets assume the High logic level when all connected BUFE/BUFT buffers are disabled. For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, BUFE elements need a PULLUP element connected to their output. NGDBuild inserts a PULLUP element if one is not connected.

BUFE4
E

X3797

BUFE8
EE

BUFE16

X3809

X3821

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BUFE, 4, 8, 16

Inputs E 0 1 1 I X 1 0

Outputs O Z 1 0

O[7:0] E I0 E I1 E I2 E I3 E I4 E I5 E I6 E I7 BUFE I[7:0] E X8119 BUFE O7 BUFE O6 BUFE O5 BUFE O4 BUFE O3 BUFE O2 BUFE O1 O0

BUFE8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
These design elements are supported for schematic, inference, and instantiation.

VHDL Inference Code


architecture Behavioral of bufe is begin process (I, E) begin if (E = '1') then O <= I; else O <= 'Z'; end if; end process; end Behavioral;

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BUFE, 4, 8, 16

Verilog Inference Code


always @ (I or E) begin if (E) O <= I; else O <= 1'bZ; end

VHDL Instantiation Template


-- Component Declaration for BUFE should be placed -- after architecture statement but before begin keyword component BUFE port (O : out STD_ULOGIC; E : in STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFE should be placed -- in architecture after the begin keyword BUFE_INSTANCE_NAME : port map (O => E => I => BUFE user_O, user_E, user_I);

Verilog Instantiation Template


BUFE instance_name (.O (user_O), .E (user_E), .I (user_I));

Commonly Used Constraints


None

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BUFE, 4, 8, 16

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BUFG

BUFG
Global Clock Buffer
Architectures Supported
BUFG Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

O X9428

BUFG, an architecture-independent global buffer, distributes high fan-out clock signals throughout a PLD device. The Xilinx implementation software converts each BUFG to an appropriate type of global buffer for the target PLD device. To use a specific type of buffer, instantiate it manually. To use a BUFG in a schematic, connect the input of the BUFG symbol to the clock source. Depending on the target PLD family, the clock source can be an external PAD symbol, an IBUF symbol, or internal logic. For a negative-edge clock input, insert an INV (inverter) symbol between the BUFG output and the clock input. The inversion is implemented at the Configurable Logic Block (CLB) or Input Output Block (IOB) clock pin.

XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II


Consult the device data sheet for the number of available global pins. For these architectures BUFG is always implemented using an IOB. Connect the input of BUFG to an IPAD or an IOPAD that represents an external signal source. Each BUFG can drive any number of register clocks in a design. The output of a BUFG may also be used as an ordinary input signal to other logic elsewhere in the design.

Virtex, Virtex-E, Spartan-II, Spartan-IIE


In Virtex, Virtex-E, Spartan-II, and Spartan-IIE, the BUFG cannot be driven directly from a pad. It can be driven from an IBUFG to indicate to use the dedicated pin (GCLKIOB pin) or from an internal driver to create an internal clock. BUFG can also be driven with an IBUF to represent an externally driven clock that does not use the dedicated pin.

Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, clock buffers are multiplexed clock buffers. In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, a BUFG is implemented using a BUFGMUX with the S_B input tied high, basically meaning the S input is tied low. I1 is unused. I0 is used.

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BUFG

Usage
This design element is supported for schematic and instantiation. Synthesis tools usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the synthesis tool usually instantiates BUFGPs for the clocks that are most utilized. The BUFGP contains both a BUFG and an IBUFG.

VHDL Instantiation Template


-- Component Declaration for BUFG should be placed -- after architecture statement but before begin keyword component BUFG port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFG -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFG should be placed -- in architecture after the begin keyword BUFG_INSTANCE_NAME : BUFG port map (O => user_O, I => user_I);

Verilog Instantiation Template


BUFG instance_name (.O (user_O), .I (user_I));

Commonly Used Constraints


LOC

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BUFGCE

BUFGCE
Global Clock MUX Buffer with Clock Enable and Output State 0
Architectures Supported
BUFGCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

CE I O

BUFGCE is a global clock buffer with a single gated input. Its O output is "0" when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.

BUFGCE
X9384

Inputs I X I CE 0 1

Outputs O 0 I

BUFGMUX
I XGND CE INV GND X9307 CE_IN I0 I1 S O O

BUFGCE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This design element is supported for schematics and instantiations but not for inference.

VHDL Instantiation Template


-- Component Declaration for BUFGCE should be placed -- after architecture statement but before begin keyword component BUFGCE port (O : out STD_ULOGIC; CE : in STD_ULOGIC; I : in STD_ULOGIC); end component;

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BUFGCE

-- Component Attribute specification for BUFGCE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFGCE should be placed -- in architecture after the begin keyword BUFGCE_INSTANCE_NAME : BUFGCE port map (O => user_O, CE => user_CE, I => user_I);

Verilog Instantiation Template


BUFGCE instance_name (.O (user_O), .CE (user_CE), .I (user_I));

Commonly Used Constraints


LOC

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BUFGCE_1

BUFGCE_1
Global Clock MUX Buffer with Clock Enable and Output State 1
Architectures Supported
BUFGCE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CE I O

No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

BUFGCE_1
X9385

BUFGCE_1 is a multiplexed global clock buffer with a single gated input. Its O output is High (1) when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.

Inputs I X I CE 0 1

Outputs O 1 I

BUFGMUX_1
I XVCC CE INV VCC X9308 CE_IN I0 I1 S O O

BUFGCE_1 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
This design element is supported for schematics and instantiations but not for inference.

VHDL Instantiation Template


-- Component Declaration for BUFGCE_1 should be placed -- after architecture statement but before begin keyword component BUFGCE_1 port (O : out STD_ULOGIC; CE : in STD_ULOGIC; I: in STD_ULOGIC); end component;

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BUFGCE_1

-- Component Attribute specification for BUFGCE_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFGCE_1 should be placed -- in architecture after the begin keyword BUFGCE_1_INSTANCE_NAME : BUFGCE_1 port map (O => user_O, CE => user_CE, I => user_I);

Verilog Instantiation Template


BUGCE_1 instance_name (.O (user_O), .CE (user_CE), .I (user_I));

Commonly Used Constraints


LOC

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BUFGDLL

BUFGDLL
Clock Delay Locked Loop Buffer
Architectures Supported
BUFGDLL Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

BUFGDLL
RST I LOCKED O

BUFGDLL is a special purpose clock delay locked loop buffer for clock skew management. It is provided as a user convenience for the most frequently used configuration of elements for clock skew management. Internally, it consists of an IBUFG driving the CLKIN pin of a CLKDLL followed by a BUFG that is driven by the CLK0 pin of the CLKDLL. Because BUFGDLL already contains an input buffer (IBUFG), it can only be driven by a top-level port (IPAD). Any DUTY_CYCLE_CORRECTION attribute on a BUFGDLL applies to the underlying CLKDLL symbol.

X10033

Usage
This design element is supported for schematics and instantiations but not for inference.

VHDL Instantiation Template


-- Component Declaration for BUFGDLL should be placed -- after architecture statement but before begin keyword component BUFGDLL port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGDLL -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

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BUFGDLL

-- Component Instantiation for BUFGDLL should be placed -- in architecture after the begin keyword BUFGDLL_INSTANCE_NAME : BUFGDLL port map (O => user_O, I => user_I);

Verilog Instantiation Template


BUFGDLL instance_name (.O (user_O), .I (user_I));

Commonly Used Constraints


STARTUP_WAIT

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BUFGMUX

BUFGMUX
Global Clock MUX Buffer with Output State 0
Architectures Supported
BUFGMUX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

BUFGMUX
I0 I1 S X9251 O

BUFGMUX is a multiplexed global clock buffer that can select between two input clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on I1 is selected for output. BUFGMUX and BUFGMUX_1 are distinguished by which state the output assumes when it switches between clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1 assumes output state 1. Using a BUFGMUX element in your design may cause inaccurate simulation if all the following conditions occur: both clock inputs (I0 and I1) are used, GSR is activated during simulation (after simulation time `0'), and the secondary clock input (I1) is selected before or while GSR is active. In this case, the primary clock input (I0) is incorrectly selected. This occurs because there is a cross-coupled register pair that ensures the BUFGMUX output does not inadvertently generate a clock edge. When GSR is asserted, these registers initialize to the default state of I0. To select the secondary clock, you must send a clock pulse to both the primary and secondary clock inputs while GSR is inactive. Note: BUFGMUX guarantees that when S is toggled, the state of the output will remain in the inactive state until the next active clock edge (either I0 or I1) occurs.

Inputs I0 I0 X X X I1 X I1 X X S 0 1

Outputs O I0 I1 0 0

Usage
This design element is supported for schematics and instantiations but not for inference.

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BUFGMUX

VHDL Instantiation Template


-- Component Declaration for BUFGMUX should be placed -- after architecture statement but before begin keyword component BUFGMUX port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGMUX -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFGMUX should be placed -- in architecture after the begin keyword BUFGMUX_INSTANCE_NAME : BUFGMUX port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

Verilog Instantiation Template


BUFGMUX instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .S (user_S));

Commonly Used Constraints


LOC

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BUFGMUX_1

BUFGMUX_1
Global Clock MUX Buffer with Output State 1
Architectures Supported
BUFGMUX_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

BUFGMUX_1
I0 I1 S X9252 O

BUFGMUX_1 is a multiplexed global clock buffer that can select between two input clocks I0 and I1. When the select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on I1 is selected for output. BUFGMUX and BUFGMUX_1 are distinguished by which state the output assumes when it switches between clocks in response to a change in its select input. BUFGMUX assumes output state 0 and BUFGMUX_1 assumes output state 1. Using a BUFGMUX_1 element in your design may cause inaccurate simulation if all the following conditions occur: both clock inputs (I0 and I1) are used, GSR is activated during simulation (after simulation time `0'), and the secondary clock input (I1) is selected before or while GSR is active. In this case, the primary clock input (I0) is incorrectly selected. This occurs because there is a cross-coupled register pair that ensures the BUFGMUX_1 output does not inadvertently generate a clock edge. When GSR is asserted, these registers initialize to the default state of I0. To select the secondary clock, you must send a clock pulse to both the primary and secondary clock inputs while GSR is inactive.

Inputs I0 I0 X X X I1 X I1 X X S 0 1

Outputs O I0 I1 1 1

Usage
This design element is supported for schematics and instantiations but not for inference.

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BUFGMUX_1

VHDL Instantiation Template


-- Component Declaration for BUFGMUX_1 should be placed -- after architecture statement but before begin keyword component BUFGMUX_1 port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGMUX_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFGMUX should be placed -- in architecture after the begin keyword BUFGMUX_1_INSTANCE_NAME : BUFGMUX_1 port map (O => user_O, I0 => user_I0, I1 => user_I1, S => user_S);

Verilog Instantiation Template


BUFGMUX_1 instance_name (.O (user_O), .I0 (user_I0), .I1 (user_I1), .S (user_S));

Commonly Used Constraints


LOC

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BUFGP

BUFGP
Primary Global Buffer for Driving Clocks or Longlines (Four per PLD Device)
BUFGP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

BUFGP, a primary global buffer, is used to distribute high fan-out clock or control signals throughout PLD devices.
X3902

In Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, BUFGP is equivalent to an IBUFG driving a BUFG. In XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, BUFGP is treated like BUFG. A BUFGP provides direct access to Configurable Logic Block (CLB) and Input Output Block (IOB) clock pins and limited access to other CLB inputs. The input to a BUFGP comes only from a dedicated IOB. Because of its structure, a BUFGP can always access a clock pin directly. However, it can access only one of the F3, G1, C3, or C1 pins, depending on the corner in which the BUFGP is placed. When the required pin cannot be accessed directly from the vertical line, PAR feeds the signal through another CLB and uses general purpose routing to access the load pin. To use a BUFGP in a schematic, connect the input of the BUFGP element directly to the PAD symbol. Do not use any IBUFs, because the signal comes directly from a dedicated IOB. The output of the BUFGP is then used throughout the schematic. For a negative-edge clock, insert an INV (inverter) element between the output of the BUFGP and the clock input. This inversion is performed inside each CLB or IOB. A Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X, or Spartan-3 BUFGP must be sourced by an external signal.

Usage
This design element is supported for schematic and instantiation. Synthesis tools usually infer a BUFGP on any clock net. If there are more clock nets than BUFGPs, the synthesis tool usually instantiates BUFGPs for the clocks that are most utilized.

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BUFGP

VHDL Instantiation Template


-- Component Declaration for BUFGP should be placed -- after architecture statement but before begin keyword component BUFGP port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGP -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFGP should be placed -- in architecture after the begin keyword BUFGP_INSTANCE_NAME : BUFGP port map (O => user_O, I => user_I);

Verilog Instantiation Template


BUFGP instance_name (.O (user_O), .I (user_I));

Commonly Used Constraints


HBLKNM

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BUFGSR

BUFGSR
Global Set/Reset Input Buffer
Architectures Supported
BUFGSR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I O X9428

No No No Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

BUFGSR distributes global set/reset signals throughout selected flip-flops of an XC9500/XV/XL, CoolRunner XPLA3, or CoolRunner-II device. Global Set/Reset (GSR) control pins are available on these CPLD devices. Consult device data sheets for availability. BUFGSR always acts as an input buffer. To use it in a schematic, connect the input of the BUFGSR symbol to an IPAD or an IOPAD representing the GSR signal source. GSR signals generated on-chip must be passed through an OBUF-type buffer before they are connected to BUFGSR. For global set/reset control, the output of BUFGSR normally connects to the CLR or PRE input of a flip-flop symbol, like FDCP, or any registered symbol with asynchronous clear or preset. The global set/reset control signal may pass through an inverter to perform an active-low set/reset. The output of BUFGSR may also be used as an ordinary input signal to other logic elsewhere in the design. Each BUFGSR can control any number of flip-flops in a design.

Usage
This design element is supported for schematics and instantiations but not for inference.

VHDL Instantiation Template


-- Component Declaration for BUFGSR should be placed -- after architecture statement but before begin keyword component BUFGSR port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGSR -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

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BUFGSR

-- Component Instantiation for BUFGSR should be placed -- in architecture after the begin keyword

BUFGSR_INSTANCE_NAME : BUFGSR port map (O => user_O, I => user_I);

Verilog Instantiation Template


BUFGSR instance_name (.O (user_O), .I (user_I));

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BUFGTS

BUFGTS
Global 3-State Input Buffer
Architectures Supported
BUFGTS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
I O X9428

No No No Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

BUFGTS distributes global output-enable signals throughout the output pad drivers of an XC9500/XV/XL, CoolRunner XPLA3, or CoolRunner-II device. Global ThreeState (GTS) control pins are available on these CPLD devices. Consult device data sheets for availability. BUFGTS always acts as an input buffer. To use it in a schematic, connect the input of the BUFGTS symbol to an IPAD or an IOPAD representing the GTS signal source. GTS signals generated on-chip must be passed through an OBUF-type buffer before they are connected to BUFGTS. For global 3-state control, the output of BUFGTS normally connects to the E input of a 3-state output buffer symbol, OBUFE. The global 3-state control signal may pass through an inverter or control an OBUFT symbol to perform an active-low outputenable. The same 3-state control signal may even be used both inverted and noninverted to enable alternate groups of device outputs. The output of BUFGTS may also be used as an ordinary input signal to other logic elsewhere in the design. Each BUFGTS can control any number of output buffers in a design.

Usage
This design element is supported for schematics and instantiations but not for inference.

VHDL Instantiation Template


-- Component Declaration for BUFGTS should be placed -- after architecture statement but before begin keyword component BUFGTS port (O : out STD_ULOGIC; I : in STD_ULOGIC); end component; -- Component Attribute specification for BUFGTS -- should be placed after architecture declaration but -- before the begin keyword

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BUFGTS

-- Enter attributes here -- Component Instantiation for BUFGTS should be placed -- in architecture after the begin keyword

BUFGTS_INSTANCE_NAME : BUFGTS port map (O => user_O, I => user_I);

Verilog Instantiation Template


BUFGTS instance_name (.O (user_O), .I (user_I));

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BUFT, 4, 8, 16

BUFT, 4, 8, 16
Internal 3-State Buffers with Active-Low Enable
Architectures Supported
BUFT Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II BUFT4, BUFT8, BUFT16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro No Macro Macro* No No Primitive No Primitive Primitive* No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

*Not supported for XC9500XL and XC9500XV devices.

BUFT T

X3789

BUFT, BUFT4, BUFT8, and BUFT16 are single or multiple 3-state buffers with inputs I, I3 I0, I7 I0, and I15 10, respectively; outputs O, O3 O0, O7 O0, and O15 O0, respectively; and active-Low output enable (T). When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, the output is high impedance (Z state or off). The outputs of the buffers are connected to horizontal longlines in FPGA architectures. The outputs of separate BUFT symbols can be tied together to form a bus or a multiplexer. Make sure that only one T is Low at one time. For XC9500 devices, BUFT output nets assume the High logic level when all connected BUFE/BUFT buffers are disabled.

BUFT4 T

X3796

For Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, when all BUFTs on a net are disabled, the net is High. For correct simulation of this effect, a PULLUP element must be connected to the net. NGDBuild inserts a PULLUP element if one is not connected so that back-annotation simulation reflects the true state of the device.

BUFT8 T

X3808

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BUFT, 4, 8, 16

BUFT16 T

X3820

Inputs T 1 0 0 I X 1 0
O[7:0] T I0 T I1 T I2 T I3 T I4 T I5 T I6 T I7 BUFT I[7:0] T X8118 BUFT O7 BUFT O6 BUFT O5 BUFT O4 BUFT O3 BUFT O2 BUFT O1 O0

Outputs O Z 1 0

BUFT8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
These design elements are supported for schematics, instantiations, or inferences.

VHDL Inference Code


architecture Behavioral of buft is begin process (I, T) begin if (T = '0') then O <= I; else O <= 'Z'; end if; end process; end Behavioral;

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BUFT, 4, 8, 16

Verilog Inference Code


always @ (I or T) begin if (!T) O <= I; else O <= 1'bZ; end

VHDL Instantiation Template


-- Component Declaration for BUFT should be placed -- after architecture statement but before begin keyword component BUFT port (O : out STD_ULOGIC; I : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for BUFT -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for BUFT should be placed -- in architecture after the begin keyword BUFT_INSTANCE_NAME : port map (O => I => T => BUFT user_O, user_I, user_T);

Verilog Instantiation Template


BUFT instance_name (.O (user_O), .I (user_I), .T (user_T));

Commonly Used Constraints


BLKNM HBLKNM HU_SET LOC U_SET

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BUFT, 4, 8, 16

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CAPTURE_SPARTAN2

CAPTURE_SPARTAN2
Spartan-II Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_SPARTAN2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CAPTURE_SPARTAN2
CAP

Primitive No No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CLK

CAPTURE_SPARTAN2 provides user control over when to capture register (flip-flop and latch) information for readback. Spartan-II and Spartan-IIE devices provide the readback function through dedicated configuration port instructions. The CAPTURE_SPARTAN2 symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available. Note: Spartan-II and Spartan-IIE devices only allow for capturing register (flip-flop and latch)
states. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured.

X8895

An asserted High CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_SPARTAN2. See the Constraints Guide for information on the ONESHOT attribute. Note: For details on the Spartan-II and Spartan-IIE readback functions, see The Programmable Logic Data Book.

Usage
This design element is supported for schematics and instantiation but not for inferrence.

VHDL Instantiation Template


-- Component Declaration for CAPTURE_SPARTAN2 should be -- placed after architecture statement but before -- begin keyword component CAPTURE_SPARTAN2 port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_SPARTAN2 -- should be placed after architecture declaration but

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CAPTURE_SPARTAN2

-- before the begin keyword -- Enter attributes here

-- Component Instantiation for CAPTURE_SPARTAN2 should be -- placed in architecture after the begin keyword CAPTURE_SPARTAN2_INSTANCE_NAME : CAPTURE_SPARTAN2 port map (CAP => user_CAP, CLK => user_CLK);

Verilog Instantiation Template


CAPTURE_SPARTAN2 instance_name (.CAP (user_CAP), .CLK (user_CLK));

Commonly Used Constraints


ONESHOT

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CAPTURE_SPARTAN3

CAPTURE_SPARTAN3
Spartan-3 Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_SPARTAN3 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CAPTURE_SPARTAN3 CAP

CAPTURE_SPARTAN3 provides user control over when to capture register (flip-flop and latch) information for readback. Spartan-3 devices provide the readback function through dedicated configuration port instructions. The CAPTURE_SPARTAN3 symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available.

CLK

X9931

Spartan-3 allows for capturing register (flip-flop and latch) states only. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured. An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_SPARTAN3. See the Constraints Guide for information on the ONESHOT attribute.

Usage
This design element is instantiated rather than inferred.

VHDL Instantiation Template


-- Component Declaration for CAPTURE_SPARTAN3 should be -- placed after architecture statement but before -- begin keyword component CAPTURE_SPARTAN3 port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_SPARTAN3 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

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CAPTURE_SPARTAN3

-- Component Instantiation for CAPTURE_SPARTAN3 should be -- placed in architecture after the begin keyword

CAPTURE_SPARTAN3_INSTANCE_NAME : CAPTURE_SPARTAN3 port map (CAP => user_CAP, CLK => user_CLK);

Verilog Instantiation Template


CAPTURE_SPARTAN3 instance_name (.CAP (user_CAP), .CLK (user_CLK));

Commonly Used Constraints


ONESHOT

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CAPTURE_VIRTEX

CAPTURE_VIRTEX
Virtex Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_VIRTEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CAPTURE_VIRTEX
CAP

No No Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CAPTURE_VIRTEX provides user control over when to capture register (flip-flop and latch) information for readback. Virtex and Virtex-E devices provide the readback function through dedicated configuration port instructions. The CAPTURE_VIRTEX symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available. Note: Virtex and Virtex-E allow for capturing register (flip-flop and latch) states only. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured. An asserted High CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_VIRTEX. See the Constraints Guide for information on the ONESHOT attribute. For details on the Virtex and Virtex-E readback functions, see the Virtex datasheets on the Xilinx web site, http://support.xilinx.com.

CLK

X8681

Usage
This design element is supported for schematics and instantiation but not for inferrence.

VHDL Instantiation Template


-- Component Declaration for CAPTURE_VIRTEX should be -- placed after architecture statement but before -- begin keyword component CAPTURE_VIRTEX port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_VIRTEX -- should be placed after architecture declaration but -- before the begin keyword

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CAPTURE_VIRTEX

-- Enter attributes here

-- Component Instantiation for CAPTURE_VIRTEX should be -- placed in architecture after the begin keyword CAPTURE_VIRTEX_INSTANCE_NAME : CAPTURE_VIRTEX port map (CAP => user_CAP, CLK => user_CLK);

Verilog Instantiation Template


CAPTURE_VIRTEX instance_name (.CAP (user_CAP), .CLK (user_CLK));

Commonly Used Constraints


ONESHOT

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CAPTURE_VIRTEX2

CAPTURE_VIRTEX2
Virtex-II Register State Capture for Bitstream Readback
Architectures Supported
CAPTURE_VIRTEX2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

CAPTURE_VIRTEX2 CAP

CLK

CAPTURE_VIRTEX2 provides user control over when to capture register (flip-flop and latch) information for readback. Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices provide the readback function through dedicated configuration port instructions. The CAPTURE_VIRTEX2 symbol is optional. Without it readback is still performed, but the asynchronous capture function it provides for register states is not available. Virtex-II, Virtex-II Pro, and Virtex-II Pro X allow for capturing register (flip-flop and latch) states only. Although LUT RAM, SRL, and block RAM states are read back, they cannot be captured. An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-High clock transition. By default, data is captured after every trigger (transition on CLK while CAP is asserted). To limit the readback operation to a single data capture, add the ONESHOT attribute to CAPTURE_VIRTEX2. See the Constraints Guide for information on the ONESHOT attribute. The GRDBK (internal capture signal) is asserted at the rising edge of the Capture clock when the Capture signal is high. The capture memory cell is continuously updated if the value of the FF is continuously changing. The final value of the capture memory cell occurs at the rising edge of the Capture clock when the Capture signal is low. For details on the Virtex-II, Virtex-II Pro, and Virtex-II Pro X readback functions, see The Programmable Logic Data Book.

X9397

Usage
This design element is supported for schematics and instantiation but not for inferrence.

VHDL Instantiation Template


-- Component Declaration for CAPTURE_VIRTEX2 should be -- placed after architecture statement but before -- begin keyword

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CAPTURE_VIRTEX2

component CAPTURE_VIRTEX2 port (CAP : in STD_ULOGIC; CLK : in STD_ULOGIC); end component; -- Component Attribute specification for CAPTURE_VIRTEX2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for CAPTURE_VIRTEX2 should be -- placed in architecture after the begin keyword CAPTURE_VIRTEX2_INSTANCE_NAME : CAPTURE_VIRTEX2 port map (CAP => user_CAP, CLK => user_CLK);

Verilog Instantiation Template


CAPTURE_VIRTEX2 instance_name (.CAP (user_CAP), .CLK (user_CLK));

Commonly Used Constraints


None

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CB2CE, CB4CE, CB8CE, CB16CE

CB2CE, CB4CE, CB8CE, CB16CE


2-, 4-, 8-,16-Bit Cascadable Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CB2CE, CB4CE, CB8CE, CB16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CB2CE

Q0 Q1 CEO TC

CE C

CLR

X4353

CB2CE, CB4CE, CB8CE, and CB16CE are, respectively, 2-, 4-, 8-, and 16-bit (stage), asynchronous, clearable, cascadable binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, outputs Low, when power is applied.

CB4CE

Q0 Q1 Q2 Q3

CE C

CEO TC

CLR X4357

CB8CE
CE C

Q[7:0] CEO TC

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs Outputs C X X Qz-Q0 0 No Chg TC 0 No Chg CEO 0 0

CLR

X4361

CB16CE
CE C

Q[15:0] CEO TC

CLR

X4365

CLR 1 0

CE X 0

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CB2CE, CB4CE, CB8CE, CB16CE

Inputs CLR 0 CE 1 C Qz-Q0 Inc

Outputs TC TC CEO CEO

z= 1 for CB2CE; z = 3 for CB4CE; z = 7 for CB8CE; z = 15 for CB16CE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE

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CB2CE, CB4CE, CB8CE, CB16CE

VCC

Q[7:0] FTCE
T CE C CLR Q

Q0

Q0

FTCE
T CE C Q

Q1 T2

CLR

Q1

AND2

FTCE
T CE C Q

Q2 T3

CLR

Q2

AND3

FTCE
T CE C Q

Q3 T4

CLR

Q3
AND4

FTCE
T CE C Q

Q4 T5

CLR

Q4

AND2

FTCE
T CE C Q

Q5 T6

CLR

Q5

AND3

FTCE
T CE C Q

Q6 T7

CLR

Q6
AND4

FTCE
CE C CLR T CE C Q

Q7

CLR

TC Q7
AND5

CEO X8136
AND2

CB8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E,

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CB2CE, CB4CE, CB8CE, CB16CE

Virtex-II, Virtex-II Pro, Virtex-II Pro X


VCC

CE AND2 Q0 Q1

FDC
D XOR2 C CLR Q0 AND3 Q CEO

TC AND2

FDC
D AND2 C CLR XOR2 C CLR Q1
X7779

CB2CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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CB2CE, CB4CE, CB8CE, CB16CE

CB2CE
Q0 CE C Q1 CE C CEO TC CLR CLR CB0 Q0 Q1

CB2CE
Q0 Q1 CE C CEO TC CLR CB2 Q2 Q3

CB2CE
Q0 Q1 CE C CEO TC CLR CB4 Q4 Q5

CB2CE
Q0 Q1 CE C CEO TC CLR CB6 Q6 Q7 CEO

TC

X7783

AND4

CB8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cb2ce is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then

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CB2CE, CB4CE, CB8CE, CB16CE

if (CE='1') then Q <= Q+1; end if; end if; end process; process (Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (CE or TC) begin CE0 <= TC && CE; end

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CB2CLE, CB4CLE, CB8CLE, CB16CLE

CB2CLE, CB4CLE, CB8CLE, CB16CLE


2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CB2CLE, CB4CLE, CB8CLE, CB16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No Macro Macro Macro

D0 D1 L CE C

CB2CLE

Q0 Q1

CEO TC

CLR X4354

D0 D1 D2 D3 L CE C

CB4CLE

Q0 Q1 Q2 Q3

CB2CLE, CB4CLE, CB8CLE, and CB16CLE are, respectively, 2-, 4-, 8-, and 16-bit (stage) synchronously loadable, asynchronously clearable, cascadable binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock transition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied.

CEO TC

CLR

X4358

D[7:0]

CB8CLE

Q[7:0]

L CE C CEO TC

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.

CLR

X4362

D[15:0]

CB16CLE

Q[15:0]

L CE C CEO TC

CLR

X4366

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207

CB2CLE, CB4CLE, CB8CLE, CB16CLE

Inputs CLR 1 0 0 0 L X 1 0 0 CE X X 0 1 C X X Dz D0 X Dn X X Qz Q0 0 Dn No Chg Inc

Outputs TC 0 TC No Chg TC CEO 0 CEO 0 CEO

z= 1 for CB2CLE; z = 3 for CB4CLE; z = 7 for CB8CLE; z = 15 for CB16CLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC

FTCLEX
D0 D L T CE C CLR Q

Q[7:0] Q0

Q0 FTCLEX
D1 D L T CE C

Q1 T2

CLR

Q1 FTCLEX
D2 D L T CE C

AND2

Q2 T3

CLR

Q2 FTCLEX
D3 D L T CE C

AND3

Q3 T4

CLR

Q3
AND4

FTCLEX
D4 D L T CE C

Q4 T5

CLR

Q4 FTCLEX
D5 D L T CE C

AND2

Q5 T6

CLR

Q5 FTCLEX
D6 D L T CE C

AND3

Q6 T7

CLR

Q6
AND4

D[7:0] D7
L CE C CLR

FTCLEX
D L T CE C Q

Q7

CLR

TC Q7
AND5

OR_CE_L OR2

CEO
AND2

X8135

CB8CLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

208

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Libraries Guide ISE 6.li

CB2CLE, CB4CLE, CB8CLE, CB16CLE

VCC

CE AND2 Q0 Q1 CEO

FDC
OR2 GND AND2B1 OR2 D0 AND2 AND2B1 D XOR2 C CLR Q0 Q AND2 AND3 TC

AND2B1 D XOR2 AND3B1 OR2 D1 C CLR AND2 C

FDC
Q

CLR Q1

X7780

CB2CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II


CB2CLE
D0 D1 L CE C D0 D1 Q0 Q1 CEO TC CLR CLR CB0 Q0 Q1

L
CE C

CB2CLE
D2 D3 D0 D1 Q0 Q1 CEO TC CLR CB2 Q2 Q3

L
CE C

D[7:0]

Q[7:0]

CB2CLE
D4 D5 D0 D1 Q0 Q1 CEO TC CLR CB4 Q4 Q5

L
CE C

CB2CLE
D6 D7 D0 D1 Q0 Q1 CEO TC CLR CB6 Q6 Q7 CEO

L
CE C

TC

X8130

AND4

CB8CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Libraries Guide ISE 6.li

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209

CB2CLE, CB4CLE, CB8CLE, CB16CLE

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cb2cle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (L = '1') then Q <= D; elsif (CE='1') then Q <= COUNT+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; TC <= TC_INT; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0;

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Libraries Guide ISE 6.li

CB2CLE, CB4CLE, CB8CLE, CB16CLE

end always @ (TC or CE) begin CEO <= TC & CE; end

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211

CB2CLE, CB4CLE, CB8CLE, CB16CLE

212

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Libraries Guide ISE 6.li

CB2CLED, CB4CLED, CB8CLED, CB16CLED

CB2CLED, CB4CLED, CB8CLED, CB16CLED


2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No Macro Macro Macro

D0 D1 UP L CE C

CB2CLED Q0
Q1

CEO TC

CLR

X4355

CB2CLED, CB4CLED, CB8CLED, and CB16CLED are, respectively, 2-, 4-, 8- and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-toHigh clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low. For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. To cascade counters, the CEO output of each counter is connected to the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, see CB2X1, CB4X1, CB8X1, CB16X1 for high-performance cascadable, bidirectional counters. The counter is asynchronously cleared, output Low, when power is applied.

D0 D1 D2 D3 UP L CE C

CB4CLED Q0
Q1 Q2 Q3

CEO TC

CLR

X4359

D[7:0]

CB8CLED

Q[7:0]

UP L CE C CEO TC

CLR

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted with an inverter in front of the GSR input of STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2.

X4363

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213

CB2CLED, CB4CLED, CB8CLED, CB16CLED

D[15:0] CB16CLED Q[15:0] UP L CE C CEO TC

Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 C X X UP X X X 1 0 Dz D0 X Dn X X X Qz Q0 0 Dn No Chg Inc Dec

Outputs TC TC No Chg TC TC CEO *CE CEO 0 CEO CEO

CLR

X4367

z = 1 for CB2CLED; z = 3 for CB4CLED; z = 7 for CB8CLED; z = 15 for CB16CLED TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP) CEO = TCCE

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Libraries Guide ISE 6.li

CB2CLED, CB4CLED, CB8CLED, CB16CLED

D[7:0] D0 VCC

FTCLEX D L T Q CE C CLR Q0 FTCLEX D L T Q CE C CLR Q1 Q1 T2_DN M2_1 AND2B2 T2_UP AND2 FTCLEX D L Q T CE C CLR Q2 Q2 T3_DN M2_1 AND3B3 T3_UP AND3 D0 D1 S0 O T3 T3 D0 D1 S0 O T2 T2 Q0 D0 D1 S0 M2_1B1 O T1 T1

D1

D2

D3

FTCLEX D L T Q CE C CLR Q3 Q3 T4_DN M2_1 AND4B4 T4_UP AND4 D0 D1 S0 O T4 T4

D4

FTCLEX D L T Q CE C CLR Q4

Q4 T5_DN M2_1 AND2B1 T5_UP AND2 D0 D1 S0 O T5 T5

D5

FTCLEX D L T Q CE C CLR Q5

Q5 T6_DN M2_1 AND3B2 D0 D1 S0 O T6 T6

T6_UP AND3 D6 FTCLEX D L Q T CE C CLR Q6

Q6 T7_DN M2_1 AND4B3 T7_UP AND4 D0 D1 S0 O T7 T7

D7 L CE C CLR

FTCLEX D L Q T CE C CLR Q7

Q7 Q[7:0] TC_DN M2_1 D0 O D1 S0 TC AND2 TC CEO

AND5B4 OR_CE_L OR2 TC_UP AND5 UP

X4046

CB8CLED Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Libraries Guide ISE 6.li

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215

CB2CLED, CB4CLED, CB8CLED, CB16CLED

VCC

CE
AND2

UP
OR2 GND

AND3B2

FDC
D AND3B1 OR2 OR3 XOR2 C CLR Q

Q0

GND

D0
AND2

Q0

AND2B1

AND4B3

FDC
D AND4B1 OR3 XOR2 C CLR Q

Q1

D1
AND2

Q1

AND2B1

AND5B4

FDC
D OR3 AND5B1 XOR2 C CLR Q

Q2

D2
AND2

Q2

AND2B1

INV INV INV INV INV AND6

FDC
INV OR3 AND6 XOR2 D C CLR Q

Q3

Q3 D3
AND2

AND2B1

AND5 OR2

TC

AND5B5

INV INV INV INV INV

AND6 OR2

CEO

AND6

C CLR

X7625

CB4CLED Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

216

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CB2CLED, CB4CLED, CB8CLED, CB16CLED

VHDL Inference Code


architecture Behavioral of cb2cled is constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif C'event and C='1' then if (L = '1') then Q <= D; elsif (CE='1') then if (UP='1') then Q <= Q+1; elsif (UP='0') then Q <= Q-1; end if; end if; end if; end process; process(Q, UP) begin if (((Q = TERMINAL_COUNT_UP) and (UP = '1')) or ((Q = TERMINAL_COUNT_DOWN) and (UP = '0'))) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (UP) Q <= Q + 1; else if (!UP) Q <= Q - 1; end end

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217

CB2CLED, CB4CLED, CB8CLED, CB16CLED

always @ (Q or UP) begin if ((Q == TERMINAL_COUNT_UP && UP) || (Q == TERMINAL_COUNT_DOWN && !UP)) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

218

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Libraries Guide ISE 6.li

CB2RE, CB4RE, CB8RE, CB16RE

CB2RE, CB4RE, CB8RE, CB16RE


2-, 4-, 8-, 16-Bit Cascadable Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CB2RE, CB4RE, CB8RE, CB16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CB2RE

Q0 Q1 CEO TC

CE C

X4356

CB2RE, CB4RE, CB8RE, and CB16RE are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, resettable, cascadable binary counters. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero during the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when both Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied.

CB4RE

Q0 Q1 Q2 Q3

CE C

CEO TC

X4360

CB8RE
CE C

Q[7:0] CEO TC

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 CE X 0 C X Qz Q0 0 No Chg Outputs TC 0 No Chg CEO 0 0

X4364

CB16RE
CE C

Q[15:0] CEO TC

X4368

Libraries Guide ISE 6.li

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219

CB2RE, CB4RE, CB8RE, CB16RE

Inputs R 0 CE 1 C Qz Q0 Inc

Outputs TC TC CEO CEO

z = 1 for CB2RE; z = 3 for CB4RE; z = 7 for CB8RE; z = 15 for CB16RE TC = QzQ(z-1)Q(z-2)...Q0) CEO = TCCE
FTRSE
T CE C S Q

VCC

Q[7:0] Q0

Q0

FTRSE
T CE C S Q

Q1 T2

Q1

AND2

FTRSE
T CE C S Q

Q2 T3

Q2

AND3

FTRSE
T CE C S Q

Q3 T4

Q3
AND4

FTRSE
T CE C S Q

Q4 T5

Q4

AND2

FTRSE
T CE C S Q

Q5 T6

Q5

AND3

FTRSE
T CE C S Q

Q6 T7

Q6
AND4

FTRSE
T CE C S Q

Q7

CE C R

TC Q7

GND

AND5

CEO X8137
AND2

CB8RE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

220

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CB2RE, CB4RE, CB8RE, CB16RE

VCC

CE AND2 R CEO AND3

FD
D AND2B1 XOR2 C Q0 AND2B1 Q AND2 TC

FD
D AND3B1 XOR2 C Q1 C AND2B1 Q

Q0 Q1

X7781

CB2RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II


CB2RE
Q0 CE C Q1 CE C R R CB0 CEO TC Q0 Q1

CB2RE
Q0 Q1 CE C R CB2 CEO TC Q2 Q3

CB2RE
Q0 Q1 CE C R CB4 CEO TC Q4 Q5

CB2RE
Q0 Q1 CE C R CB6 CEO TC Q6 Q7 CEO Q[7:0]

TC X8129 AND4

CB8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cb2re is

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221

CB2RE, CB4RE, CB8RE, CB16RE

constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C) begin if (C'event and C='1') then if (R='1') then Q <= (others => '0'); elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

222

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Libraries Guide ISE 6.li

CB2RLE, CB4RLE, CB8RLE, CB16RLE

CB2RLE, CB4RLE, CB8RLE, CB16RLE


2-, 4-, 8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CB2RLE, CB4RLE, CB8RLE, CB16RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro Macro

D0 D1

CB2RLE

Q0 Q1

L CE C CEO TC

CB2RLE, CB4RLE, CB8RLE, and CB16RLE are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, loadable, resettable, cascadable binary counters. The synchronous reset (R) is the highest priority input. The synchronous R, when High, overrides all other inputs and resets the Q outputs, terminal count (TC), and clock enable out (CEO) outputs to Low on the Low-to-High clock (C) transition. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of CE. The Q outputs increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. The CEO output is High when all Q outputs and CE are High to allow direct cascading of counters. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and by connecting the C, L, and R inputs in parallel. The maximum length of the counter is determined by the accumulated CE-to-CEO propagation delays versus the clock period. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

X4513

D0 D1 D2 D3 L CE C

CB4RLE

Q0 Q1 Q2 Q3

CEO TC

X4514

D[7:0]

CB8RLE

Q[7:0]

L CE C CEO TC

X4515

Inputs
D[15:0]

Outputs C X Dz D0 X Dn X Qz Q0 0 Dn No Chg TC 0 TC No Chg CEO 0 CEO 0

CB16RLE Q[15:0]

R 1

L X 1 0

CE X X 0

L CE C CEO TC

0 0

X4516

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223

CB2RLE, CB4RLE, CB8RLE, CB16RLE

Inputs R 0 L 0 CE 1 C Dz D0 X Qz Q0 Inc

Outputs TC TC CEO CEO

z = 1 for CB2RLE; z = 3 for CB4RLE; z = 7 for CB8RLE; z = 15 for CB16RLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC

CE AND2 L OR2 GND

CEO AND3

Q1 AND3B2 D0 Q0

OR2 AND3B1 XOR2 C D

FD
TC Q AND2

Q0 AND3B2

AND4B2 D1

OR2 AND3B1 XOR2 C D

FD
Q

Q1 AND3B2 C
X7782

CB2RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

CB2RLE
D0 D1 L CE C R Q0 D0 Q1 D1 L CE CEO TC C R CB0 Q0 Q1

CB2RLE
D2 D3 Q0 D0 D1 Q1 L CE CEO C TC R CB2 Q2 Q3

CB2RLE
D4 D5 Q0 D0 Q1 D1 L CE CEO TC C R CB4 Q4 Q5

CB2RLE
D6 D7 D0 Q0 Q1 D1 L CE CEO C TC R CB6 Q6 Q7 CEO

D[7:0] Q[7:0]

TC AND4

X7621

CB8RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

224

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Libraries Guide ISE 6.li

CB2RLE, CB4RLE, CB8RLE, CB16RLE

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cb2rle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C) begin if (C'event and C='1') then if (R='1') then Q <= (others => '0'); elsif (L='1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

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225

CB2RLE, CB4RLE, CB8RLE, CB16RLE

226

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Libraries Guide ISE 6.li

CB2X1, CB4X1, CB8X1, CB16X1

CB2X1, CB4X1, CB8X1, CB16X1


2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CB2X1, CB4X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II CB8X1, CB16X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D0 D1 L CEU CED C

CB2X1

QO Q1 TCU TCD CEOU CEOD

CB2X1, CB4X1, CB8X1, and CB16X1 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronously loadable, asynchronously clearable, bidirectional binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support high-speed cascading in XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU and CEOD go to Low and High, respectively, independent of clock transitions. The data on the D inputs loads into the counter on the Low-to-High clock (C) transition when the load enable input (L) is High, independent of the CE inputs. The Q outputs increment when CEU is High, provided CLR and L are Low, during the Low-to-High clock transition. The Q outputs decrement when CED is High, provided CLR and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are

CLR

X4194

D0 D1 D2 D3 CEU CED L C

CB4X1

Q0 Q1 Q2 Q3 TCU TCD CEOU CEOD

CLR

X4196

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227

CB2X1, CB4X1, CB8X1, CB16X1

D[7:0]

CB8X1

Q[7:0] TCU

connected directly to the CEU and CED inputs, respectively, of the next stage. The clock, L, and CLR inputs are connected in parallel. The maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

L CEU CED C

TCD CEOU CEOD

CLR

X4198

D[15:0]

CB16X1

Q[15:0] TCU

L CEU CED C

TCD CEOU CEOD

CLR

X4200

Inputs CLR 1 0 0 0 0 0 L X 1 0 0 0 0 CEU X X 0 1 0 1 CED X X 0 0 1 1 C X X DzD0 X Dn X X X X QzQ0 0 Dn No Chg Inc Dec Inc TCU 0 TCU No Chg TCU TCU TCU

Outputs TCD 1 TCD No Chg TCD TCD TCD CEOU 0 CEOU 0 CEOU 0 Invalid CEOD CEOD CEOD 0 0 CEOD Invalid

z = 1 for CB2X1; z = 3 for CB4X1; z = 7 for CB8X1; z = 15 for CB16X1 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED

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CB2X1, CB4X1, CB8X1, CB16X1

L
OR2

CEU
OR2

AND2B1

FDC CED
OR2 AND2B1 GND D AND3B2 OR3 XOR2 C CLR Q

Q0

Q0

D0
AND2

AND4B3

FDC
D AND3B1 OR3 XOR2 C CLR AND2B1 Q

Q1

Q1

D1
AND2

AND5B4

FDC
D AND4B1 OR3 XOR2 C CLR Q

Q2

Q2
AND2B1

D2
AND2

INV INV INV INV INV AND6

FDC
D OR3 AND5B1 XOR2 C CLR Q

Q3

Q3
AND2B1

D3
AND2

TCU
AND4 INV INV INV INV INV INV INV AND7

INV INV INV INV INV AND7 NOR4 D C CLR

FDC
Q

TCDINV

TCDINV
AND5B4

AND3B1

CEQU
AND2

CEQD
AND3B1

TCD
INV

C CLR

X7624

CB4X1 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

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229

CB2X1, CB4X1, CB8X1, CB16X1

VHDL Inference Code


architecture Behavioral of cb2x1 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif ((C'event) and (C='1')) then if (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process (Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU <= '1'; TCD <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU <= TCU and CEU; CEOD <= TCD and CED; end Behavioral;

230

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Libraries Guide ISE 6.li

CB2X1, CB4X1, CB8X1, CB16X1

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @ (TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end

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231

CB2X1, CB4X1, CB8X1, CB16X1

232

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Libraries Guide ISE 6.li

CB2X2, CB4X2, CB8X2, CB16X2

CB2X2, CB4X2, CB8X2, CB16X2


2-, 4-, 8-, and 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CB2X2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II CB4X2, CB8X2, CB16X2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D0 D1 L CEU CED C

CB2X2

QO Q1 TCU TCD CEOU CEOD

CB2X2, CB4X2, CB8X2, and CB16X2 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, loadable, resettable, bidirectional binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support high-speed cascading in CPLD architectures. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, and clock enable outputs CEOU and CEOD go to Low and High, respectively, on the Low-to-High clock (C) transition. The data on the D inputs loads into the counter on the Low-to-High clock (C) transition when the load enable input (L) is High, independent of the CE inputs. All Q outputs increment when CEU is High, provided R and L are Low during the Low-to-High clock transition. All Q outputs decrement when CED is High, provided R and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are, respectively, connected directly to the CEU and CED inputs of the next stage. The C, L, and R inputs are connected in parallel.

X4195

D0 D1 D2 D3 L CEU CED C

CB4X2

Q0 Q1 Q2 Q3 TCU TCD CEOU CEOD

X4197

D[7:0]

CB8X2

Q[7:0] TCU

L CEU CED C

TCD CEOU CEOD

X4199

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233

CB2X2, CB4X2, CB8X2, CB16X2

D[15:0]

CB16X2

Q[15:0] TCU

L CEU CED C

TCD CEOU CEOD

The maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

X4201

Inputs R 1 0 0 0 0 0 L X 1 0 0 0 0 CEU X X 0 1 0 1 CED X X 0 0 1 1 C X Dz D0 X Dn X X X X Qz Q0 0 Dn No Chg Inc Dec Inc TCU 0 TCU No Chg TCU TCU TCU

Outputs TCD 1 TCD No Chg TCD TCD TCD CEOU 0 CEOU 0 CEOU 0 Invalid CEOD CEOD CEOD 0 0 CEOD Invalid

z = 1 for CB2X2; z = 3 for CB4X2; z = 7 for CB8X2; z = 15 for CB16X2 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED

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CB2X2, CB4X2, CB8X2, CB16X2

L
OR2

Q3 Q2 Q1 Q0

CED
OR2

TCU
AND4B3 AND4

R TCD
INV

FD
AND3B2 OR3 XOR2 C AND3B2 D Q AND3B1

CEQD

CEQU

D0

Q0

AND2

AND3B1

CEU
OR2

GND

AND5B4

FD
AND4B2 OR3 D XOR2 C Q

AND3B2

Q1

D1

AND3B1

INV INV INV INV INV AND6

OR3 AND5B2 XOR2 D C

FDC
Q

AND3B2

Q2

D2

AND3B1

INV INV INV INV INV INV AND7

INV INV OR3 AND6 XOR2 D C

FDC
Q

AND3B2

Q3

D3

AND3B1 INV INV INV INV INV INV INV AND7

INV INV INV INV INV AND7 D C

FDC
Q

NOR5 INV

TCDINV

AND6

AND5B4

CB4X2 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Libraries Guide ISE 6.li

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235

CB2X2, CB4X2, CB8X2, CB16X2

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cb2x2 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C) begin if ((C'event) and (C='1'))then if (R='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process(Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU <= '1'; TCD <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU<=TCU and CEU; CEOD<=TCD and CED;

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CB2X2, CB4X2, CB8X2, CB16X2

end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @(TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end

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237

CB2X2, CB4X2, CB8X2, CB16X2

238

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Libraries Guide ISE 6.li

CBD2CE, CBD4CE, CBD8CE, CBD16CE

CBD2CE, CBD4CE, CBD8CE, CBD16CE


2-, 4-, 8-,16-Bit Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CE, CBD4CE, CBD8CE, CBD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
CBD2CE

No No No No No No Macro

Q0 Q1 CEO TC

CE C

CLR
X9621

CBD4CE

CBD2CE, CBD4CE, CBD8CE, and CBD16CE are, respectively, 2-, 4-, 8-, and 16-bit (stage), asynchronous, clearable, cascadable dual edge triggered binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, outputs Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Q0 Q1 Q2 Q3

CE C

CEO TC

CLR
X9622

CBD8CE
CE C

Q[7:0] CEO TC

CLR

X9623

CBD16CE
CE C

Q[15:0] CEO TC

CLR
X9624

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239

CBD2CE, CBD4CE, CBD8CE, CBD16CE

VCC

CE AND2 Q0 Q1

FDDC
D XOR2 C CLR Q0 AND3 Q CEO

TC AND2

FDDC
D AND2 C CLR XOR2 C CLR Q1
X9625

CBD2CE Implementation CoolRunner-II


CBD2CE
Q0 CE C Q1 CE C CEO TC CLR CLR CB0 Q0 Q1

CBD2CE
Q0 Q1 CE C CEO TC CLR CB2 Q2 Q3

CBD2CE
Q0 Q1 CE C CEO TC CLR CB4 Q4 Q5

CBD2CE
Q0 Q1 CE C CEO TC CLR CB6 TC Q6 Q7 CEO

AND4

X9626

CBD8CE Implementation CoolRunner-II

240

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Libraries Guide ISE 6.li

CBD2CE, CBD4CE, CBD8CE, CBD16CE

Usage
For HDL, these design elements are supported for inference but not instantiation.

VHDL Inference Code


architecture Behavioral of cbd2ce is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif C'event then if (CE='1') then Q <= Q+1; end if; end if; end process; process (Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

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241

CBD2CE, CBD4CE, CBD8CE, CBD16CE

242

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Libraries Guide ISE 6.li

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE


2-, 4-, 8-, 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro

D0 D1 L CE C

CBD2CLE

Q0 Q1

CEO TC

CLR
X9627

D0 D1 D2 D3 L CE C

CBD4CLE

Q0 Q1 Q2 Q3

CBD2CLE, CBD4CLE, CBD8CLE, and CBD16CLE are, respectively, 2-, 4-, 8-, and 16bit (stage) synchronously loadable, asynchronously clearable, cascadable dual edge triggered binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock transition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

CEO TC

CLR D[7:0]

X9628

CBD8CLE

Q[7:0]

L CE C CEO TC

CLR
X9629

Inputs CLR L X 1 1 0 CE X X X 0 C X X Dz D0 X Dn Dn X Qz Q0 0 Dn Dn No Chg

Outputs TC 0 TC TC No Chg CEO 0 CEO CEO 0

D[15:0]

CBD16CLE

Q[15:0]

1 0
CEO TC

L CE C

0 0

CLR
X9630

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243

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

Inputs CLR 0 0 L 0 0 CE 1 1 C Dz D0 X X Qz Q0 Inc Inc

Outputs TC TC TC CEO CEO CEO

z= 1 for CBD2CLE; z = 3 for CBD4CLE; z = 7 for CBD8CLE; z = 15 for CBD16CLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC

CE AND2 Q0 Q1 CEO

FDDC
OR2 GND AND2B1 OR2 D0 AND2 AND2B1 D XOR2 C CLR Q0 Q AND2 AND3 TC

AND2B1 D XOR2 AND3B1 OR2 D1 C CLR AND2 C

FDDC
Q

CLR Q1

X9631

CBD2CLE Implementation CoolRunner-II

244

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Libraries Guide ISE 6.li

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

CBD2CLE
D0 D1 L CE C D0 D1 L CE C CEO TC CLR CLR CB0 Q0 Q1 Q0 Q1

CBD2CLE
D2 D3 D0 D1 L CE C D[7:0] Q0 Q1 CEO TC CLR CB2 Q[7:0] Q2 Q3

CBD2CLE
D4 D5 D0 D1 L CE C Q0 Q1 CEO TC CLR CB4 Q4 Q5

CBD2CLE
D6 D7 D0 D1 L CE C Q0 Q1 CEO TC CLR CB6 Q6 Q7 CEO

TC

AND4

X9632

CBD8CLE Implementation CoolRunner-II

Usage
For HDL, these design elements are supported for inference but not instantiation.

VHDL Inference Code


architecture Behavioral of cbd2cle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then

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245

CBD2CLE, CBD4CLE, CBD8CLE, CBD16CLE

Q <= (others => '0'); elsif C'event then if (L = '1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

246

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Libraries Guide ISE 6.li

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED


2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro

D0 D1 UP L CE C

CBD2CLED Q0
Q1

CEO TC

CLR

X9633

D0 D1 D2 D3 UP L CE C

CBD4CLED Q0
Q1 Q2 Q3

CBD2CLED, CBD4CLED, CBD8CLED, and CBD16CLED are, respectively, 2-, 4-, 8and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional dual edge triggered binary counters. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-to-High and High-to-Low clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low. For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. To cascade counters, the CEO output of each counter is connected to the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. For CoolRunner-II, see CB2X1, CB4X1, CB8X1, CB16X1 for high-performance cascadable, bidirectional counters. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

CEO TC

CLR

X9634

D[7:0]

CBD8CLED

Q[7:0]

UP L CE C CEO TC

CLR

X9635

D[15:0] CBD16CLED Q[15:0] UP L CE C CEO TC

CLR

X9636

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247

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

Inputs CLR 1 0 0 0 0 0 0 0 L X 1 1 0 0 0 0 0 CE X X X 0 1 1 1 1 C X X UP X X X X 1 1 0 0 Dz D0 X Dn Dn X X X X X Qz Q0 0 Dn Dn No Chg Inc Inc Dec Dec

Outputs TC 0 TC TC No Chg TC TC TC TC CEO 0 CEO CEO 0 CEO CEO CEO CEO

z = 1 for CBD2CLED; z = 3 for CBD4CLED; z = 7 for CBD8CLED; z = 15 for CBD16CLED TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP) CEO = TCCE

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CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

VCC

CE
AND2

UP
OR2 GND

AND3B2

FDDC
D AND3B1 OR2 OR3 XOR2 C CLR Q0 AND2 Q Q0

GND

D0

AND2B1

AND4B3

FDDC
D AND4B1 OR3 XOR2 C CLR Q1 AND2 Q Q1

D1

AND2B1

AND5B4

FDDC
D OR3 AND5B1 XOR2 C CLR Q2 AND2 Q Q2

D2

AND2B1

INV INV INV INV INV AND6

FDDC
INV OR3 AND6 XOR2 D C CLR Q3 Q Q3

D3
AND2

AND2B1

AND5 OR2

TC

AND5B5

INV INV INV INV INV

AND6 OR2

CEO

AND6

C CLR

X9637

CBD4CLED Implementation CoolRunner-II

Libraries Guide ISE 6.li

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249

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

Usage
For HDL, these design elements are supported for inference but not instantiation.

VHDL Inference Code


architecture Behavioral of cbd2cled is constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event) then if (L = '1') then Q <= D; elsif (CE='1') then if (UP='1') then Q <= Q+1; elsif (UP='0') then Q <= Q-1; end if; end if; end if; end process; process(Q, UP) begin if (((Q = TERMINAL_COUNT_UP) and (UP = '1')) or ((Q = TERMINAL_COUNT_DOWN) and (UP = '0'))) then TC <='1'; else TC <='0'; end if; end process; CEO <=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (UP) Q <= Q + 1;

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CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

else if (!UP) Q <= Q - 1; end end always @ (Q or UP) begin if ((Q == TERMINAL_COUNT_UP && UP) || (Q == TERMINAL_COUNT_DOWN && !UP)) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

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251

CBD2CLED, CBD4CLED, CBD8CLED, CBD16CLED

252

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Libraries Guide ISE 6.li

CBD2RE, CBD4RE, CBD8RE, CBD16RE

CBD2RE, CBD4RE, CBD8RE, CBD16RE


2-, 4-, 8-, 16-Bit Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CBD2RE, CBD4RE, CBD8RE, CBD16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro

CBD2RE

Q0 Q1 CEO TC

CE C

X9638

CBD4RE

Q0 Q1 Q2 Q3

CBD2RE, CBD4RE, CBD8RE, and CBD16RE are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, resettable, cascadable dual edge triggered binary counters. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero during the Low-to-High or High-to-Low clock transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when both Q outputs are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

CE C

CEO TC

R
X9639

CBD8RE
CE C

Q[7:0] CEO TC

R
X9640

Inputs
CBD16RE
CE C Q[15:0] CEO TC

Outputs C X Qz Q0 0 0 No Chg Inc TC 0 0 No Chg TC CEO 0 0 0 CEO

R 1 1 0 0

CE X X 0 1

X9641

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253

CBD2RE, CBD4RE, CBD8RE, CBD16RE

Inputs R 0 CE 1 C Qz Q0 Inc

Outputs TC TC CEO CEO

z = 1 for CBD2RE; z = 3 for CBD4RE; z = 7 for CBD8RE; z = 15 for CBD16RE TC = QzQ(z-1)Q(z-2)...Q0) CEO = TCCE
VCC

CE AND2 R CEO AND3

FDD
D AND2B1 XOR2 C Q0 AND2B1 Q AND2 TC

FDD
D AND3B1 XOR2 C Q1 C AND2B1 Q

Q0 Q1

X9642

CBD2RE Implementation CoolRunner-II

254

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CBD2RE, CBD4RE, CBD8RE, CBD16RE

CBD2RE
Q0 CE C Q1 CE C R R CB0 CEO TC Q0 Q1

CBD2RE
Q0 Q1 CE C R CB2 CEO TC Q2 Q3

CBD2RE
Q0 Q1 CE C R CB4 CEO TC Q4 Q5

CBD2RE
Q0 Q1 CE C R CB6 CEO TC Q6 Q7 CEO Q[7:0]

TC

AND4
X9643

CBD8RE Implementation CoolRunner-II

Usage
For HDL, these design elements are supported for inference but not instantiation.

Libraries Guide ISE 6.li

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255

CBD2RE, CBD4RE, CBD8RE, CBD16RE

VHDL Inference Code


architecture Behavioral of cbd2re is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, R) begin if (C'event) then if (R='1') then Q <= (others => '0'); elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <='1'; else TC <='0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

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CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE


2-, 4-, 8-, 16-Bit Loadable Cascadable Dual Edge Triggered Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
D0 D1

No No No No No No Macro

CBD2RLE

Q0 Q1

L CE C CEO TC

X9644

CBD2RLE, CBD4RLE, CBD8RLE, and CBD16RLE are, respectively, 2-, 4-, 8-, and 16bit (stage), synchronous, loadable, resettable, cascadable dual edge triggered binary counters. The synchronous reset (R) is the highest priority input. The synchronous R, when High, overrides all other inputs and resets the Q outputs, terminal count (TC), and clock enable out (CEO) outputs to Low on the Low-to-High or High-to-Low clock (C) transition. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High and High-to-Low clock (C) transition, independent of the state of CE. The Q outputs increment when CE is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. The CEO output is High when all Q outputs and CE are High to allow direct cascading of counters. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and by connecting the C, L, and R inputs in parallel. The maximum length of the counter is determined by the accumulated CE-to-CEO propagation delays versus the clock period. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

D0 D1 D2 D3 L CE C

CBD4RLE

Q0 Q1 Q2 Q3

CEO TC

X9645

D[7:0]

CBD8RLE

Q[7:0]

L CE C CEO TC

X9646

D[15:0]

CBD16RLE

Q[15:0]

L CE C CEO TC

X9647

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257

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

Inputs R 1 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 C X Dz D0 X X Dn Dn X X X Qz Q0 0 0 Dn Dn No Chg Inc Inc

Outputs TC 0 0 TC TC No Chg TC TC CEO 0 0 CEO CEO 0 CEO CEO

z = 1 for CBD2RLE; z = 3 for CBD4RLE; z = 7 for CBD8RLE; z = 15 for CBD16RLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE
VCC

CE AND2 L OR2 GND

CEO AND3

Q1 AND3B2 D0 Q0

OR2 AND3B1 XOR2 C D

FDD
TC Q AND2

Q0 AND3B2

AND4B2 D1

OR2 AND3B1 XOR2 C D

FDD
Q

Q1 AND3B2 C
X9648

CBD2RLE Implementation CoolRunner-II

258

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CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

CBD2RLE
D0 D1 L CE C R Q0 D0 Q1 D1 L CE CEO TC C R CB0 Q0 Q1

CBD2RLE
D2 D3 D0 Q0 D1 Q1 L CE CEO C TC R CB2 Q2 Q3

CBD2RLE
D4 D5 Q0 D0 Q1 D1 L CE CEO TC C R CB4 Q4 Q5

CBD2RLE
D6 D7 D0 Q0 D1 Q1 L CE CEO C TC R D[7:0] Q[7:0] TC CB6 Q6 Q7 CEO

AND4
X9649

CBD8RLE Implementation CoolRunner-II

Usage
For HDL, these design elements are supported for inference but not instantiation.

VHDL Inference Code


architecture Behavioral of cbd2rle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, R) begin if (C'event) then if (R='1') then Q <= (others => '0'); elsif (L='1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin

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259

CBD2RLE, CBD4RLE, CBD8RLE, CBD16RLE

if (Q = TERMINAL_COUNT) then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

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CBD2X1, CBD4X1, CBD8X1, CBD16X1

CBD2X1, CBD4X1, CBD8X1, CBD16X1


2-, 4-, 8-, 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CBD2X1, CBD4X1, CBD8X1, CBD16X1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro

D0 D1 L CEU CED C

CBD2X1

QO Q1 TCU TCD CEOU CEOD

CBD2X1, CBD4X1, CBD8X1, and CBD16X1 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronously loadable, asynchronously clearable, bidirectional dual edge triggered binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support highspeed cascading in the CoolRunner-II architecture. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, clock enable outputs CEOU and CEOD go to Low and High, respectively, independent of clock transitions. The data on the D inputs loads into the counter on the Low-to-High and High-to-Low clock (C) transition when the load enable input (L) is High, independent of the CE inputs. The Q outputs increment when CEU is High, provided CLR and L are Low, during the Low-to-High and High-to-Low clock transition. The Q outputs decrement when CED is High, provided CLR and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are connected directly to the CEU and CED inputs, respectively, of the next stage. The clock, L, and CLR inputs are connected in parallel. In CoolRunner-II, the maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable

CLR

X9650

D0 D1 D2 D3 CEU CED L C

CBD4X1

Q0 Q1 Q2 Q3 TCU TCD CEOU CEOD

CLR
X9651

D[7:0]

CBD8X1

Q[7:0] TCU

L CEU CED C

TCD CEOU CEOD

CLR
X9652

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261

CBD2X1, CBD4X1, CBD8X1, CBD16X1

D[15:0]

CBD16X1

Q[15:0] TCU

AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

L CEU CED C

TCD CEOU CEOD

CLR
X9653

Inputs CLR 1 0 0 0 0 0 0 0 0 0 L X 1 1 0 0 0 0 0 0 0 CEU X X X 0 1 1 0 0 1 1 CED X X X 0 0 0 1 1 1 1 C X X DzD0 X Dn Dn X X X X X X X QzQ0 0 Dn Dn No Chg Inc Inc Dec Dec Inc Inc TCU 0 TCU TCU No Chg TCU TCU TCU TCU TCU TCU

Outputs TCD 1 TCD TCD No Chg TCD TCD TCD TCD TCD TCD CEOU 0 CEOU CEOU 0 CEOU CEOU 0 0 Invalid Invalid CEOD CEOD CEOD CEOD 0 0 0 CEOD CEOD Invalid Invalid

z = 1 for CBD2X1; z = 3 for CBD4X1; z = 7 for CBD8X1; z = 15 for CBD16X1 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED

CBD4X1 Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

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CBD2X1, CBD4X1, CBD8X1, CBD16X1

VHDL Inference Code


architecture Behavioral of cbd2x1 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif C'event then if (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process(Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU_INT <= '1'; TCD_INT <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU <= TCU and CEU; CEOD <= TCD and CED; end Behavioral;

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263

CBD2X1, CBD4X1, CBD8X1, CBD16X1

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @ (TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end

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CBD2X2, CBD4X2, CBD8X2, CBD16X2

CBD2X2, CBD4X2, CBD8X2, CBD16X2


2-, 4-, 8-, and 16-Bit Loadable Cascadable Bidirectional Dual Edge Triggered Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CBD2X2, CBD4X2, CBD8X2, CBD16X2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Macro

D0 D1 L CEU CED C

CBD2X2

QO Q1 TCU TCD CEOU CEOD

CBD2X2, CBD4X2, CBD8X2, and CBD16X2 are, respectively, 2-, 4-, 8-, and 16-bit (stage), synchronous, loadable, resettable, bidirectional dual edge triggered binary counters. These counters have separate count-enable inputs and synchronous terminal-count outputs for up and down directions to support high-speed cascading in the CoolRunner-II architecture. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the data outputs (Q) go to logic level zero, terminal count outputs TCU and TCD go to zero and one, respectively, and clock enable outputs CEOU and CEOD go to Low and High, respectively, on the Low-to-High and High-to-Low clock (C) transition. The data on the D inputs loads into the counter on the Low-to-High and High-to-Low clock (C) transition when the load enable input (L) is High, independent of the CE inputs. All Q outputs increment when CEU is High, provided R and L are Low during the Low-to-High and High-to-Low clock transition. All Q outputs decrement when CED is High, provided R and L are Low. The counter ignores clock transitions when CEU and CED are Low. Both CEU and CED should not be High during the same clock transition; the CEOU and CEOD outputs might not function properly for cascading when CEU and CED are both High. For counting up, the CEOU output is High when all Q outputs and CEU are High. For counting down, the CEOD output is High when all Q outputs are Low and CED is High. To cascade counters, the CEOU and CEOD outputs of each counter are, respectively, connected directly to the CEU and CED inputs of the next stage. The C, L, and R inputs are connected in parallel. In CoolRunner-II, the maximum clocking frequency of these counter components is unaffected by the number of cascaded stages for all counting and loading functions. The TCU terminal count output is High when all Q outputs are High, regardless of CEU. The TCD output is High when all Q outputs are Low, regardless of CED. When cascading counters, the final terminal count signals can be produced by AND wiring all the TCU outputs (for the up direction) and all the TCD outputs (for the down direction). The TCU, CEOU, and CEOD outputs are produced by optimizable

X9655

D0 D1 D2 D3 L CEU CED C

CBD4X2

Q0 Q1 Q2 Q3 TCU TCD CEOU CEOD

R
X9656

D[7:0]

CBD8X2

Q[7:0] TCU

L CEU CED C

TCD CEOU CEOD

X9657

D[15:0]

CBD16X2

Q[15:0] TCU

L CEU CED C

TCD CEOU CEOD

X9658

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265

CBD2X2, CBD4X2, CBD8X2, CBD16X2

AND gates within the component. This results in zero propagation from the CEU and CED inputs and from the Q outputs, provided all connections from each such output remain on-chip. Otherwise, a macrocell buffer delay is introduced. The counter is initialized to zero (TCU Low and TCD High) when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Inputs R 1 1 0 0 0 0 0 0 0 0 0 L X X 1 1 0 0 0 0 0 0 0 CEU X X X X 0 1 1 0 0 1 1 CED X X X X 0 0 0 1 1 1 1 C X Dz D0 X X Dn Dn X X X X X X X Qz Q0 0 0 Dn Dn No Chg Inc Inc Dec Dec Inc Inc TCU 0 0 TCU TCU No Chg TCU TCU TCU TCU TCU TCU

Outputs TCD 1 1 TCD TCD No Chg TCD TCD TCD TCD TCD TCD CEOU 0 0 CEOU CEOU 0 CEOU CEOU 0 0 Invalid Invalid CEOD CEOD CEOD CEOD CEOD 0 0 0 CEOD CEOD Invalid Invalid

z = 1 for CBD2X2; z = 3 for CBD4X2; z = 7 for CBD8X2; z = 15 for CBD16X2 TCU = QzQ(z-1)Q(z-2)...Q0 TCD = QzQ(z-1)Q(z-2)...Q0 CEOU = TCUCEU CEOD = TCDCED

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CBD2X2, CBD4X2, CBD8X2, CBD16X2

L OR2

Q3 Q2 Q1 Q0

CED OR2 R AND4B3 AND4 TCD INV TCU

FDD
AND3B2 OR3 XOR2 C AND3B2 D0 Q0 AND2 CEQD D Q AND3B1 CEQU

AND3B1 CEU OR2

GND

AND5B4

FDD
AND4B2 OR3 D XOR2 C Q1 Q

AND3B2 D1

AND3B1

INV INV INV INV INV AND6

OR3 AND5B2 XOR2 D C

FDDC
Q

AND3B2 D2

Q2

AND3B1

INV INV INV INV INV INV AND7

INV INV OR3 AND6 XOR2 D C Q3

FDDC
Q

AND3B2 D3

AND3B1 INV INV INV INV INV INV INV AND7

INV INV INV INV INV AND7 D C TCDINV

FDDC
Q

NOR5 INV

AND6

AND5B4 C
X9659

CBD4X2 Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

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267

CBD2X2, CBD4X2, CBD8X2, CBD16X2

VHDL Inference Code


architecture Behavioral of cbd2x2 is signal CEU_INT : std_logic; signal CED_INT : std_logic; constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C) begin if (C'event) then if (R='1') then Q <= (others => '0'); CEU_INT <= '0'; CED_INT <= '1'; elsif (L = '1') then Q <= D; CEU_INT <= CEU; CED_INT <= CED; elsif (CEU='1') then Q <= Q+1; CEU_INT <= '1'; CED_INT <= '0'; elsif (CED='1') then Q <= Q-1; CEU_INT <= '0'; CED_INT <= '1'; end if; end if; end process; process(Q, CEU_INT, CED_INT) begin if ((Q = TERMINAL_COUNT_UP) and (CEU_INT = '1')) then TCU_INT <= '1'; TCD_INT <= '0'; elsif ((Q = TERMINAL_COUNT_DOWN) and (CED_INT = '1')) then TCU <= '0'; TCD <= '1'; else TCU <= '0'; TCD <= '0'; end if; end process; CEOU <= TCU and CEU; CEOD <= TCD and CED; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C)

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CBD2X2, CBD4X2, CBD8X2, CBD16X2

begin if (R) begin Q <= 0; CEU_INT <= 1'b0; CED_INT <= 1'b1; end else if (L) begin Q <= D; CEU_INT <= CEU; CED_INT <= CED; end else if (CEU) begin Q <= Q + 1; CEU_INT <= 1; CED_INT <= 0; end else if (CED) begin Q <= Q - 1; CEU_INT <= 1'b0; CED_INT <= 1'b1; end end always @ (Q or CEU_INT or CED_INT) begin if (Q == TERMINAL_COUNT_UP && CEU_INT) begin TCU_INT <= 1; TCD_INT <= 0; end else if ((Q == TERMINAL_COUNT_DOWN) && CED_INT) begin TCU_INT <= 0; TCD_INT <= 1; end else begin TCU_INT <= 0; TCD_INT <= 0; end end always @ (TCU_INT or CEU or TCD_INT or CED) begin CEOU <= TCU_INT && CEU; CEOD <= TCD_INT && CED; TCU <= TCU_INT; TCD <= TCD_INT; end

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269

CBD2X2, CBD4X2, CBD8X2, CBD16X2

270

www.xilinx.com 1-800-255-7778

Libraries Guide ISE 6.li

CC8CE, CC16CE

CC8CE, CC16CE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CC8CE, CC16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CC8CE
CE C

Q[7:0] CEO TC

CLR

X4290

CC16CE
CE C

Q[15:0] CEO TC

CC8CE and CC16CE are, respectively, 8- and 16-bit (stage), asynchronous clearable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, with Low outputs, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 CE X 0 C X X Qz Q0 0 No Chg Outputs TC 0 No Chg CEO 0 0

CLR X4286

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271

CC8CE, CC16CE

Inputs CLR 0 CE 1 C Qz Q0 Inc

Outputs TC TC CEO CEO

z = 7 for CC8CE; z = 15 for CC16CE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE

TC CEO AND2 Q[7:0]

Q7

MUXCY O RLOC=R0C0.S1 S 0 1 CI DI LI CI C7 XORCY

FMAP FDCE O TQ7 D Q CE C CLR RLOC=R0C0.S0 FDCE O TQ6 D Q CE C CLR RLOC=R0C0.S0 FDCE O TQ5 D Q CE C CLR RLOC=R1C0.S0 FDCE O TQ4 D Q CE C CLR RLOC=R1C0.S0 FMAP FDCE O TQ3 D Q CE C CLR RLOC=R2C0.S0 FDCE O TQ2 D Q CE C CLR RLOC=R2C0.S0 FDCE O TQ1 D Q CE C CLR RLOC=R3C0.S0 FDCE O TQ0 D Q CE C CLR RLOC=R3C0.S0 Q0 C0 Q0 Q1 C1 Q1 Q2 C2 Q2 Q3 C3 Q3 I4 I3 I2 I1 TQ3 Q4 C4 Q4 Q5 C5 Q5 Q6 C6 Q6 Q7 C7 Q7 I4 I3 I2 I1 TQ7

Q6

MUXCY_L LO S RLOC=R0C0.S1 0 1 DI CI LI CI C6 XORCY

RLOC=R0C0.S0 FMAP I4 I3 I2 I1 TQ6

Q5

MUXCY_L LO RLOC=R1C0.S1 S 0 1 CI DI LI CI C5 XORCY

RLOC=R0C0.S0 FMAP I4 I3 I2 I1 TQ5

Q4

MUXCY_L LO S RLOC=R1C0.S1 0 1 CI DI LI CI C4 XORCY

RLOC=R1C0.S0 FMAP I4 I3 I2 I1 TQ4

Q3

MUXCY_L LO RLOC=R2C0.S1 S 0 1 CI DI LI CI C3 XORCY

RLOC=R1C0.S0

Q2

MUXCY_L LO S RLOC=R2C0.S1 0 1 DI CI LI CI C2 XORCY

RLOC=R2C0.S0 FMAP I4 I3 I2 I1 TQ2

Q1

MUXCY_L LO S RLOC=R3C0.S1 0 1 CI DI LI CI C1 XORCY

RLOC=R2C0.S0 FMAP I4 I3 I2 I1 TQ1

Q0

MUXCY_L LO S RLOC=R3C0.S1 0 1 CI DI LI CI C0 XORCY

RLOC=R3C0.S0 FMAP I4 I3 I2 I1 TQ0

GND VCC

RLOC=R3C0.S0

CE C CLR

X8890

CC8CE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

272

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CC8CE, CC16CE

TC

CEO AND2 Q[7:0]

O Q7 S MUXCY 0 DI 1 CI LI O TQ7 CI XORCY C7 LO Q6 S MUXCY_L 0 DI 1 CI LI O TQ6 CI XORCY C6 LO Q5 S MUXCY_L 0 1 DI CI LI O TQ5 CI XORCY C5 LO Q4 S MUXCY_L 0 DI 1 CI LI O TQ4 CI XORCY C4 LO Q3 S MUXCY_L 0 DI 1 CI LI O TQ3 CI XORCY C3 LO Q2 S MUXCY_L 0 1 DI CI LI O TQ2 CI XORCY C2 LO Q1 S MUXCY_L 0 1 DI CI LI O TQ1 CI XORCY C1 LO Q0 S MUXCY_L 0 DI 1 CI LI O TQ0 CI XORCY GND VCC C0 D CE C CLR RLOC=X0Y0 RLOC=X0Y0 D CE C CLR RLOC=X0Y0 RLOC=X0Y1 D CE C CLR RLOC=X0Y1 RLOC=X0Y1 D CE C CLR RLOC=X0Y1 RLOC=X0Y2 D CE C CLR RLOC=X0Y2 RLOC=X0Y2 D CE C CLR RLOC=X0Y2 RLOC=X0Y3 D CE C CLR RLOC=X0Y3 RLOC=X0Y3 D CE C CLR RLOC=X0Y3

FDCE
Q Q7

FDCE
Q Q6

FDCE
Q Q5

FDCE
Q Q4

FDCE
Q Q3

FDCE
Q Q2

FDCE
Q Q1

FDCE
Q Q0

RLOC=X0Y0 CE C CLR X9309

CC8CE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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273

CC8CE, CC16CE

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cc8ce is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (CE='1') then Q <= Q+1; end if; end if; end process; process (Q) begin if (Q = TERMINAL_COUNT) then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end

274

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CC8CE, CC16CE

always @ (TC or CE) begin CEO <= TC & CE; end

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275

CC8CE, CC16CE

276

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Libraries Guide ISE 6.li

CC8CLE, CC16CLE

CC8CLE, CC16CLE
8-, 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CC8CLE, CC16CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D[7:0]

CC8CLE

Q[7:0] CEO

L CE C

TC

CC8CLE and CC16CLE are, respectively, 8- and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, with Low output, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

CLR

X4289

D[15:0]

CC16CLE Q[15:0]
CEO TC

L CE C

CLR

X4284

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277

CC8CLE, CC16CLE

GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 L X 1 0 0 CE X X 0 1 C X X Dz D0 X Dn X X Qz Q0 0 Dn No Chg Inc Outputs TC 0 TC No Chg TC CEO 0 CEO 0 CEO

z = 7 for CC8CLE; z = 15 for CC16CLE TC = QzQ(z-1)Q(z-2)...Q0 CEO = TCCE

278

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CC8CLE, CC16CLE

TC CEO AND2 MUXCY S 0 DI O 1 CI RLOC=R0C0.S1 L LI CI M2_1 O TQ7 D7 XORCY RLOC=R0C0.S1 RLOC=R0C0.S0 CI LI CI C6 MUXCY_L Q5 S DI 0 LO 1 CI RLOC=R1C0.S1 LI CI M2_1 O TQ5 D5 XORCY RLOC=R1C0.S1 1 CI LI CI M2_1 O TQ4 D4 XORCY D0 D1 S0 O MD4 RLOC=R1C0.S0 FDCE D Q CE C CLR RLOC=R1C0.S0 M2_1 O TQ3 D3 XORCY RLOC=R2C0.S1 0 DI 1 CI LI CI M2_1 O TQ2 D2 XORCY D0 D1 S0 O MD2 RLOC=R2C0.S0 FDCE D Q CE C CLR RLOC=R2C0.S0 M2_1 O TQ1 D1 XORCY RLOC=R3C0.S1 RLOC=R3C0.S0 CI LI CI M2_1 O TQ0 D0 XORCY C0 VCC D0 D1 S0 O MD0 FDCE Q0 D Q CE C CLR RLOC=R3C0.S0 D[7:0] L CE C CLR OR2 X8891 L_CE L D0 TQ0 D0 D1 S0 O MD1 D Q CE C CLR FDCE Q1 L D1 TQ1 Q2 L D2 TQ2 FMAP I4 I3 I2 I1 RLOC=R2C0.S0 FMAP I4 I3 I2 I1 RLOC=R3C0.S0 FMAP I4 I3 I2 I1 RLOC=R3C0.S0 O MD0 O MD1 O MD2 D0 D1 S0 O MD3 FDCE D Q CE C CLR Q3 L D3 TQ3 Q4 L D4 TQ4 RLOC=R1C0.S0 FMAP I4 I3 I2 I1 RLOC=R1C0.S0 FMAP I4 I3 I2 I1 RLOC=R2C0.S0 O MD3 O MD4 D0 D1 S0 O MD5 O TQ6 D6 XORCY D0 D1 S0 M2_1 O MD6 FDCE D Q CE C CLR RLOC=R0C0.S0 FDCE D Q CE C CLR Q5 L D5 TQ5 Q6 L D6 TQ6 D0 D1 S0 O MD7 FDCE D Q CE C CLR Q7 D7 TQ7 FMAP I4 I3 I2 I1 RLOC=R0C0.S0 FMAP I4 I3 I2 I1 RLOC=R0C0.S0 FMAP I4 I3 I2 I1 O MD5 O MD6 O MD7 Q[7:0]

Q7

C7 Q6 MUXCY_L S 0 DI LO 1

C5 Q4 MUXCY_L S 0 DI LO

C4 MUXCY_L Q3 S DI 0 LO 1 CI

RLOC=R2C0.S1 LI CI

C3 MUXCY_L Q2 S LO

C2 Q1 MUXCY_L S 0 DI LO

RLOC=R3C0.S1 1 CI LI CI C1

MUXCY_L Q0 S DI 0

LO 1

GND

CC8CLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide ISE 6.li

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279

CC8CLE, CC16CLE

TC

CEO AND2 Q[7:0]

O Q7 S MUXCY 0 1 DI CI LI O CI D7 XORCY C7 LO Q6 S MUXCY_L 0 1 DI CI LI O CI D6 XORCY S0 C6 LO Q5 S MUXCY_L 0 1 DI CI LI O CI D5 XORCY C5 LO Q4 S MUXCY_L 0 1 DI CI LI O CI D4 XORCY S0 C4 LO Q3 S MUXCY_L 0 1 DI CI LI O CI D3 XORCY C3 LO Q2 S MUXCY_L 0 1 DI CI LI O CI D2 XORCY S0 C2 LO Q1 S MUXCY_L 0 1 DI CI LI O CI D1 XORCY C1 LO Q0 S MUXCY_L 0 1 DI CI LI O CI D0 XORCY GND VCC C0 S0 D1 TQ0 D0 O MD0 D CE C CLR Q Q0 TQ0 RLOC=X0Y0 RLOC=X1Y0 L I4 I3 O I2 I1 RLOC=X1Y0 MD0 S0 D1 TQ1 D0 O MD1 D CE C CLR Q Q1 TQ1 RLOC=X0Y0 RLOC=X1Y1 L D1 TQ2 D0 O MD2 D CE C CLR Q Q2 TQ2 RLOC=X0Y1 RLOC=X1Y1 L I4 I3 O I2 I1 RLOC=X1Y1 MD2 S0 D1 TQ3 D0 O MD3 D CE C CLR Q Q3 TQ3 RLOC=X0Y1 RLOC=X1Y2 L D1 TQ4 D0 O MD4 D CE C CLR Q Q4 TQ4 RLOC=X0Y2 RLOC=X1Y2 L I4 I3 O I2 I1 RLOC=X1Y2 MD4 S0 D1 TQ5 D0 O MD5 D CE C CLR Q Q5 TQ5 RLOC=X0Y2 RLOC=X1Y3 L D1 TQ6 D0 O MD6 D CE C CLR Q Q6 TQ6 RLOC=X0Y3 RLOC=X1Y3 L I4 I3 O I2 I1 RLOC=X1Y3 MD6 S0 D1 TQ7 D0 O MD7 D CE C CLR Q Q7 TQ7 RLOC=X0Y3

FMAP
L

M2_1

FDCE

I4 I3 O I2 I1 RLOC=X1Y3 MD7

D7

FMAP

M2_1

FDCE

D6

FMAP
I4 I3 O I2 I1 RLOC=X1Y2 MD5

M2_1

FDCE

D5

FMAP

M2_1

FDCE

D4

FMAP
I4 I3 O I2 I1 RLOC=X1Y1 MD3

M2_1

FDCE

D3

FMAP

M2_1

FDCE

D2

FMAP
I4 I3 O I2 I1 RLOC=X1Y0 MD1

M2_1

FDCE

D1

FMAP

M2_1

FDCE

D0

RLOC=X1Y0 D[7:0] L L_CE CE C CLR OR2 X9310

CC8CLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

280

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Libraries Guide ISE 6.li

CC8CLE, CC16CLE

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cc8cle is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (L = '1') then Q <= D; elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) Q <= Q + 1; end always @ (Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end

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281

CC8CLE, CC16CLE

always @ (TC or CE) begin CEO <= TC & CE; end

282

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Libraries Guide ISE 6.li

CC8CLED, CC16CLED

CC8CLED, CC16CLED
8-, 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CC8CLED, CC16CLED Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D[7:0]

CC8CLED Q[7:0]
CEO TC

UP L CE C

CC8CLED and CC16CLED are, respectively, 8- and 16-bit (stage), synchronously loadable, asynchronously clearable, cascadable, bidirectional binary counters. These counters are implemented using carry logic with relative location constraints, which assures most efficient logic placement. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High and UP is Low during the Low-to-High clock transition. The Q outputs increment when CE and UP are High. The counter ignores clock transitions when CE is Low. For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TC output is High when all Q outputs and UP are Low. To cascade counters, the count enable out (CEO) output of each counter is connected to the CE pin of the next stage. The clock, UP, L, and CLR inputs are connected in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, outputs Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.

CLR

X4287

D[15:0] CC16CLED Q[15:0] CEO UP L CE C TC

CLR

X4285

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283

CC8CLED, CC16CLED

Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 0 1 1 C X X UP X X X 1 0 Dz D0 X Dn X X X Qz Q0 0 Dn No Chg Inc Dec

Outputs TC 0 TC No Chg TC TC CEO 0 CEO 0 CEO CEO

z = 7 for CC8CLED; z = 15 for CC16CLED TC = (QzQ(z-1)Q(z-2)...Q0UP) + (QzQ(z-1)Q(z-2)...Q0UP) CEO = TCCE

284

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CC8CLED, CC16CLED

TC CEO

AND2
Q[7:0]

INV DN7 Q7 XOR2

O SQ7 S
MUXCY

RLOC=R0C0.S1

0 DI

1 CI LI CI XORCY C7 LO

FMAP
I4 I3 I2 I1 O SQ7

TQ7 D7

M2_1
D0 D1 S0 O MD7

FDCE
D Q CE C CLR RLOC=R0C0.S0 Q7

FMAP
L I4 D7 I3 TQ7 I2 I1 O MD7

UP Q7

RLOC=R0C0.S1 Q6

INV DN6 XOR2

RLOC=R0C0.S1

RLOC=R0C0.S0

SQ6

MUXCY_L

FMAP
I4 I3 I2 I1 O SQ6

0 DI

1 CI LI CI XORCY C6

FMAP M2_1
O TQ6 D6 D0 D1 S0 O MD6

FDCE
D Q CE C CLR RLOC=R0C0.S0 Q6

UP Q6

L I4 D6 I3 TQ6 I2 I1

O MD6

RLOC=R0C0.S1 INV DN5 Q5 XOR2 O SQ5 LO SQ5 S


MUXCY_L

RLOC=R0C0.S0

RLOC=R1C0.S1

FMAP
I4 I3 I2 I1

0 DI

FMAP M2_1
O XORCY TQ5 D5 D0 D1 S0 O MD5 L I4 D5 I3 TQ5 I2 I1 O MD5

1 CI LI CI

UP Q5

FDCE
D Q CE C CLR RLOC=R1C0.S0 Q5

RLOC=R1C0.S1 C5

RLOC=R1C0.S0

FMAP
I4 I3 I2 I1 INV DN4 Q4 O SQ4 XOR2 SQ4 S 0 DI

LO
MUXCY_L

RLOC=R1C0.S1

FMAP
L I4 D4 I3 TQ4 I2 I1 Q4 O MD4

UP Q4

1 CI LI CI XORCY TQ4 D4

M2_1
D0 D1 S0 O MD4

FDCE
D Q CE C CLR RLOC=R1C0.S0

RLOC=R1C0.S1

RLOC=R1C0.S0

FMAP
I4 I3 I2 I1 O SQ3 Q3 XOR2 INV DN3 LO SQ3 S

C4

FMAP
L I4 D3 I3 TQ3 I2 I1 O MD3

RLOC=R2C0.S1

UP Q3

MUXCY_L

0 DI

1 CI LI CI XORCY C3 TQ3 D3

RLOC=R2C0.S1

M2_1
D0 D1 S0 O MD3

FDCE
D Q CE C CLR RLOC=R2C0.S0 Q3

RLOC=R2C0.S0

FMAP
I4 I3 I2 I1 O SQ2 INV DN2 Q2 RLOC=R2C0.S1 XOR2 SQ2 S

FMAP
L I4 D2 I3 TQ2 I2 I1 O MD2

UP Q2

LO
MUXCY_L

RLOC=R2C0.S1

0 DI

1 CI LI CI XORCY

RLOC=R2C0.S0

M2_1
O TQ2 D2 D0 D1 S0 O MD2

FDCE
D Q CE C CLR RLOC=R2C0.S0 Q2

FMAP
I4 I3 I2 I1 O SQ1 LO SQ1 XOR2 S
MUXCY_L

FMAP
L I4 D1 I3 TQ1 I2 I1 O MD1

UP Q1

C2 RLOC=R3C0.S1

RLOC=R3C0.S1 Q1

INV DN1

RLOC=R3C0.S0

0 DI

1 CI LI CI

FMAP
I4 I3 I2 I1 O XORCY C1 RLOC=R3C0.S1 INV DN0 Q0 XOR2 SQ0 S LO
MUXCY_L

M2_1
TQ1 D1 D0 D1 S0 O MD1

FDCE
D Q CE C CLR RLOC=R3C0.S0 Q1

FMAP
L I4 D0 I3 TQ0 I2 I1 O MD0

UP Q0

O SQ0

RLOC=R3C0.S0

RLOC=R3C0.S1

0 DI

1 CI LI CI XORCY

M2_1
O TQ0 D0 D0 D1 S0 O MD0

FDCE
D Q CE C CLR RLOC=R3C0.S0 Q0

GND VCC UP

C0

D[7:0] L CE C CLR OR2 X8892 L_CE

CC8CLED Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide ISE 6.li

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285

CC8CLED, CC16CLED

TC

CEO AND2 Q[7:0]

FMAP
I4 I3 UP Q7 O I2 I1 RLOC=X0Y3 DN7 SQ7 Q7 INV XOR2 SQ7 S O MUXCY 0 1 DI CI RLOC=X0Y3

FMAP
L LI O CI D7 D1 S0 XORCY TQ7 D0 O MD7 D CE C CLR RLOC=X0Y3 RLOC=X1Y3 L LI Q Q7 TQ7

M2_1

FDCE

I4 I3 O I2 I1 RLOC=X1Y3 MD7

D7

FMAP
I4 I3 UP Q6 O I2 I1 RLOC=X0Y3 DN6 SQ6 Q6 INV XOR2 SQ6 S LO

C7

MUXCY_L 0 1 DI CI

FMAP
I4 I3 O I2 I1 MD6 D6

M2_1
O TQ6 D6 XORCY D0 O D1 S0 MD6 D

FDCE
Q Q6

CI

TQ6

CE C CLR

FMAP
I4 I3 UP Q5 O I2 I1 RLOC=X0Y2 DN5 SQ5 Q5 INV XOR2 SQ5 S LO

C6

RLOC=X1Y3

MUXCY_L 0 1 DI CI

RLOC=X0Y2 RLOC=X1Y3 L LI O CI D5 D1 S0 XORCY TQ5 D0 O MD5 D CE C CLR RLOC=X0Y2 RLOC=X1Y2 L LI Q Q5 TQ5

FMAP
I4 I3 O I2 I1 RLOC=X1Y2 MD5 D5

M2_1

FDCE

FMAP
I4 I3 UP Q4 O I2 I1 RLOC=X0Y2 DN4 SQ4 Q4 INV XOR2 SQ4 S LO

C5

MUXCY_L 0 1 DI CI

FMAP
I4 I3 O I2 I1 MD4 D4

M2_1
O TQ4 D4 D0 O D1 S0 XORCY MD4 D

FDCE
Q Q4

CI C4 LO

TQ4

CE C CLR

FMAP
I4 I3 UP Q3 O I2 I1 RLOC=X0Y1 SQ3 Q3 INV XOR2 DN3 SQ3 S

RLOC=X1Y2

MUXCY_L 0 1 DI CI

RLOC=X0Y1 RLOC=X1Y2

FMAP
L Q3 D3 TQ3 I4 I3 O I2 I1 MD3

LI CI C3 LO XORCY O TQ3 D3 D0 D1 S0

M2_1
O MD3 D

FDCE
Q

CE C CLR

FMAP
I4 I3 UP Q2 O I2 I1 RLOC=X0Y1 SQ2 Q2 INV XOR2 DN2 SQ2 S

MUXCY_L 0 1 DI CI

RLOC=X0Y1 RLOC=X1Y1

RLOC=X1Y1

FMAP
L D2 Q2 TQ2 I4 I3 O I2 I1 MD2

LI O CI D2 XORCY C2 LO D1 S0 TQ2 D0

M2_1
O MD2 D

FDCE
Q

CE C CLR RLOC=X1Y1

FMAP
I4 I3 UP Q1 O I2 I1 RLOC=X0Y0 SQ1 Q1 INV XOR2 DN1 SQ1 S

MUXCY_L 0 1 DI CI

RLOC=X0Y0 RLOC=X1Y1

FMAP
LI O CI D1 D1 S0 XORCY TQ1 D0 O MD1 D CE I1 C CLR RLOC=X0Y0 RLOC=X1Y0 RLOC=X1Y0 Q Q1 TQ1

M2_1

FDCE

L D1

I4 I3 O I2 MD1

C1

FMAP
I4 I3 UP Q0 O I2 I1 RLOC=X0Y0 Q0 SQ0 XOR2 INV DN0 SQ0 S

LO MUXCY_L 0 1 DI CI

FMAP
L D0 Q0 TQ0 I4 I3 O I2 I1 MD0

LI O CI D0 XORCY C0 VCC UP D[7:0] L GND D1 S0 TQ0 D0

M2_1
O MD0 D

FDCE
Q

CE C CLR RLOC=X1Y0 RLOC=X1Y0

L_CE CE C CLR OR2 X9311

CC8CLED Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

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CC8CLED, CC16CLED

VHDL Inference Code


architecture Behavioral of cc8cled is constant TERMINAL_COUNT_UP : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); constant TERMINAL_COUNT_DOWN : std_logic_vector(WIDTH-1 downto 0) := (others => '0'); begin process(C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C'event and C='1') then if (L = '1') then Q <= D; elsif (CE='1') then if (UP='1') then Q <= Q+1; elsif (UP='0') then Q <= Q-1; end if; end if; end if; end process; process(Q, UP) begin if (((Q = TERMINAL_COUNT_UP) and (UP = '1')) or ((Q = TERMINAL_COUNT_DOWN) and (UP = '0'))) then TC<='1'; else TC<='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (UP) Q <= Q + 1; else if (!UP) Q <= Q - 1;

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CC8CLED, CC16CLED

end end always @ (Q or UP) begin if ((Q == TERMINAL_COUNT_UP && UP) || (Q == TERMINAL_COUNT_DOWN && !UP)) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC & CE; end

288

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Libraries Guide ISE 6.li

CC8RE, CC16RE

CC8RE, CC16RE
8-, 16-Bit Cascadable Binary Counters with Clock Enable and Synchronous Reset
Architectures Supported
CC8RE, CC16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CC8RE
CE C

Q[7:0] CEO TC

X4288

CC16RE
CE C

Q[15:0] CEO TC

CC8RE and CC16RE are, respectively, 8- and 16-bit (stage), synchronous resettable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The synchronous reset (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs and CE are High. Larger counters are created by connecting the CEO output of the first stage to the CE input of the next stage and connecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, with Low outputs, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 CE X 0 C X Qz Q0 0 No Chg Outputs TC 0 No Chg CEO 0 0

X4283

Libraries Guide ISE 6.li

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289

CC8RE, CC16RE

Inputs R 0 CE 1 C Qz Q0 Inc

Outputs TC TC CEO CEO

z = 7 for CC8RE; z = 15 for CC16RE TC = QzQ(z-1)Q(z-2)...Q0CE CEO = TCCE

290

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CC8RE, CC16RE

TC CEO AND2 Q[7:0]

O MUXCY Q7 S 0 DI 1 CI LI CI C7 LO XORCY INV RLOC=R0C0.S1 0 DI 1 CI LI CI C6 LO MUXCY_L Q5 S 0 DI 1 CI LI CI C5 LO MUXCY_L Q4 S 0 DI 1 CI LI CI C4 LO MUXCY_L Q3 S 0 DI 1 CI LI CI C3 LO MUXCY_L Q2 S 0 DI 1 CI LI CI C2 LO MUXCY_L Q1 S 0 DI 1 CI LI CI C1 MUXCY_L Q0 S 0 DI 1 CI LI CI XORCY GND VCC C0 INV O LO RLOC=R3C0.S1 XORCY INV RLOC=R3C0.S1 RLOC=R2C0.S0 CE Q1 TQ1 Q Q1 R XORCY INV RLOC=R2C0.S1 XORCY INV O RLOC=R2C0.S1 RLOC=R1C0.S0 CE Q3 O CE_M3 TQ3 Q Q3 R XORCY INV O RLOC=R1C0.S1 XORCY INV O TQ5 Q5 RLOC=R1C0.S1 RLOC=R0C0.S0 CE Q5 O CE_M5 TQ5 Q Q5 R XORCY INV O TQ7 Q7 RLOC=R0C0.S1 VCC

FMAP
M2_1
D0 D1 S0 CEB7 O CE_M7 CE Q7 I4 I3 I2 I1 RLOC=R0C0.S0 CLR RLOC=R0C0.S0 CE Q6 TQ6 Q Q6 R R_TQ7 O

FDCE
R_TQ7 AND2B1 D CE C Q Q7

TQ7 R

MUXCY_L Q6 S

FMAP
I4 I3 I2 I1 RLOC=R0C0.S0 O R_TQ6

M2_1
O TQ6 Q6 D0 D1 S0 CEB6 AND2B1 O CE_M6

FDCE
R_TQ6 D CE C CLR

FMAP
M2_1
D0 D1 S0 CEB5 I4 I3 I2 I1 RLOC=R1C0.S0 CLR RLOC=R1C0.S0 CE Q4 O CE_M4 TQ4 Q Q4 R R_TQ5 O

FDCE
R_TQ5 AND2B1 D CE C

FMAP
I4 I3 I2 I1 RLOC=R1C0.S0 R_TQ4 O

M2_1
TQ4 Q4 D0 D1 S0 CEB4 AND2B1

FDCE
R_TQ4 D CE C CLR

FMAP
I4 I3 I2 I1 RLOC=R2C0.S0 CLR RLOC=R2C0.S0 CE Q2 O CE_M2 TQ2 Q Q2 R R_TQ3 O

M2_1
TQ3 Q3 D0 D1 S0 CEB3 AND2B1 R_TQ3

FDCE
D CE C

FMAP
I4 I3 I2 I1 RLOC=R2C0.S0 R_TQ2 O

M2_1
O TQ2 Q2 D0 D1 S0 CEB2 AND2B1

FDCE
R_TQ2 D CE C CLR

FMAP
I4 I3 I2 I1 RLOC=R3C0.S0 CLR RLOC=R3C0.S0 CE Q0 O CE_M0 TQ0 Q Q0 R R_TQ1 O

M2_1
O TQ1 Q1 D0 D1 S0 CEB1 AND2B1 O CE_M1 R_TQ1

FDCE
D CE C

FMAP
I4 I3 I2 I1 RLOC=R3C0.S0 R_TQ0 O

M2_1
TQ0 Q0 D0 D1 S0 CEB0 AND2B1 R_TQ0

FDCE
D CE C CLR RLOC=R3C0.S0

CE R C GND

X8893

CC8RE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide ISE 6.li

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291

CC8RE, CC16RE

TC

CEO AND2 Q[7:0]

O Q7 S MUXCY 0 1 DI CI LI O CI Q7 XORCY C7 LO Q6 S MUXCY_L 0 1 DI CI RLOC=X1Y3 INV S0 AND2B1 CEB7 D1 TQ7 D0 O RLOC=X1Y3

VCC

FMAP
CE

M2_1
CE_M7 R_TQ7 D CE C

I4 I3 O I2 I1 RLOC=X0Y3 R_TQ7

FDCE
Q Q7

Q7 TQ7 R

CLR

FMAP
RLOC=X0Y3 CE LI O CI Q6 XORCY S0 D1 AND2B1 CEB6 TQ6 D0 O

M2_1
CE_M6 R_TQ6 D CE C

I4 I3 O I2 I1 RLOC=X0Y3 R_TQ6

FDCE
Q Q6

Q6 TQ6 R

C6 LO Q5 S MUXCY_L 0 1 DI CI RLOC=X1Y2

INV

CLR

RLOC=X0Y3 CE LI O CI Q5 XORCY D1 S0 INV RLOC=X1Y2 AND2B1 CEB5 TQ5 D0 O

FMAP
I4 I3 O I2 I1 RLOC=X0Y2 R_TQ5 Q5 TQ5 Q5 R

M2_1
CE_M5 R_TQ5 D CE C

FDCE
Q

C5 LO Q4 S MUXCY_L 0 1 DI CI LI O CI Q4 XORCY C4 LO Q3 S MUXCY_L 0 1 DI CI RLOC=X1Y1 TQ4

CLR

RLOC=X0Y2 CE

FMAP
I4 I3 O I2 I1 RLOC=X0Y2 R_TQ4 Q4 TQ4 Q4 R

M2_1
D0 O D1 S0 INV AND2B1 CEB4 CE_M4 R_TQ4 D CE C

FDCE
Q

CLR

RLOC=X0Y2 CE LI O CI Q3 XORCY D1 S0 INV RLOC=X1Y1 AND2B1 CEB3 TQ3 D0 O

FMAP
I4 I3 O I2 I1 RLOC=X0Y1 R_TQ3 Q3 TQ3 Q3 R

M2_1
CE_M3 R_TQ3 D CE C

FDCE
Q

C3 LO Q2 S MUXCY_L 0 1 DI CI LI O CI Q2 XORCY C2 LO Q1 S MUXCY_L 0 1 DI CI LI O CI Q1 XORCY C1 LO Q0 S MUXCY_L 0 1 DI CI RLOC=X1Y0 INV TQ1 RLOC=X1Y0 TQ2

CLR

RLOC=X0Y1 CE

FMAP
I4 I3 O I2 I1 RLOC=X0Y1 R_TQ2 Q2 TQ2 Q2 R

M2_1
D0 O D1 S0 INV AND2B1 CEB2 CE_M2 R_TQ2 D CE C

FDCE
Q

CLR

RLOC=X0Y1 CE

FMAP
I4 I3 O I2 I1 RLOC=X0Y0 R_TQ1 Q1 TQ1 Q1 R

M2_1
D0 O D1 S0 AND2B1 CEB1 CE_M1 R_TQ1 D CE C

FDCE
Q

CLR

RLOC=X0Y0 CE LI O CI Q0 XORCY S0 D1 AND2B1 INV CEB0 TQ0 D0 O

FMAP
I4 I3 O I2 I1 RLOC=X0Y0 R_TQ0 Q0 TQ0 Q0 R

M2_1
CE_M0 R_TQ0 D CE C

FDCE
Q

GND VCC C0

CLR

RLOC=X0Y0 CE R C X9312

GND

CC8RE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

292

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Libraries Guide ISE 6.li

CC8RE, CC16RE

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cc8re is constant TERMINAL_COUNT : std_logic_vector(WIDTH-1 downto 0) := (others => '1'); begin process(C, R) begin if (C'event and C='1') then if (R='1') then Q <= (others => '0'); elsif (CE='1') then Q <= Q+1; end if; end if; end process; process(Q) begin if (Q = TERMINAL_COUNT) then TC<='1'; else TC<='0'; end if; end process; CEO<=TC and CE; end Behavioral;

Verilog Inference Code


always @(posedge C) begin if (R) Q <= 0; else if (CE) Q <= Q + 1; end always @(Q) begin if (Q == TERMINAL_COUNT) TC <= 1; else TC <= 0; end

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293

CC8RE, CC16RE

always @(TC or CE) begin CEO <= TC & CE; end

294

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Libraries Guide ISE 6.li

CD4CE

CD4CE
4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear
Architectures Supported
CD4CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CD4CE

Q0 Q1 Q2 Q3

CE C

CEO TC

CLR X4369

CD4CE is a 4-bit (stage), asynchronous clearable, cascadable binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when clock enable (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.

X2355

Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage.

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295

CD4CE

When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse to the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.

Inputs CLR 1 0 0 0
CEO = TCCE

Outputs C X X X Q3 0 Inc No Chg 1 Q2 0 Inc No Chg 0 Q1 0 Inc No Chg 0 Q0 0 Inc No Chg 1 TC 0 TC TC 1 CEO 0 CEO 0 1

CE X 1 0 1

TC = Q3!Q2!Q1Q0

FDCE
D0 INV D CE C CLR Q0 Q Q0

AX1 AND2B1 XOR2

FDCE
D1 D CE C CLR Q1 Q Q1

AX2 AND2 AO3B AND3 XOR2

FDCE
D2 D CE C CLR Q2 Q Q2

AO3A AND2 OR2

OX3 XOR2

FDCE
D3 D CE C CLR Q3 Q Q3

C CLR AND4B2 CE AND2 X7784

TC

CEO

CD4CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

296

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Libraries Guide ISE 6.li

CD4CE

VCC

CE
AND2

CLR C Q0 Q1 Q2 Q3

AND3B2

FDC
D OR3 AND4B3 C CLR Q

Q0

AND5B2

FDC Q0
AND4B2 D Q

Q2 CEO

AND2B1 OR4 AND4B2


AND4B2

CLR

Q2

AND5B2

FDC
D OR3
AND4B2

Q1

AND2B1 AND4B2

TC

CLR

Q1
AND2B1 AND5B1

FDC
D
OR3 AND5B3

Q3

CLR

Q3
AND2B1
X7629

CD4CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred.

VHDL Inference Code


architecture Behavioral of cd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C'event and C = '1') then if (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1;

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297

CD4CE

end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC_INT <= '1'; else TC_INT <= '0'; end if; end process; TC <= TC; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end

298

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Libraries Guide ISE 6.li

CD4CLE

CD4CLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous Clear
Architectures Supported
CD4CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D0 D1 D2 D3 L CE C

CD4CLE

Q0 Q1 Q2 Q3

CEO TC

CLR

X4370

CD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, binarycoded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition. The Q outputs increment when clock enable input (CE) is High during the Low- to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.
0 1 2 3 4

X2355

Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the

Libraries Guide ISE 6.li

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299

CD4CLE

clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 L X 1 0 0 0 CE X X 1 0 1 D3 D0 X D3 D0 X X X C X X X Q3 0 D3 Inc No Chg 1 Q2 0 D2 Inc No Chg 0 Outputs Q1 0 D1 Inc No Chg 0 Q0 0 D0 Inc No Chg 1 TC 0 TC TC TC 1 CEO 0 CEO CEO 0 1

TC = Q3!Q2!Q1Q0 CEO = TCCE


FTCLEX
D0 L D L Q T CE C CLR Q0

C CLR

Q0

FTCLEX
D1 T1 AND2B1 OR_CE_L OR2 D2 D L Q T CE C CLR Q1 Q1

FTCLEX
D L Q T CE C CLR Q2

Q2

FTCLEX
D3 T2 AND2 TQ03 AND2 AND2 TQ2 OR2 T3 D L Q T CE C CLR Q3 Q3 TC

AND4B2 CE AND2 CEO

X7785

CD4CLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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CD4CLE

Q0 Q1 Q2 Q3

INV INV AND5B4 INV AND6

FDC
AND4B3 OR4 AND3B2 D C Q
AND5B2

CEO

AND5B3

CLR D0
AND2 AND5B3 OR5

Q0
D C

FDC
Q
AND4B2

TC

CLR
Q2

AND3B2 AND5B3

D2
AND2

FDC
AND5B3 OR4 AND3B2

INV Q

CLR Q1

INV AND6

D1
AND2

INV INV INV INV


AND6 OR4 AND3B2

VCC

FDC
D Q

CE L

CLR Q3

GRD

D3
AND2

C CLR
X7628

CD4CLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred.

VHDL Inference Code


architecture Behavioral of cd4cle is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C'event and C = '1') then if (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then

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301

CD4CLE

Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC_INT <= '1'; else TC_INT <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @(TC or CE) begin CEO <= TC && CE; end

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CD4RE

CD4RE
4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset
Architectures Supported
CD4RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CD4RE

Q0 Q1 Q2 Q3

CE C

CEO TC

X4371

CD4RE is a 4-bit (stage), synchronous resettable, cascadable binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.

X2355

Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When

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303

CD4RE

cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.

Inputs R 1 0 0 0
CEO = TCCE

Outputs C X X Q3 0 Inc No Chg 1 Q2 0 Inc No Chg 0 Q1 0 Inc No Chg 0 Q0 0 Inc No Chg 1 TC 0 TC TC 1 CEO 0 CEO 0 1

CE X 1 0 1

TC = Q3!Q2!Q1Q0

FDRE
D0 INV D CE C R Q0 Q Q0

AX1 AND2B1

FDRE
D1 XOR2 D CE C R Q1 Q Q1

AX2 AND2 A03B

FDRE
D2 XOR2 D CE C R Q2 Q Q2

AND3

AO3A OR2 AND2

OX3

FDRE
D3 XOR2 D CE C R Q3 Q Q3

C R CE AND4B2 AND2

TC

CEO

X9315

CD4RE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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CD4RE

R Q0 Q1 Q2 Q3

INV

AND5B4

FD
D OR3 AND4B3 C Q

INV INV

AND6

CEO FD Q0
AND5B3

Q
AND5B2

AND3B2 OR4 C

Q2
AND5B3

TC
AND4B2

AND5B3

FD
D OR3 AND5B3 C Q INV

AND3B2

Q1
INV AND3B2 AND6

INV INV INV INV VCC


AND6 OR3

FD
D Q

Q3 CE
AND2
AND3B2
X7627

CD4RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred.

VHDL Inference Code


architecture Behavioral of cd4re is begin process (C) begin if (C'event and C = '1') then if (R = '1') then Q <= "0000"; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if;

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CD4RE

end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @(TC or CE) begin CEO <= TC && CE; end

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Libraries Guide ISE 6.li

CD4RLE

CD4RLE
4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset
Architectures Supported
CD4RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D0 D1 D2 D3 L CE C

CD4RLE

Q0 Q1 Q2 Q3

CEO TC

R X4372

CD4RLE is a 4-bit (stage), synchronous loadable, resettable, binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers from any of six possible illegal states and returns to a normal count sequence within two clock cycles for Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X as shown in the following state diagram. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the counter resets to zero or recovers within the first clock cycle.
0 1 2 3 4

X2355

Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When

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307

CD4RLE

cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.

Inputs R 1 0 0 0 0 L X 1 0 0 0 CE X X 1 0 1 D3 D0 X D3 D0 X X X C X X Q3 0 D3 Inc No Chg 1 Q2 0 D Inc No Chg 0

Outputs Q1 0 D Inc No Chg 0 Q0 0 D0 Inc No Chg 1 TC 0 TC TC TC 1 CEO 0 CEO CEO 0 1

TC = Q3!Q2!Q1Q0 CEO = TCCE

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CD4RLE

FTRSLE
D0 L D S L T Q CE C R Q0

C R

Q0

FTRSLE
D1 T1 AND2B1 D S L T Q CE C R Q1 Q1

FTRSLE
D2 D S L T Q CE C R Q2

Q2

FTRSLE
D3 T2 AND2 TQ03 AND2 AND2 TQ2 OR2 T3 D S L T Q CE C R Q3 Q3 TC

AND4B2 CE AND2 CEO

GND

X7787

CD4RLE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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309

CD4RLE

Q1 Q2 Q3
AND2

INV INV INV OR2 INV INV AND5B2 AND6

CEO

D AND4B2 Q

TC

FD
AND5B4 OR4 C D

Q0
AND4B3

D0
AND3B1

INV INV INV INV

AND6

INV INV INV INV AND6 OR4 C D

FD
Q

Q1
AND4B3

D1
AND3B1

INV INV

INV INV

AND7

INV INV INV INV AND6

FD
INV INV INV INV AND6 D OR5 C Q

Q2

AND4B3

D2
AND3B1

INV INV

INV

AND7

INV INV INV INV INV AND7 OR4 C

FD
D Q

Q3
AND4B3

CD4RLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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CD4RLE

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of cd4rle is begin process (C) begin if (C'event and C = '1') then if (R = '1') then Q <= "0000"; elsif (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000;

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311

CD4RLE

else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end

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CDD4CE

CDD4CE
4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear
Architectures Supported
CDD4CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CDD4CE

Q0 Q1 Q2 Q3

CE C

CEO TC

CLR
X9734

CDD4CE is a 4-bit (stage), asynchronous clearable, cascadable dual edge triggered Binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when clock enable (CE) is High during the Low-to-High and High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse to the PRLD global net.

Inputs CLR 1 0 0 0 CE X 1 1 0 C X X Q3 0 Inc Inc No Chg Q2 0 Inc Inc No Chg

Outputs Q1 0 Inc Inc No Chg Q0 0 Inc Inc No Chg TC 0 TC TC TC CEO 0 CEO CEO 0

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CDD4CE

Inputs CLR 0
CEO = TCCE

Outputs C X Q3 1 Q2 0 Q1 0 Q0 1 TC 1 CEO 1

CE 1

TC = Q3!Q2!Q1Q0

VCC

CE AND2 CLR C Q0 Q1 Q2 Q3

AND3B2

FDDC
D OR3 AND4B3 C CLR Q0 AND2B1 Q Q0

AND5B2

FDDC
AND4B2 D Q Q2 CEO

OR4 AND4B2 AND4B2

CLR Q2 AND5B2

FDDC
D OR3 AND4B2 C CLR Q1 AND2B1 AND5B1 Q Q1 AND2B1 AND4B2

TC

FDDC
D OR3 AND5B3 C CLR Q3 AND2B1
X9735

Q3

CDD4CE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of cdd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C'event) then if (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110";

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CDD4CE

elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end

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315

CDD4CE

316

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Libraries Guide ISE 6.li

CDD4CLE

CDD4CLE
4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Asynchronous Clear
Architectures Supported
CDD4CLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D0 D1 D2 D3 L CE C

CDD4CLE

Q0 Q1 Q2 Q3

CEO TC

CLR

X9736

CDD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, dual edge triggered Binary-coded-decimal (BCD) counter. The asynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High and High-to-Low clock (C) transitions. The Q outputs increment when clock enable input (CE) is High during the Low- to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the CLR, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Inputs CLR 1 0 0 0 L X 1 1 0 CE X X X 1 D3 D0 X D3 D0 D3 D0 X C X Q3 0 D3 D3 Inc Q2 0 D2 D2 Inc

Outputs Q1 0 D1 D1 Inc Q0 0 D0 D0 Inc TC 0 TC TC TC CEO 0 CEO CEO CEO

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CDD4CLE

Inputs CLR 0 0 0 L 0 0 0 CE 1 0 1 D3 D0 X X X C X X Q3 Inc No Chg 1 Q2 Inc No Chg 0

Outputs Q1 Inc No Chg 0 Q0 Inc No Chg 1 TC TC TC 1 CEO CEO 0 1

TC = Q3!Q2!Q1Q0 CEO = TCCE

Q0 Q1 Q2 Q3

INV INV AND5B4 INV AND6 CEO

FDDC
AND4B3 OR4 AND3B2 D0 AND2 AND5B3 OR5 D C CLR Q0 D C CLR Q2 Q AND5B2 AND5B3

FDDC
Q AND4B2

TC

AND3B2 AND5B3 D2 AND2

FDDC
AND5B3 OR4 AND3B2 D1 AND2 VCC CE L D Q

INV

CLR Q1

INV AND6

INV INV INV INV AND6 OR4 AND3B2 D

FDDC
Q

CLR Q3

GRD C CLR

D3 AND2

X9737

CDD4CLE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of cdd4cle is begin process (C, CLR) begin if (CLR = '1') then

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CDD4CLE

Q <= "0000"; elsif (C'event) then if (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin

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CDD4CLE

if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end

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CDD4RE

CDD4RE
4-Bit Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset
Architectures Supported
CDD4RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CDD4RE

Q0 Q1 Q2 Q3

CE C

CEO TC

X9738

CDD4RE is a 4-bit (stage), synchronous resettable, cascadable dual edge triggered binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High or High-to-Low clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R and clock inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 CE X X 1 1 0 C X Q3 0 0 Inc Inc No Chg Q2 0 0 Inc Inc No Chg Outputs Q1 0 0 Inc Inc No Chg Q0 0 0 Inc Inc No Chg TC 0 0 TC TC TC CEO 0 0 CEO CEO 0

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CDD4RE

Inputs R 0
CEO = TCCE

Outputs C X Q3 1 Q2 0 Q1 0 Q0 1 TC 1 CEO 1

CE 1

TC = Q3!Q2!Q1Q0

R Q0 Q1 Q2 Q3

INV

AND5B4

INV INV

FDD
D OR3 AND4B3 C Q0 AND3B2 Q

AND6

CEO

FDD
AND5B3 D Q AND5B2 OR4 C Q2 AND5B3 TC

AND5B3

AND4B2

FDD
D OR3 AND5B3 C Q1 INV AND3B2 Q INV

AND3B2

AND6

INV INV INV INV VCC AND6 OR3

FDD
D Q

C Q3

CE AND2 AND3B2
X9739

CDD4RE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of cdd4re is begin process (C) begin if (C'event) then if (R = '1') then Q <= "0000"; elsif (CE = '1') then if (Q = "1001") then Q <= "0000";

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CDD4RE

elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100; else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end

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CDD4RE

always @ (TC or CE) begin CEO <= TC && CE; end

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CDD4RLE

CDD4RLE
4-Bit Loadable Cascadable Dual Edge Triggered BCD Counter with Clock Enable and Synchronous Reset
Architectures Supported
CDD4RLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D0 D1 D2 D3 L CE C

CDD4RLE

Q0 Q1 Q2 Q3

CEO TC

R
X9740

CDD4RLE is a 4-bit (stage), synchronous loadable, resettable, dual edge triggered binary-coded-decimal (BCD) counter. The synchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High or High-to-Low clock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High and High-to-Low clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 are High and Q2 and Q1 are Low. The counter recovers to zero from any illegal state within the first clock cycle. Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the R, L, and C inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 L X X 1 1 0 CE X X X X 1 D3 D0 X X D3 D0 D3 D0 X C Q3 0 0 D3 D3 Inc Q2 0 0 D2 D2 Inc Outputs Q1 0 0 D1 D1 Inc Q0 0 0 D0 D0 Inc TC 0 0 TC TC TC CEO 0 0 CEO CEO CEO

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CDD4RLE

Inputs R 0 0 0 L 0 0 0 CE 1 0 1 D3 D0 X X X C X X Q3 Inc No Chg 1 Q2 Inc No Chg 0

Outputs Q1 Inc No Chg 0 Q0 Inc No Chg 1 TC TC TC 1 CEO CEO 0 1

TC = Q3!Q2!Q1Q0 CEO = TCCE

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CDD4RLE

C Q0 VCC Q1 Q2 CE AND2 CEO Q3

R L OR2

INV INV INV INV INV AND5B2 AND6

GND AND4B2 Q

TC

FDD
AND5B4 OR4 C Q0 AND4B3 D0 AND3B1 D

INV INV INV INV

AND6

INV INV INV INV AND6 OR4 C D

FDD
Q

Q1 AND4B3 D1 AND3B1

INV INV

INV INV

AND7

INV INV INV INV AND6

FDD
INV INV INV INV AND6 Q2 D OR5 C Q

AND4B3 D2 AND3B1

INV INV

INV

AND7

INV INV INV INV INV AND7 OR4 C Q3 AND4B3 D3 AND3B1


X9741

FDD
D Q

CDD4RLE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

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CDD4RLE

VHDL Inference Code


architecture Behavioral of cdd4rle is begin process (C) begin if (C'event) then if (R = '1') then Q <= "0000"; elsif (L = '1') then Q <= D; elsif (CE = '1') then if (Q = "1001") then Q <= "0000"; elsif (Q = "1011") then Q <= "0110"; elsif (Q = "1101") then Q <= "0100"; elsif (Q = "1111") then Q <= "0010"; else Q <= Q + 1; end if; end if; end if; end process; process (Q) begin if (Q = "1001") then TC <= '1'; else TC <= '0'; end if; end process; CEO <= TC and CE; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 0; else if (L) Q <= D; else if (CE) begin if (Q == 4'b1001) Q <= 4'b0000; else if (Q == 4'b1011) Q <= 4'b0110; else if (Q == 4'b1101) Q <= 4'b0100;

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CDD4RLE

else if (Q == 4'b1111) Q <= 4'b0010; else Q <= Q + 1; end end always @ (Q) begin if (Q == 4'b1001) TC <= 1; else TC <= 0; end always @ (TC or CE) begin CEO <= TC && CE; end

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CDD4RLE

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CJ4CE, CJ5CE, CJ8CE

CJ4CE, CJ5CE, CJ8CE


4-, 5-, 8-Bit Johnson Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CJ4CE, CJ5CE, CJ8CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CJ4CE

Q0 Q1 Q2 Q3

CE C

CLR

X4112

CJ4CE, CJ5CE, and CJ8CE are clearable Johnson/shift counters. The asynchronous clear (CLR) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero, independent of clock (C) transitions. The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High during the Low-to-High clock transition. Clock transitions are ignored when CE is Low. For CJ4CE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operation. For CJ5CE, the Q4 output is inverted and fed back to input Q0. For CJ8CE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. CJ4CE Truth Table
Inputs CLR 1 0 0 CE X 0 1 C X X Q0 0 No Chg !q3 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2

CJ5CE

Q0 Q1 Q2

CE C

Q3 Q4

CLR

X4114

CJ8CE
CE C

Q[7:0]

CLR

X4118

q = state of referenced output one setup time prior to active clock transition

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CJ4CE, CJ5CE, CJ8CE

CJ5CE Truth Table


Inputs CLR 1 0 0 CE X 0 1 C X X Q0 0 No Chg !q4 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2 Q4 0 No Chg q3

q = state of referenced output one setup time prior to active clock transition

CJ8CE Truth Table


Inputs CLR 1 0 0 CE X 0 1 C X X Q0 0 No Chg !q7 Outputs Q1 Q7 0 No Chg q0 q6

q = state of referenced output one setup time prior to active clock transition

Q[7:0] Q7

FDCE FDCE
Q7B INV D CE C CLR Q0 Q Q0 Q3 D CE C CLR Q4 Q Q4

FDCE FDCE
D CE C CLR Q1 Q Q1 D CE C CLR Q5 Q Q5

FDCE FDCE
D CE C CLR Q2 Q Q2 D CE C CLR Q6 Q Q6

FDCE FDCE
D CE C CLR Q3 CE C CLR X7789 Q Q3 D CE C CLR Q7 Q Q7

CJ8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element can be inferred but not instantiated.

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CJ4CE, CJ5CE, CJ8CE

VHDL Inference Code


architecture Behavioral of cj4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= (others => '0'); elsif (C'event and C = '1') then if (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else begin if (CE) begin Q[0] <= !Q[WIDTH-1]; Q[WIDTH-1:1] <= Q[WIDTH-2:0]; end end end

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CJ4CE, CJ5CE, CJ8CE

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CJ4RE, CJ5RE, CJ8RE

CJ4RE, CJ5RE, CJ8RE


4-, 5-, 8-Bit Johnson Counters with Clock Enable and Synchronous Reset
Architectures Supported
CJ4RE, CJ5RE, CJ8RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CJ4RE

Q0 Q1 Q2 Q3

CE C

X4113

CJ4RE, CJ5RE, and CJ8RE are resettable Johnson/shift counters. The synchronous reset (R) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero during the Low-to-High clock (C) transition. The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High during the Low-to-High clock transition. Clock transitions are ignored when CE is Low. For CJ4RE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operations. For CJ5RE, the Q4 output is inverted and fed back to input Q0. For CJ8RE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. CJ4RE Truth Table
Inputs R 1 0 0 CE X 0 1 C X Q0 0 No Chg q3 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2

CJ5RE

Q0 Q1 Q2

CE C

Q3 Q4

X4115

CJ8RE
CE C

Q[7:0]

X4119

q = state of referenced output one setup time prior to active clock transition

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CJ4RE, CJ5RE, CJ8RE

CJ5RE Truth Table


Inputs R 1 0 0 CE X 0 1 C X Q0 0 No Chg q4 Q1 0 No Chg q0 Outputs Q2 0 No Chg q1 Q3 0 No Chg q2 Q4 0 No Chg q3

q = state of referenced output one setup time prior to active clock transition

CJ8RE Truth Table


Inputs R 1 0 0 CE X 0 1 C X Q0 0 No Chg q7 Outputs Q1 Q7 0 No Chg q0 q6

q = state of referenced output one setup time prior to active clock transition

Q[7:0] Q7

FDRE FDRE
Q7B INV D CE C R Q0 Q Q0 Q3 D CE C R Q4 Q Q4

FDRE FDRE
D CE C R Q1 Q Q1 D CE C R Q5 Q Q5

FDRE FDRE
D CE C R Q2 Q Q2 D CE C R Q6 Q Q6

FDRE FDRE
D CE C R Q3 CE C R X7790 Q Q3 D CE C R Q7 Q Q7

CJ8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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CJ4RE, CJ5RE, CJ8RE

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of cj4re is begin process (C) begin if (C'event and C = '1') then if (R = '1') then Q <= (others => '0'); elsif (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else begin if (CE) begin Q[0] <= !Q[WIDTH-1]; Q[WIDTH-1:1] <= Q[WIDTH-2:0]; end end end

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CJD4CE, CJD5CE, CJD8CE

CJD4CE, CJD5CE, CJD8CE


4-, 5-, 8-Bit Dual Edge Triggered Johnson Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CJD4CE, CJD5CE, CJD8CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CJD4CE
Q0 Q1 CE C Q2 Q3

CLR
X9742

CJD4CE, CJD5CE, and CJD8CE are dual edge triggered clearable Johnson/shift counters. The asynchronous clear (CLR) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero, independent of clock (C) transitions. The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. Clock transitions are ignored when CE is Low. For CJD4CE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operations. For CJD5CE, the Q4 output is inverted and fed back to input Q0. For CJD8CE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. CJD4CE Truth Table

CJD5CE

Q0 Q1 Q2

CE C

Q3 Q4

CLR

X9743

CJD8CE
CE C

Q[7:0]

Inputs CLR
X9744

Outputs C X X Q0 0 No Chg !q3 !q3 Q1 0 No Chg q0 q0 Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2

CE X 0 1 1

CLR

1 0 0 0

q = state of referenced output one setup time prior to active clock transition

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CJD4CE, CJD5CE, CJD8CE

CJD5CE Truth Table


Inputs CLR 1 0 0 0 CE X 0 1 1 C X X Q0 0 No Chg !q4 !q4 Q1 0 No Chg q0 q0 Outputs Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2 Q4 0 No Chg q3 q3

q = state of referenced output one setup time prior to active clock transition

CJD8CE Truth Table


Inputs CLR 1 0 0 0 CE X 0 1 1 C X X Q0 0 No Chg !q7 !q7 Outputs Q1 Q7 0 No Chg q0 q6 q0 q6

q = state of referenced output one setup time prior to active clock transition

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of cjd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= (others => '0'); elsif (C'event) then if (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;

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CJD4CE, CJD5CE, CJD8CE

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q_INT <= 0; else begin if (CE) begin Q_INT[0] <= !Q_INT[WIDTH-1]; Q_INT[WIDTH-1:1] <= Q_INT[WIDTH-2:0]; end end end always @ (Q_INT) begin Q <= Q_INT; end

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CJD4CE, CJD5CE, CJD8CE

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CJD4RE, CJD5RE, CJD8RE

CJD4RE, CJD5RE, CJD8RE


4-, 5-, 8-Bit Dual Edge Triggered Johnson Counters with Clock Enable and Synchronous Reset
Architectures Supported
CJD4RE, CJD5RE, CJD8RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CJD4RE

Q0 Q1 Q2 Q3

CE C

X9745

CJD4RE, CJD5RE, and CJD8RE are resettable dual edge triggered Johnson/shift counters. The synchronous reset (R) input, when High, overrides all other inputs and causes the data (Q) outputs to go to logic level zero during the Low-to-High and High-to-Low clock (C) transition. The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High during the Low-to-High and High-to-Low clock transition. Clock transitions are ignored when CE is Low. For CJD4RE, the Q3 output is inverted and fed back to input Q0 to provide continuous counting operations. For CJD5RE, the Q4 output is inverted and fed back to input Q0. For CJD8RE, the Q7 output is inverted and fed back to input Q0. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. CJD4RE Truth Table

CJD5RE

Q0 Q1 Q2

CE C

Q3 Q4

X9746

CJD8RE
CE C

Q[7:0]

Inputs R 1 CE X 0 1 1 C X Q0 0 No Chg q3 q3 Q1 0

Outputs Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2

X9747

0 0 0

No Chg q0 q0

q = state of referenced output one setup time prior to active clock transition

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CJD4RE, CJD5RE, CJD8RE

CJD5RE Truth Table


Inputs R 1 0 0 0 CE X 0 1 1 C X Q0 0 No Chg q4 q4 Q1 0 No Chg q0 q0 Outputs Q2 0 No Chg q1 q1 Q3 0 No Chg q2 q2 Q4 0 No Chg q3 q3

q = state of referenced output one setup time prior to active clock transition

CJD8RE Truth Table


Inputs R 1 1 0 0 0 CE X X 0 1 1 C X Q0 0 0 No Chg q7 q7 Outputs Q1 Q7 0 0 No Chg q0 q6 q0 q6

q = state of referenced output one setup time prior to active clock transition

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of cjd4re is begin process (C) begin if (C'event) then if (R = '1') then Q <= (others => '0'); elsif (CE = '1') then Q(0) <= not Q(WIDTH-1); Q(WIDTH-1 downto 1) <= Q(WIDTH-2 downto 0); end if; end if; end process; end Behavioral;

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CJD4RE, CJD5RE, CJD8RE

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 0; else begin if (CE) begin Q[0] <= !Q[WIDTH-1]; Q[WIDTH-1:1] <= Q[WIDTH-2:0]; end end end

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Libraries Guide ISE 6.li

CLK_DIV2,4,6,8,10,12,14,16

CLK_DIV2,4,6,8,10,12,14,16
Global Clock Divider
Architectures Supported
CLK_DIV2 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLK_DIV4, CLK_DIV6, CLK_DIV8, CLK_DIV10, CLK_DIV12, CLK_DIV14, CLK_DIV16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLKIN

CLKDV

The CLK_DIV2,4,6,8,10,12,14,16 Global Clock Dividers divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 orXC2C64. The CLKIN input can only be connected to the device gclk<2> pin. The duty cycle of the CLKDV output is 50-50. The CLKDV output is reset low by power-on reset circuitry.

Usage
This design element is supported for schematics and instantiation but not for inference.

VHDL Instantiation Template


-- Component Declaration for CLK_DIVn should be placed -- after architecture statement but before begin keyword component CLK_DIVn port (CLKDV : out STD_ULOGIC; CLKIN : in STD_ULOGIC); end component; -- Component Instantiation for CLK_DIVn should be placed -- in architecture after the begin keyword

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CLK_DIV2,4,6,8,10,12,14,16

CLK_DIVn_INSTANCE_NAME : CLK_DIVn port map (CLKDV => user_CLKDV, CLKIN => user_CLKIN);

Verilog Instantiation Template


CLK_DIVn CLK_DIVn_instance_name (.CLKDV (user_CLKDV), .CLKIN (user_CLKIN));

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CLK_DIV2,4,6,8,10,12,14,16R

CLK_DIV2,4,6,8,10,12,14,16R
Global Clock Divider with Synchronous Reset
Architectures Supported
CLK_DIV2R Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLK_DIV4R, CLK_DIV6R, CLK_DIV8R, CLK_DIV10R, CLK_DIV12R, CLK_DIV14R, CLK_DIV16R Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLKIN CLKDV CDRST

The CLK_DIV2,4,6,8,10,12,14,16R Global Clock Dividers with Synchronous Reset divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN and CDRST inputs can only be connected to the device gclk<2> and CDRST pins. The duty cycle of the CLKDV output is 50-50. The CDRST input is an active High synchronous reset. If CDRST is input High when the CLKDV output is High, the CLKDV output remains High to complete the last clock pulse, and then goes Low. The CLKDV output is reset low by power-on reset circuitry.

Usage
For HDL, these design elements are supported for instantiation but not inference.

VHDL Instantiation Template


-- Component Declaration for CLK_DIVnR should be placed -- after architecture statement but before begin keyword component CLK_DIVnR port (CLDV : out STD_ULOGIC; CDRST : in STD_ULOGIC;

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CLK_DIV2,4,6,8,10,12,14,16R

CLKIN : in STD_ULOGIC); end component; -- Component Instantiation for CLK_DIVnR should be placed -- in architecture after the begin keyword CLK_DIVnR_INSTANCE_NAME : port map (CLKDV => CDRST => CLKIN => CLK_DIVnR user_CLKDV, user_CDRST, user_CLKIN);

Verilog Instantiation Template


CLK_DIVnR CLK_DIVnR_instance_name (.CLKDV (user_CLKDV), .CDRST (user_CDRST), .CLKIN (user_CLKIN));

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CLK_DIV2,4,6,8,10,12,14,16RSD

CLK_DIV2,4,6,8,10,12,14,16RSD
Global Clock Divider with Synchronous Reset and Start Delay
Architectures Supported
CLK_DIV2RSD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLK_DIV4RSD, CLK_DIV6RSD, CLK_DIV8RSD, CLK_DIV10RSD, CLK_DIV12RSD, CLK_DIV14RSD, CLK_DIV16RSD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLKIN CLKDV CDRST

The CLK_DIV2,4,6,8,10,12,14,16 Global Clock Dividers with Synchronous Reset and Start Delay divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN and CDRST inputs can only be connected to the device gclk<2> and CDRST pins. The duty cycle of the CLKDV output is 50-50. The CDRST input is an active High synchronous reset. If CDRST is input High when the CLKDV output is High, the CLKDV output remains High to complete the last clock pulse, and then goes Low. The start delay function delays the start of the CLKDV output by (n + 1) clocks, where n is the divisor for the clock divider. The CLKDV output is reset low by power-on reset circuitry.

Usage
For HDL, these design elements are supported for instantiation but not inference.

VHDL Instantiation Template


-- Component Declaration for CLK_DIVnRSD should be placed -- after architecture statement but before begin keyword

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CLK_DIV2,4,6,8,10,12,14,16RSD

component CLK_DIVnRSD port (CLDV : out STD_ULOGIC; CDRST : in STD_ULOGIC; CLKIN : in STD_ULOGIC); end component; -- Component Instantiation for CLK_DIVnRSD should be placed -- in architecture after the begin keyword CLK_DIVnRSD_INSTANCE_NAME port map (CLKDV CDRST CLKIN : CLK_DIVnRSD => user_CLKDV, => user_CDRST, => user_CLKIN);

Verilog Instantiation Template


CLK_DIVnRSD CLK_DIVnRSD_instance_name (.CLKDV (user_CLKDV), .CDRST (user_CDRST), .CLKIN (user_CLKIN));

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CLK_DIV2,4,6,8,10,12,14,16SD

CLK_DIV2,4,6,8,10,12,14,16SD
Global Clock Divider with Start Delay
Architectures Supported
CLK_DIV2SD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLK_DIV4SD, CLK_DIV6SD, CLK_DIV8SD, CLK_DIV10SD, CLK_DIV12SD, CLK_DIV14SD, CLK_DIV16SD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No Primitive

CLKIN

CLKDV

The CLK_DIV2,4,6,8,10,12,14,16SD Global Clock Dividers with Start Delay divide a user-provided external clock signal gclk<2> by 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Only one clock divider may be used per design. The global clock divider is available on the XC2C128, XC2C256, XC2C384, and XC2C512 CoolRunner-II devices, but not the XC2C32 or XC2C64. The CLKIN input can only be connected to the device gclk<2> pin. The duty cycle of the CLKDV output is 50-50. The start delay function delays the CLKDV output (n + 1) clocks, where n is the divisor for the clock divider. The CLKDV output is reset low by power-on reset circuitry.

Usage
This design element is supported for schematics and instantiation but not for inference.

VHDL Instantiation Template


-- Component Declaration for CLK_DIVnSD should be placed -- after architecture statement but before begin keyword component CLK_DIVnSD port (CLKDV : out STD_ULOGIC; CLKIN : in STD_ULOGIC); end component;

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CLK_DIV2,4,6,8,10,12,14,16SD

-- Component Instantiation for CLK_DIVnSD should be placed -- in architecture after the begin keyword CLK_DIVnSD_INSTANCE_NAME : CLK_DIVnSD port map (CLKDV => user_CLKDV, CLKIN => user_CLKIN);

Verilog Instantiation Template


CLK_DIVnSD CLK_DIVnSD_instance_name (.CLKDV (user_CLKDV), .CLKIN (user_CLKIN));

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CLKDLL

CLKDLL
Clock Delay Locked Loop
Architectures Supported
CLKDLL Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II * Use CLKDLLE for Spartan-IIE and Virtex-E. Primitive* No Primitive* No No No No

CLKDLL
CLKIN CLKFB CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV RST LOCKED

CLKDLL is a clock delay locked loop used to minimize clock skew. CLKDLL synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specific range of each other (see The Programmable Logic Data Book for the most current value). The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (see The Programmable Logic Data Book for the most current values). The CLKIN pin must be driven by an IBUFG or a BUFG. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the CLKDLL must be sourced from either the CLK0 or CLK2X outputs of the same CLKDLL. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X output can be used but not both. The CLK0 or CLK2X must be connected to the input of OBUF, an output buffer. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X and CLKDV outputs is always 50-50. The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for just 2ns.

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CLKDLL

CLKDLL Outputs
Output CLK0 CLK180 CLK270 CLK2X CLK90 CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0 Clock at 1x CLKIN frequency, shifted 270o with regards to CLK0 Clock at 2x CLKIN frequency, in phase with CLK0 Clock at 1x CLKIN frequency, shifted 90o with regards to CLK0 Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. CLKDLL locked Description

Note: See the "PERIOD Specifications on CLKDLLs and DCM" section of the "Xilinx Constraints P" chapter in the Constraints Guide for additional information on using the TNM,
TNM_NET, and PERIOD attributes with CLKDLL components.

Usage
This component is generally instantiated in the code as it can not be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool's documentation. Generally, global buffers (IBUFG, BUFG) are instantiated with the CLKDLL component to construct the proper clocking circuit. See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the Xilinx Databook for more information on using the CLKDLL component.

VHDL Instantiation Template


-- Component Declaration for CLKDLL should be placed -- after architecture statement but before begin keyword

component CLKDLL -- synthesis translate_off generic (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0) DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLK270 : out STD_ULOGIC; CLK2X : out STD_ULOGIC; CLK90 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; LOCKED : out STD_ULOGIC;

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CLKDLL

CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; RST : in STD_ULOGIC); end component;

-- Component Attribute specification for CLKDLL -- should be placed after architecture declaration but -- before the begin keyword

attribute CLKDV_DIVIDE : real; attribute DUTY_CYCLE_CORRECTION : boolean; attribute STARTUP_WAIT : boolean;

attribute CLKDV_DIVIDE of CLKDLL_instance_name: label is 2.0; -- 1.5,2,2.5,3,4, 5, 8, 16 are valid for CLKDV_DIVIDE attribute DUTY_CYCLE_CORRECTION of CLKDLL_instance_name: label is "TRUE"; -- TRUE, FALSE are valid for DUTY_CYCLE_CORRECTION attribute STARTUP_WAIT of CLKDLL_instance_name: label is "FALSE"; -(TRUE,FALSE)

-- Component Instantiation for CLKDLL should be placed -- in architecture after the begin keyword

CLKDLL_INSTANCE_NAME : CLKDLL -- synthesis translate_off generic map (CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) STARTUP_WAIT => boolean_value); -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLK270 => user_CLK270, CLK2X => user_CLK2X, CLK90 => user_CLK90, CLKDV => user_CLKDV,

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CLKDLL

LOCKED => user_LOCKED, CLKFB => user_CLKFB, CLKIN0 => user_CLKIN, RST => user_RST);

Verilog Instantiation Template


CLKDLL CLKDLL_instance_name (.CLK0 (user_CLK0), .CLK180 (user_CLK180), .CLK270 (user_CLK270), .CLK2X (user_CLK2X), .CLK90 (user_CLK90), .CLKDV (user_CLKDV), .LOCKED (user_LOCKED), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .RST (user_RST));

defparam CLKDLL_instance_name.CLKDV_DIVIDE = integer_value; //(1.5,2,2.5,3,4,5,8,16) defparam CLKDLL_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;// (TRUE, FALSE) defparam CLKDLL_instance_name.STARTUP_WAIT = boolean_value; // (TRUE, FALSE) Note: Additional syntax may be necessary in order to pass the CLKDLL attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints


STARTUP_WAIT, DUTY_CYCLE_CORRECTION, CLKDV_DIVIDE and LOC.

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CLKDLLE

CLKDLLE
Virtex-E Clock Delay Locked Loop
Architectures Supported
CLKDLLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive* No Primitive* No No No No

* Supported for Spartan-IIE and Virtex-E devices only.

CLKDLLE CLK0 CLKIN CLKFB CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV RST LOCKED

CLKDLLE is a clock delay locked loop used to minimize clock skew for Virtex-E devices. CLKDLLE synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specific range of each other (see The Programmable Logic Data Book for the most current value). The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (see The Programmable Logic Data Book for the most current values). The CLKIN pin must be driven by an IBUFG or a BUFG. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG input can only be connected to the CLK0 or CLK2X output of CLKDLLE. The BUFG connected to the CLKFB input of the CLKDLLE must be sourced from either the CLK0 or CLK2X outputs of the same CLKDLLE. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X output can be used but not both. The CLK0 or CLK2X must be connected to the input of OBUF, an output buffer. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X, CLK2X180, and CLKDV outputs is always 50-50. The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. The master reset input (RST) resets CLKDLLE to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for just 2ns.

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CLKDLLE

CLKDLLE Outputs
Output CLK0 CLK180 CLK270 CLK2X CLK2X180 CLK90 CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLK0 frequency, shifted 180o with regards to CLK0 Clock at 1x CLK0 frequency, shifted 270o with regards to CLK0 Clock at 2x CLK0 frequency, in phase with CLK0 Clock at 1x CLK2X frequency shifted 180o with regards to CLK2X Clock at 1x CLK0 frequency, shifted 90o with regards to CLK0 Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. CLKDLLE locked. CLKIN and CLKFB synchronized. Description

Usage
This component is generally instantiated in the code as it cannot be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool documentation. Generally, global buffers (IBUFG, BUFG) are instantiated with the CLKDLLE component to construct the proper clocking circuit. See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the Xilinx Databook for more information on using the CLKDLLE component.

VHDL Instantiation Template


-- Component Declaration for CLKDLLE should be placed -- after architecture statement but before begin keyword component CLKDLLE -- synthesis translate_off generic (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0) DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) STARTUP_WAIT :boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLK270 : out STD_ULOGIC; CLK2X : out STD_ULOGIC; CLK2X180: out STD_ULOGIC; CLK90 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; LOCKED : out STD_ULOGIC; CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; RST : in STD_ULOGIC); end component; -- Component Attribute specification for CLKDLLE -- should be placed after architecture declaration but -- before the begin keyword attribute CLKDV_DIVIDE : real;

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CLKDLLE

attribute DUTY_CYCLE_CORRECTION : boolean; attribute STARTUP_WAIT : boolean; attribute CLKDV_DIVIDE of CLKDLLE_instance_name: label is 2.0; -- (1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.5, 8.0, 9.0, 10.0, 11.0, -- 12.0, 13.0, 14.0, 15.0, 16.0) are valid for CLKDV_DIVIDE attribute DUTY_CYCLE_CORRECTION of CLKDLLE_instance_name: label is TRUE; -- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION attribute STARTUP_WAIT of CLKDLLE_instance_name: label is FALSE; -- (TRUE,FALSE)

-- Component Instantiation for CLKDLLE should be placed -- in architecture after the begin keyword CLKDLLE_INSTANCE_NAME : CLKDLLE -- synthesis translate_off generic map (CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) STARTUP_WAIT => boolean_value); -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLK270 => user_CLK270, CLK2X => user_CLK2X, CLK2X180 => user_CLK2X, CLK90 => user_CLK90, CLKDV => user_CLKDV, LOCKED => user_LOCKED, CLKFB => user_CLKFB, CLKIN0 => user_CLKIN, RST => user_RST);

Verilog Instantiation Template


CLKDLLE CLKDLLE_instance_name (.CLK0 (user_CLK0), .CLK180 (user_CLK180), .CLK270 (user_CLK270), .CLK2X (user_CLK2X), .CLK2X180 (user_CLK2X180), .CLK90 (user_CLK90), .CLKDV (user_CLKDV), .LOCKED (user_LOCKED), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .RST (user_RST)); defparam CLKDLLE_instance_name.CLKDV_DIVIDE = integer_value; // 1.5,2,2.5,3,4,5,8,16 are valid for CLKDV_DIVIDE defparam CLKDLLE_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;// (TRUE,FALSE) defparam CLKDLLE_instance_name.STARTUP_WAIT = boolean_value; // (TRUE, FALSE)

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CLKDLLE

Note: Additional syntax may be necessary in order to pass the CLKDLLE attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints


STARTUP_WAIT, DUTY_CYCLE_CORRECTION, CLKDV_DIVIDE, and LOC

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CLKDLLHF

CLKDLLHF
High Frequency Clock Delay Locked Loop
Architectures Supported
CLKDLLHF Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive No Primitive* No No No No

*Use CLKDLLHF for the Virtex-E DLL in HF mode. In LF mode, both the separate CLKDLLE and CLKDLL primitive can be used.

CLKDLLHF
CLKIN CLKFB CLK180 CLK0

CLKDLLHF is a high frequency clock delay locked loop used to minimize clock skew. CLKDLLHF synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specific range of each other (see The Programmable Logic Data Book for the most current value). The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (see The Programmable Logic Data Book for the most current values). The CLKIN pin must be driven by an IBUFG or a BUFG. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG input can only be connected to the CLK0 output of CLKDLLHF. The BUFG connected to the CLKFB input of the CLKDLLHF must be sourced from the CLK0 output of the same CLKDLLHF. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Only the CLK0 output can be used. CLK0 must be connected to the input of OBUF, an output buffer. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted output (CLK180) is the same as that of the CLK0 output. The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. The master reset input (RST) resets CLKDLLHF to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for just 2ns.

CLKDV RST LOCKED

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CLKDLLHF

CLKDLLHF Outputs
Output CLK0 CLK180 CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0 Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. CLKDLLHF locked Description

Note: See the "PERIOD Specifications on CLKDLLs and DCM" section of the "Xilinx Constraints P" chapter in the Constraints Guide for additional information on using the TNM,
TNM_NET, and PERIOD attributes with CLKDLLHF components.

Usage
This component is generally instantiated in the code as it cannot be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool documentation. Generally, global buffers (IBUFG, BUFG) are instantiated with the CLKDLLHF component to construct the proper clocking circuit. See the XAPP 132 application note, "Using the Virtex Delay-Locked Loop" and the Xilinx Databook for more information on using the CLKDLLHF component.

VHDL Instantiation Template


-- Component Declaration for CLKDLLHF should be placed -- after architecture statement but before begin keyword

component CLKDLLHF -- synthesis translate_off generic (CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0) DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; LOCKED : out STD_ULOGIC; CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; RST : in STD_ULOGIC); end component;

-- Component Attribute specification for CLKDLLHF

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CLKDLLHF

-- should be placed after architecture declaration but -- before the begin keyword

attribute CLKDV_DIVIDE : real; attribute DUTY_CYCLE_CORRECTION : boolean; attribute STARTUP_WAIT : boolean;

attribute CLKDV_DIVIDE of CLKDLLHF_instance_name: label is 2.0; -- (1.5,2,2.5,3,4, 5, 8, 16) are valid for CLKDV_DIVIDE attribute DUTY_CYCLE_CORRECTION of CLKDLLHF_instance_name: label is TRUE; -- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION attribute STARTUP_WAIT of CLKDLLHF_instance_name: label is FALSE; -(TRUE,FALSE)

-- Component Instantiation for CLKDLLHF should be placed -- in architecture after the begin keyword

CLKDLLHF_INSTANCE_NAME : CLKDLLHF -- synthesis translate_off generic map(CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) STARTUP_WAIT => boolean_value); -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLKDV => user_CLKDV, LOCKED => user_LOCKED, CLKFB => user_CLKFB, CLKIN => user_CLKIN, RST => user_RST); Verilog Instantiation Template CLKDLLHF CLKDLLHF_instance_name (.CLK0 (user_CLK0),

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365

CLKDLLHF

.CLK180 (user_CLK180), .CLKDV (user_CLKDV), .LOCKED (user_LOCKED), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .RST (user_RST));

defparam CLKDLLHF_instance_name.CLKDV_DIVIDE = integer_value; // 1.5,2,2.5,3,4,5,8,16 are valid for CLKDV_DIVIDE defparam CLKDLLHF_instance_name.DUTY_CYCLE_CORRECTION = boolean_value;// (TRUE,FALSE) defparam CLKDLLHF_instance_name.STARTUP_WAIT = boolean_value; // (TRUE, FALSE) Note: Additional syntax may be necessary in order to pass the CLKDLLHF attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints


STARTUP_WAIT DUTY_CYCLE_CORRECTION CLKDV_DIVIDE LOC

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Libraries Guide ISE 6.li

COMP2, 4, 8, 16

COMP2, 4, 8, 16
2-, 4-, 8-, 16-Bit Identity Comparators
Architectures Supported
COMP2, COMP4, COMP8, COMP16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

A0 A1 B0 B1

COMP2
EQ

X4122

COMP2, COMP4, COMP8, and COMP16 are, respectively, 2-, 4-, 8-, and 16-bit identity comparators. The equal output (EQ) of the COMP2 2-bit, identity comparator is High when the two words A1 A0 and B1 B0 are equal. EQ is high for COMP4 when A3 A0 and B3 B0 are equal; for COMP8, when A7 A0 and B7 B0 are equal; and for COMP16, when A15 A0 and B15 B0 are equal. Equality is determined by a bit comparison of the two words. When any two of the corresponding bits from each word are not the same, the EQ output is Low.

A0 A1 A2 A3 B0 B1 B2 B3

COMP4

EQ

X4126

A[7:0]

COMP8
EQ

B[7:0]

X4131

A[15:0]

COMP16
EQ

B[15:0]

X4133

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367

COMP2, 4, 8, 16

A0 B0 XNOR2 A1 B1 XNOR2 A2 B2 XNOR2 A3 B3 XNOR2 A4 B4 XNOR2 A5 B5 XNOR2 A6 B6 XNOR2 A7 B7 A[7:0] B[7:0] XNOR2

AB0

AB1 AB03 AB2 AND4

AB3 EQ AB4 AND2

AB5 AB47 AB6 AND4

AB7

X7791

COMP8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture behavioral of comp2 is begin process (A, B) begin If (A=B) then EQ <= '1'; else EQ <= '0'; end if; end process; end behavioral;

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COMP2, 4, 8, 16

Verilog Inference Code


always @ begin if (A EQ <= else EQ <= end (A or B) == B) 1; 0;

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COMP2, 4, 8, 16

370

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Libraries Guide ISE 6.li

COMPM2, 4, 8, 16

COMPM2, 4, 8, 16
2-, 4-, 8-, 16-Bit Magnitude Comparators
Architectures Supported
COMPM2, COMPM4, COMPM8, COMPM16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro Macro

A0 A1 B0 B1

COMPM2
GT LT

COMPM2, COMPM4, COMPM8, and COMPM16 are, respectively, 2-, 4-, 8-, and 16bit magnitude comparators that compare two positive binary-weighted words. COMPM2 compares A1 A0 and B1 B0, where A1 and B1 are the most significant bits. COMPM4 compares A3 A0 and B3 B0, where A3 and B3 are the most significant bits. COMPM8 compares A7 A0 and B7 B0, where A7 and B7 are the most significant bits. COMPM16 compares A15 A0 and B15 B0, where A15 and B15 are the most significant bits. The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When the two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparing both outputs with a NOR gate. COMPM2 Truth Table
Inputs Outputs A0 0 1 0 1 0 1 0 1 X X B0 0 0 1 1 0 0 1 1 X X GT 0 1 0 0 0 1 0 0 1 0 LT 0 0 1 0 0 0 1 0 0 1

X4123

A0 A1 A2 A3 B0 B1 B2 B3

COMPM4

GT LT

X4127

A1 0

B1 0 0 0 0 1 1 1 1 0 1

A[7:0]

COMPM8
GT

0 0 0 1 1 1 1
GT LT

B[7:0]

X4132

A[15:0]

COMPM16

1 0

B[15:0]

LT

X4134

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COMPM2, 4, 8, 16

COMPM4 Truth Table


Inputs A3, B3 A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2, B2 X X A2>B2 A2<B2 A2=B2 A2=B2 A2=A2 A2=B2 A2=B2 A1, B1 X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A0, B0 X X X X X X A0>B0 A0<B0 A0=B0 GT 1 0 1 0 1 0 1 0 0 Outputs LT 0 1 0 1 0 1 0 1 0

COMPM8 Truth Table (also representative of COMPM16)


Inputs A7, B7 A7>B7 A7<B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A6, B6 X X A6>B6 A6<B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A5, B5 X X X X A5>B5 A5<B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A4, B4 X X X X X X A4>B4 A4<B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A3, B3 X X X X X X X X A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A3=B3 A2, B2 X X X X X X X X X X A2>B2 A2<B2 A2=B2 A2=B2 A2=B2 A2=B2 A2=B2 A1, B1 X X X X X X X X X X X X A1>B1 A1<B1 A1=B1 A1=B1 A1=B1 A0, B0 X X X X X X X X X X X X X X A0>B0 A0<B0 A0=B0 Outputs GT 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 LT 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

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Libraries Guide ISE 6.li

COMPM2, 4, 8, 16

EQ_1 XNOR2 A0

LE0_1

LT0_1 OR2 AND4 GTA GT0_1 AND4 OR2 LTA

AND3B1 GE0_1

B0 AND3B1 A1 B1 AND2B1 LT_1 AND2B1 EQ_3 XNOR2 A2 GE2_3 B2 AND3B1 A3 A3 GT_3 AND2B1 LT_3 AND2B1 EQ_5 XNOR2 A4 GE4_5 B4 AND3B1 A5 B5 GT_5 AND2B1 LT_5 AND2B1 EQ_7 XNOR2 A6 GE6_7 B6 AND3B1 A[7:0] B[7:0] A7 B7 GT_7 AND2B1 LT_7 AND2B1 OR2 NOR2 LE6_7 OR2 GT4_5 NOR2 LE4_5 LT4_5 OR2 EQ4_5 OR2 GT2_3 NOR2 LE2_3 LT2_3 GT_1

LTB AND3B1 OR2 EQ2_3 AND3 OR4 GTB AND3

LT

LTC AND2

AND3B1

GTC AND2 OR4

GT

LTD OR2 EQ6_7

AND3B1

GTD

X7793

COMPM8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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COMPM2, 4, 8, 16

B0 A0
AND2B1

B1 A1
OR2B1

AND2 OR2

AND2 AND2B1

B2 A2
OR2B1 AND2 AND2B1 OR2

B3 A3
OR2B1 OR2

AND2 AND2B1

B4 A4
OR2B1 OR2

AND2B1

AND2

B5 A5
OR2B1 OR2

AND2 AND2B1

B6 A6
OR2B1 OR2

AND2B1

AND2 LT

B7 A7
OR2B1 OR2

AND2B1

A0 B0
AND2B1

A1 B1
OR2B1

AND2 OR2

AND2 AND2B1

A2 B2
OR2B1 AND2 AND2B1 OR2

A3 B3
OR2B1 OR2

AND2 AND2B1

A4 B4
OR2B1 OR2

AND2B1

AND2

A5 B5
OR2B1 OR2

AND2 AND2B1

A6 B6
OR2B1 OR2

AND2 AND2B1

A7 B7 A[7:0]
OR2B1 OR2

GT

B[7:0]

AND2B1 X7632

COMPM8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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COMPM2, 4, 8, 16

Usage
For HDL, these design elements are supported for inference rather than instantiation.

VHDL Inference Code


architecture Behavioral of compm2 is begin process (A,B) begin if (A>B) then GT <= '1'; LT <= '0'; elsif (A<B) then GT <= '0'; LT <= '1'; else GT <= '0'; LT <= '0'; end if; end process; end Behavioral;

Verilog Inference Code


always @ (A or B)
begin if (A > B) begin GT <= 1; LT <= 0; end else if (A < B) begin GT <= 0; LT <= 1; end else begin GT <= 0; LT <= 0; end end

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375

COMPM2, 4, 8, 16

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COMPMC8, 16

COMPMC8, 16
8-, 16-Bit Magnitude Comparators
Architectures Supported
COMPMC, COMPMC8, COMPMC16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

A[7:0]

COMPMC8
GT LT

B[7:0]

COMPMC8 is an 8-bit, magnitude comparator that compares two positive binaryweighted words A7 A0 and B7 B0, where A7 and B7 are the most significant bits. COMPMC16 is a 16-bit, magnitude comparator that compares two positive binaryweighted words A15 A0 and B15 B0, where A15 and B15 are the most significant bits. These comparators are implemented using carry logic with relative location constraints to ensure efficient logic placement. The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When the two words are equal, both GT and LT are Low. Equality can be flagged with this macro by connecting both outputs to a NOR gate. COMPMC8 Truth Table (also representative of COMPMC16)
Inputs A7, B7 A7>B7 A7<B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A7=B7 A6, B6 X X A6>B6 A6<B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A6=B6 A5, B5 X X X X A5>B5 A5<B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A5=B5 A4, B4 X X X X X X A4>B4 A4<B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A4=B4 A3, B3 X X X X X X X X A3>B3 A3<B3 A3=B3 A3=B3 A3=B3 A3=B3 A2, B2 X X X X X X X X X X A2>B2 A2<B2 A2=B2 A2=B2 A1, B1 X X X X X X X X X X X X A1>B1 A1<B1 A0, B0 X X X X X X X X X X X X X X Outputs GT 1 0 1 0 1 0 1 0 1 0 1 0 1 0 LT 0 1 0 1 0 1 0 1 0 1 0 1 0 1

X4264

A[15:0]

COMPMC16 GT

B[15:0]

LT

X4265

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COMPMC8, 16

COMPMC8 Truth Table (also representative of COMPMC16)


Inputs A7, B7 A7=B7 A7=B7 A7=B7 A6, B6 A6=B6 A6=B6 A6=B6 A5, B5 A5=B5 A5=B5 A5=B5 A4, B4 A4=B4 A4=B4 A4=B4
LT LO RLOC=R0C0.S1 B7 A7 C8 B6 A6 XNOR2 LO MUXCY_L RLOC=R0C0.S1 I6 S 0 1 DI CI C7 MUXCY_L I5 XNOR2 S LO RLOC=R1C0.S1 B5 A5 C6 LO RLOC=R1C0.S1 B4 A4 C5 MUXCY_L B3 A3 XNOR2 I3 S DI LO RLOC=R2C0.S1 B3 A3 XNOR2 MUXCY_L I3G S DI XNOR2 MUXCY_L I4G S DI XNOR2 MUXCY_L I5G S DI MUXCY_L B6 A6 XNOR2 I6G S DI XNOR2 MUXCY I7G S DI LO RLOC=R0C0.S0 CI C8G LO RLOC=R0C0.S0 CI C7G LO RLOC=R1C0.S0 CI C6G LO RLOC=R1C0.S0 CI C5G LO RLOC=R2C0.S0 CI C4G MUXCY_L I2G XNOR2 S DI LO RLOC=R2C0.S0 CI C2G MUXCY_L B1 A1 XNOR2 I1G S DI LO RLOC=R3C0.S0 CI C1G RLOC=R3C0.S1 DI 0 1 CI C0 MUXCY_L B0 A0 XNOR2 I0G S DI LO RLOC=R3C0.S0 CI C0G

Outputs A2, B2 A2=B2 A2=B2 A2=B2 A1, B1 A1=B1 A1=B1 A1=B1 A0, B0 A0>B0 A0<B0 A0=B0
GT

A3, B3 A3=B3 A3=B3 A3=B3

GT 1 0 0

LT 0 1 0

MUXCY B7 A7 XNOR2 I7 S

0 1 DI CI

0 1

0 1

B5 A5

0 1 DI CI

0 1

B4 A4 XNOR2

MUXCY_L I4 S DI

0 1 CI

0 1

0 1 CI C4

0 1

B2 A2 XNOR2

MUXCY_L RLOC=R2C0.S1 S I2 0 1 DI CI C2 LO MUXCY_L RLOC=R3C0.S1 I1 S 0 1 CI DI C1 MUXCY_L LO

LO

B2 A2

0 1

B1 A1 XNOR2

0 1

B0 A0 XNOR2

I0

0 1

GND

GND

A[7:0] B[7:0]

X8713

COMPMC8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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COMPMC8, 16

LT

GT

O B7 I7 XNOR2 A7 C8 S MUXCY 0 1 DI CI

RLOC=X0Y3 B7 I7G XNOR2 A7 S

O RLOC=X1Y3 MUXCY 0 1 DI CI C8G

LO B6 I6 XNOR2 S MUXCY_L 0 1 DI CI A6 C7 RLOC=X0Y3 B6 I6G XNOR2 S

LO MUXCY_L 0 1 DI CI

RLOC=X1Y3

A6

C7G LO B5 I5G XNOR2 A5 S MUXCY_L 0 1 DI CI

LO B5 I5 XNOR2 A5 C6 S MUXCY_L 0 1 DI CI

RLOC=X0Y2

RLOC=X1Y2

C6G

LO B4 I4 XNOR2 A4 S MUXCY_L 0 1 DI CI

RLOC=X0Y2 B4 I4G XNOR2 A4 C5 S

LO MUXCY_L 0 1 DI CI

RLOC=X1Y2

C5G

LO B3 I3 XNOR2 A3 S MUXCY_L 0 1 DI CI

RLOC=X0Y1 B3 I3G XNOR2 A3 C4 S

LO MUXCY_L 0 1 DI CI

RLOC=X1Y1

C4G

LO B2 I2 XNOR2 A2 S MUXCY_L 0 1 DI CI

RLOC=X0Y1

LO B2 I2G XNOR2 A2 S MUXCY_L 0 1 DI CI

RLOC=X1Y1

C2

C2G

LO B1 I1 XNOR2 A1 S MUXCY_L 0 1 DI CI

RLOC=X0Y0 B1 I1G XNOR2 A1 C1 S

LO MUXCY_L 0 1 DI CI

RLOC=X1Y0

C1G

LO B0 I0 XNOR2 A0 S MUXCY_L 0 1 DI CI

RLOC=X0Y0 B0 I0G XNOR2 A0 C0 S

LO MUXCY_L 0 1 DI CI

RLOC=X1Y0

C0G

GND A[7:0]

GND

B[7:0] X9313

COMPMC8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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379

COMPMC8, 16

Usage
For HDL, these design elements are supported for inference rather than instantiation.

VHDL Inference Code


architecture Behavioral of compmc8 is begin process (A,B) begin if (A>B) then GT <= '1'; LT <= '0'; elsif (A<B) then GT <= '0'; LT <= '1'; else GT <= '0'; LT <= '0'; end if; end process; end Behavioral;

Verilog Inference Code


always @(A or B) begin if (A > B) begin GT <= 1; LT <= 0; end else if (A < B) begin GT <= 0; LT <= 1; end else begin GT <= 0; LT <= 0; end end

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Libraries Guide ISE 6.li

CR8CE, CR16CE

CR8CE, CR16CE
8-, 16-Bit Negative-Edge Binary Ripple Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CR8CE, CR16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

CR8CE
CE C

Q[7:0]

CLR

X4116

CR8CE and CR16CE are 8-bit and 16-bit, cascadable, clearable, binary, ripple counters. The asynchronous clear (CLR), when High, overrides all other inputs and causes the Q outputs to go to logic level zero. The counter increments when the clock enable input (CE) is High during the High-to-Low clock (C) transition. The counter ignores clock transitions when CE is Low. Larger counters can be created by connecting the last Q output (Q7 for CR8CE, Q15 for CR16CE) of the first stage to the clock input of the next stage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of a ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the time tC - Q is the C-to-Qz propagation delay of each stage. The counter is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0
z = 7 for CR8CE; z = 15 for CR16CE.

CR16CE
CE C

Q[15:0]

CLR

X4120

Outputs C X X Qz Q0 0 No Chg Inc

CE X 0 1

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381

CR8CE, CR16CE

Q[7:0] Q7

FDCE_1
TQ0 CE C INV D CE C CLR Q0 Q Q0 Q3 TQ4 INV

FDCE_1
D CE C CLR Q4 Q Q4

FDCE_1
TQ1 INV D CE C CLR Q1 Q Q1 TQ5 INV

FDCE_1
D CE C CLR Q5 Q Q5

FDCE_1
TQ2 INV D CE C CLR Q2 Q Q2 TQ6 INV

FDCE_1
D CE C CLR Q6 Q Q6

FDCE_1
TQ3 INV D CE C CLR Q3 CLR Q Q3 TQ7 INV

FDCE_1
D CE C CLR Q7 Q Q7

VCC

X8142

CR8CE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

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CR8CE, CR16CE

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Q[7:0]

VCC

FDC
D AND2 XOR2 C Q

CE

CLR Q0

FDC
D AND2 XOR2 C Q

CLR Q1

FDC
D AND3 XOR2 C Q

CLR Q2

FDC
D XOR2 AND4 C Q

CLR Q3

FDC
D XOR2 AND5 C Q

CLR Q4

FDC
D XOR2 AND6 C Q

CLR Q5

FDC
D XOR2 C Q

CLR
AND7

Q6

FDC
D XOR2 C Q

CLR
AND8

Q7

C CLR

INV

X7631

CR8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of cr8ce is begin

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383

CR8CE, CR16CE

process (C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C' event and C='0') then if (CE='1') then Q <= Q + 1; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end

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CRD8CE, CRD16CE

CRD8CE, CRD16CE
8-, 16-Bit Dual-Edge Triggered Binary Ripple Counters with Clock Enable and Asynchronous Clear
Architectures Supported
CRD8CE, CRD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

CRD8CE
CE C

Q[7:0]

CLR

X9748

CRD8CE and CRD16CE are dual edge triggered 8-bit and 16-bit, cascadable, clearable, binary, ripple counters. The asynchronous clear (CLR), when High, overrides all other inputs and causes the Q outputs to go to logic level zero. The counter increments when the clock enable input (CE) is High during the High-to-Low and Low-to-High clock (C) transitions. The counter ignores clock transitions when CE is Low. Larger counters can be created by connecting the last Q output (Q7 for CRD8CE, Q15 for CRD16CE) of the first stage to the clock input of the next stage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of a ripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the time tC - Q is the C-to-Qz propagation delay of each stage. The counter is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0
z = 7 for CR8CE; z = 15 for CR16CE.

CRD16CE
CE C

Q[15:0]

CLR

X9749

Outputs C X X Qz Q0 0 No Chg Inc Inc

CE X 0 1 1

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CRD8CE, CRD16CE

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Q[7:0]

VCC CE AND2 XOR2 D C

FDDC
Q

CLR Q0

FDDC
D AND2 XOR2 C CLR Q1 Q

FDDC
D AND3 XOR2 C CLR Q2 Q

FDDC
D XOR2 AND4 C CLR Q3 Q

FDDC
D XOR2 AND5 C CLR Q4 Q

FDDC
D XOR2 AND6 C CLR Q5 Q

FDDC
D XOR2 C CLR AND7 Q6 Q

FDDC
D XOR2 C CLR AND8 Q7 Q

C CLR INV
X9750

CRD8CE Implementation CoolRunner-II

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CRD8CE, CRD16CE

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of crd8ce is begin process (C, CLR) begin if (CLR='1') then Q <= (others => '0'); elsif (C' event) then if (CE='1') then Q <= Q + 1; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) Q <= Q + 1; end

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387

CRD8CE, CRD16CE

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D2_4E

D2_4E
2- to 4-Line Decoder/Demultiplexer with Enable
Architectures Supported
D2_4E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

A0 A1 E

D2_4E

D0 D1 D2 D3

When the enable (E) input of the D2_4E decoder/demultiplexer is High, one of four active-High outputs (D3 D0) is selected with a 2-bit binary address (A1 A0) input. The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E input is the data input.

X3853

Inputs A1 X 0 0 1 1 A0 X 0 1 0 1 E 0 1 1 1 1 D3 0 0 0 0 1 D2 0 0 0 1 0
D0
AND3B2

Outputs D1 0 0 1 0 0 D0 0 1 0 0 0

D1
AND3B1

D2
AND3B1

E A0 A1
AND3

D3

X7794

D2_4E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

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D2_4E

VHDL Inference Code


architecture Behavioral of d2_4e is begin process (A, E) begin if (E='0') then D <= "0000"; else case A is when "00" => D <= "0001"; when "01" => D <= "0010"; when "10" => D <= "0100"; when "11" => D <= "1000"; when others => D <= "0000"; end case; end if; end process; end Behavioral;

Verilog Inference Code


always @ (A or E) begin if (!E) D <= 4'b0000; else begin case (A) 2'b00 : D <= 2'b01 : D <= 2'b10 : D <= 2'b11 : D <= endcase end end

4'b0001; 4'b0010; 4'b0100; 4'b1000;

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D3_8E

D3_8E
3- to 8-Line Decoder/Demultiplexer with Enable
Architectures Supported
D3_8E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

A0 A1 A2

D3_8E

D0 D1 D2 D3 D4 D5 D6

When the enable (E) input of the D3_8E decoder/demultiplexer is High, one of eight active-High outputs (D7 D0) is selected with a 3-bit binary address (A2 A0) input. The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E input is the data input.

D7

Inputs A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 E 0 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 1 D6 0 0 0 0 0 0 0 1 0 D5 0 0 0 0 0 0 1 0 0

Outputs D4 0 0 0 0 0 1 0 0 0 D3 0 0 0 0 1 0 0 0 0 D2 0 0 0 1 0 0 0 0 0 D1 0 0 1 0 0 0 0 0 0 D0 0 1 0 0 0 0 0 0 0

X3854

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391

D3_8E

D0

AND4B3

D1

AND4B2 D2

AND4B2 D3

AND4B1 D4

AND4B2 D5

AND4B1 D6

E A0 A1 A2

AND4B1 D7

AND4 X7795

D3_8E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of d3_8e is begin process (A, E) begin if (E='0') then D <= "00000000"; else case A is when "000" => D <= "00000001"; when "001" => D <= "00000010"; when "010" => D <= "00000100"; when "011" => D <= "00001000";

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D3_8E

when "100" => D <= "00010000"; when "101" => D <= "00100000"; when "110" => D <= "01000000"; when "111" => D <= "10000000"; when others => D <= "00000000"; end case; end if; end process; end Behavioral;

Verilog Inference Code


always @ (A or E) begin if (!E) D <= 8'b00000000; else begin case (A) 3'b000 : D <= 8'b00000001; 3'b001 : D <= 8'b00000010; 3'b010 : D <= 8'b00000100; 3'b011 : D <= 8'b00001000; 3'b100 : D <= 8'b00010000; 3'b101 : D <= 8'b00100000; 3'b110 : D <= 8'b01000000; 3'b111 : D <= 8'b10000000; endcase end end

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393

D3_8E

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D4_16E

D4_16E
4- to 16-Line Decoder/Demultiplexer with Enable
Architectures Supported
D4_16E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

A0 A1 A2 A3

D4_16E

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

When the enable (E) input of the D4_16E decoder/demultiplexer is High, one of 16 active-High outputs (D15 D0) is selected with a 4-bit binary address (A3 A0) input. The non-selected outputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the E input is the data input. See D3_8E for a representative truth table derivation.

D15

X3855

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395

D4_16E

D0

AND5B4

D1

AND5B3

D2

AND5B3

D3

AND5B2

D4

AND5B3

D5

AND5B2

D6

AND5B2

D7

AND5B1

D8

AND5B3

D9

AND5B2

D10

AND5B2

D11

AND5B1

D12

AND5B2

D13

AND5B1

D14

AND5B1 E A0 A1 A2 A3 AND5 X7638

D15

D4_16E Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of d4_16e is begin process (A, E) begin

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D4_16E

if (E='0') then D <= "0000000000000000"; else case A is when "0000" => D <= "0000000000000001"; when "0001" => D <= "0000000000000010"; when "0010" => D <= "0000000000000100"; when "0011" => D <= "0000000000001000"; when "0100" => D <= "0000000000010000"; when "0101" => D <= "0000000000100000"; when "0110" => D <= "0000000001000000"; when "0111" => D <= "0000000010000000"; when "1000" => D <= "0000000100000000"; when "1001" => D <= "0000001000000000"; when "1010" => D <= "0000010000000000"; when "1011" => D <= "0000100000000000"; when "1100" => D <= "0001000000000000"; when "1101" => D <= "0010000000000000"; when "1110" => D <= "0100000000000000"; when "1111" => D <= "1000000000000000"; when others => D <= "0000000000000000"; end case; end if; end process; end Behavioral;

Verilog Inference Code


always @ (A or E) begin if (!E) D <= 16'b0000000000000000; else begin case (A) 4'b0000 : D <= 16'b0000000000000001; 4'b0001 : D <= 16'b0000000000000010; 4'b0010 : D <= 16'b0000000000000100; 4'b0011 : D <= 16'b0000000000001000; 4'b0100 : D <= 16'b0000000000010000;

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397

D4_16E

4'b0101 4'b0110 4'b0111 4'b1000 4'b1001 4'b1010 4'b1011 4'b1100 4'b1101 4'b1110 4'b1111 endcase end end

: : : : : : : : : : :

D D D D D D D D D D D

<= <= <= <= <= <= <= <= <= <= <=

16'b0000000000100000; 16'b0000000001000000; 16'b0000000010000000; 16'b0000000100000000; 16'b0000001000000000; 16'b0000010000000000; 16'b0000100000000000; 16'b0001000000000000; 16'b0010000000000000; 16'b0100000000000000; 16'b1000000000000000;

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DCM

DCM
Digital Clock Manager
Architectures Supported
DCM Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

DCM CLKIN CLKFB CLK0 CLK90 CLK180 RST DSSEN CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180

DCM is a digital clock manager that provides multiple functions. It can implement a clock delay locked loop, a digital frequency synthesizer, digital phase shifter, and a digital spread spectrum. Note: All unused inputs must be driven Low. The program will automatically tie the inputs Low if they are unused.

PSINCDEC PSEN PSCLK

Clock Delay Locked Loop (DLL)


DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase when their rising edges are within a specified time (ps) of each other. See The Programmable Logic Data Book for the specified time value. DCM supports two frequency modes for the DLL. By default, the DLL_FREQUENCY_MODE attribute is set to Low and the frequency of the clock signal at the CLKIN input must be in the Low (DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF) frequency range (MHz). See The Programmable Logic Data Book for the current DLL_CLKIN_MIN_LF to DLL_CLKIN_MAX_LF frequency range values. In Low frequency mode, the CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, and CLK2X180 outputs are available. When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data Book for the current DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF frequency range values. In High frequency mode, only the CLK0, CLK180, and CLKDV outputs are available. On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock network driven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the DCM must be sourced from either the CLK0 or CLK2X outputs of the same DCM. The CLKIN input should be connected to the output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock. Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFG input connected to a pad. Either the CLK0 or CLK2X

LOCKED STATUS [7:0]

PSDONE X9469

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DCM

output can be used but not both. The CLK0 or CLK2X must be connected to the input of OBUF, an output buffer. The CLK_FEEDBACK attribute controls whether the CLK0 output, the default, or the CLK2X output is the source of the CLKFB input. The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs (CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X, CLK2X180, and CLKDV outputs is 50-50 unless CLKDV_DIVIDE is a non-integer and the DLL_FREQUENCY_MODE is High (see CLKDV_DIVIDE, in the Constraints Guide for details). The frequency of the CLKDV output is determined by the value assigned to the CLKDV_DIVIDE attribute. DCM Clock Delay Lock Loop Outputs
Output CLK0 CLK180 CLK270* CLK2X* CLK2X180* CLK90* CLKDV LOCKED Clock at 1x CLKIN frequency Clock at 1x CLK0 frequency, shifted 180o with regards to CLK0 Clock at 1x CLK0 frequency, shifted 270o with regards to CLK0 Clock at 2x CLK0 frequency, in phase with CLK0 Clock at 2x CLK0 frequency shifted 180o with regards to CLK2X Clock at 1x CLK0 frequency, shifted 90o with regards to CLK0 Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0. All enabled DCM features locked. Description

* The CLK90, CLK270, CLK2X, and CLK2X180 outputs are not available if the DLL_FREQUENCY_MODE is set to High.

Digital Frequency Synthesizer (DFS)


The CLKFX and CLKFX180 outputs in conjunction with the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes provide a frequency synthesizer that can be any multiple or division of CLKIN. CLKFX and CLKIN are in phase every CLKFX_MULTIPLY cycles of CLKFX and every CLKFX_DIVIDE cycles of CLKIN when a feedback is provided to the CLKFB input of the DLL. The frequency of CLKFX is defined by the following equation.
FrequencyCLKFX= (CLKFX_MULTIPLY_value/CLKFX_DIVIDE_value) * FrequencyCLKIN

Both the CLKFX or CLKFX180 output can be used simultaneously. CLKFX180 is 1x the CLKFX frequency, shifted 180o with regards to CLKFX. CLKFX and CLKFX180 always have a 50/50 duty cycle. The DFS_FREQUENCY_MODE attribute specifies the allowable input clock and output clock frequency ranges. The CLK_FEEDBACK attribute set to NONE will cause the DCM to be in the Digital Frequency Synthesizer mode. The CLKFX and CLKFX180 will be generated without phase correction with respect to CLKIN. See The Programmable Logic Data Book for the allowable frequency range of CLKFX.

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DCM

Digital Phase Shifter (DPS)


The phase shift (skew) between the rising edges of CLKIN and CLKFB may be configured as a fraction of the CLKIN period with the PHASE_SHIFT attribute. This allows the phase shift to remain constant as ambient conditions change. The CLKOUT_PHASE_SHIFT attribute controls the use of the PHASE_SHIFT value. By default, the CLKOUT_PHASE_SHIFT attribute is set to NONE and the PHASE_SHIFT attribute has no effect. By creating skew between CLKIN and CLKFB, all DCM output clocks are phase shifted by the amount of the skew. When the CLKOUT_PHASE_SHIFT attribute is set to FIXED, the skew set by the PHASE_SHIFT attribute is used at configuration for the rising edges of CLKIN and CLKFB. The skew remains constant. When the CLKOUT_PHASE_SHIFT attribute is set to VARIABLE, the skew set at configuration is used as a starting point and the skew value can be changed dynamically during operation using the PS* signals. This digital phase shifter feature is controlled by a synchronous interface. The inputs PSEN (phase shift enable) and PSINCDEC (phase shift increment/decrement) are set up to the rising edge of PSCLK (phase shift clock). The PSDONE (phase shift done) output is clocked with the rising edge of PSCLK (the phase shift clock). PSDONE must be connected to implement the complete synchronous interface. The rising-edge skew between CLKIN and CLKFB may be dynamically adjusted after the LOCKED output goes High. The PHASE_SHIFT attribute value specifies the initial phase shift amount when the device is configured. Then the PHASE_SHIFT value is changed one unit when PSEN is activated for one period of PSCLK. The PHASE_SHIFT value is incremented when PSINCDEC is High and decremented when PSINCDEC is Low during the period that PSEN is High. When the DCM completes an increment or decrement operation, the PSDONE output goes High for a single PSCLK cycle to indicate the operation is complete. At this point the next change may be made. When RST (reset) is High, the PHASE_SHIFT attribute value is reset to the skew value set at configuration. If CLKOUT_PHASE_SHIFT is FIXED or NONE, the PSEN, PSINCDEC, and PSCLK inputs must be tied to GND. The program will automatically tie the inputs to GND if they are not connected by the user.

Digital Spread Spectrum (DSS)


The digital spread spectrum function of DCM broadens the frequency spectrum of the output clocks to help meet FCC requirements. Spread spectrum clocking is a simple method to lower electromagnetic interference (EMI). A digital system can create a severe EMI spike at the clock frequency. Spread spectrum clocking speeds up and slows down the clock within a few percent of the target frequency, thus flattening out the EMI peak by spreading it across a range of frequencies. When the DSS_MODE attribute is set to NONE, the DSSEN input has no effect. When DSS_MODE is set to a value other than NONE and DSSEN is High, the output clock frequency is modulated by the amount of spread specified by the DSS_MODE value. For Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the DSS feature of the DCM has limited EMI reduction capability. For maximum EMI reduction an IP core available from Xilinx is recommended. Note: DSS is not supported in Spartan-3.

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DCM

Additional Status Bits


The STATUS output bits return the following information. DCM Additional Status Bits
Bit 0 1 2 3 4 5 6 7 Description Phase Shift Overflow* 1 = |PHASE_SHIFT| > 255 DLL CLKIN stopped** 1 = CLKIN stopped toggling DLL CLKFX stopped 1 = CLKFX stopped toggling No No No No No

* Phase Shift Overflow will also go high if the end of the phase shift delay line is reached (see the product data sheet for the most current value of the maximum shifting delay). ** If only the DFS outputs are used (CLKFX & CLKFX180), this status bit will not go high if CLKIN stops.

LOCKED
When LOCKED is high, all enabled signals are locked.

RST
The master reset input (RST) resets DCM to its initial (power-on) state. The signal at the RST input is asynchronous and must be held High for 2ns.

Usage
This component is generally instantiated in the code as it cannot be easily inferred in synthesis tools. Some synthesis tools may allow inference via an attribute. See your synthesis tool documentation.

VHDL Instantiation Template


-- Component Declaration for DCM should be placed -- after architecture statement but before begin keyword

component DCM -- synthesis translate_off generic (CLK_FEEDBACK : string := "1X"; CLKDV_DIVIDE : real := 2.0; -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0) CLKFX_DIVIDE : integer := 1; -- (1 to 4096)

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DCM

CLKFX_MULTIPLY : integer := 4; -- (1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 5.0, 5.5, -- 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, 16.0) CLKIN_DIVIDE_BY_2 : boolean := FALSE; -- (TRUE, FALSE) CLKOUT_PHASE_SHIFT : string := "NONE"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE) PHASE_SHIFT : real := 0; STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE) -- synthesis translate_on port (CLK0 : out STD_ULOGIC; CLK180 : out STD_ULOGIC; CLK270 : out STD_ULOGIC; CLK2X : out STD_ULOGIC; CLK2X180 : out STD_ULOGIC; CLK90 : out STD_ULOGIC; CLKDV : out STD_ULOGIC; CLKFX : out STD_ULOGIC; CLKFX180 : out STD_ULOGIC; LOCKED : out STD_ULOGIC; PSDONE : out STD_ULOGIC; STATUS : out STD_LOGIC_VECTOR (7 downto 0); CLKFB : in STD_ULOGIC; CLKIN : in STD_ULOGIC; DSSEN : in STD_ULOGIC; PSCLK : in STD_ULOGIC; PSEN : in STD_ULOGIC; PSINCDEC : in STD_ULOGIC; RST : in STD_ULOGIC); end component;

-- Component Attribute specification for DCM -- should be placed after architecture declaration but

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DCM

-- before the begin keyword

attribute CLK_FEEDBACK : string; attribute CLKDV_DIVIDE : real; attribute CLKFX_DIVIDE : integer; attribute CLKFX_MULTIPLY : integer; attribute CLKIN_DIVIDE_BY_2 : string; attribute CLKOUT_PHASE_SHIFT : string; attribute DESKEW_ADJUST : string; attribute DFS_FREQUENCY_MODE : string; attribute DLL_FREQUENCY_MODE : string; attribute DSS_MODE : string; attribute DUTY_CYCLE_CORRECTION : string; attribute PHASE_SHIFT : real; attribute STARTUP_WAIT : boolean;

attribute CLK_FEEDBACK of DCM_instance_name: label is "1X"; attribute CLKDV_DIVIDE of DCM_instance_name: label is 2.0; -- (1.5,2,2.5,3,4, 5, 8, 16) are valid for CLKDV_DIVIDE attribute CLKFX_DIVIDE of DCM_instance_name: label is 1; attribute CLKFX_MULTIPLY of DCM_instance_name: label is 4; attribute CLKIN_DIVIDE_BY_2 of DCM_instance_name: label is "FALSE"; attribute CLKOUT_PHASE_SHIFT of DCM_instance_name: label is "NONE"; attribute DESKEW_ADJUST of DCM_instance_name : label is "SYSTEM_SYNCHRONOUS"; attribute DFS_FREQUENCY_MODE of DCM_instance_name: label is "LOW"; attribute DLL_FREQUENCY_MODE of DCM_instance_name: label is "LOW"; attribute DSS_MODE of DCM_instance_name: label is "NONE"; attribute DUTY_CYCLE_CORRECTION of DCM_instance_name: label is TRUE; -- (TRUE, FALSE) are valid for DUTY_CYCLE_CORRECTION attribute PHASE_SHIFT of DCM_instance_name: label is 0; attribute STARTUP_WAIT of DCM_instance_name: label is FALSE; -- (TRUE,FALSE)

-- Component Instantiation for DCM should be placed

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DCM

-- in architecture after the begin keyword

DCM_INSTANCE_NAME : DCM -- synthesis translate_off generic map(CLK_FEEDBACK => "string_value", CLKDV_DIVIDE => real_value, -- (1.5,2,2.5,3,4,5,8,16) CLKFX_DIVIDE => integer_value, CLKFX_MULTIPLY => integer_value, CLKIN_DIVIDE_BY_2 => boolean_value, -- (TRUE, FALSE) CLKOUT_PHASE_SHIFT => "string_value", DESKEW_ADJUST => "string_value", DFS_FREQUENCY_MODE => "string_value", DLL_FREQUENCY_MODE => "string_value", DSS_MODE => "string_value", DUTY_CYCLE_CORRECTION => boolean_value, -- (TRUE, FALSE) PHASE_SHIFT => integer_value, STARTUP_WAIT => boolean) -- (TRUE, FALSE) -- synthesis translate_on port map (CLK0 => user_CLK0, CLK180 => user_CLK180, CLK270 => user_CLK270, CLK2X => user_CLK2X, CLK2X180 => user_CLK2X180, CLK90 => user_CLK90, CLKDV => user_CLKDV, CLKFX => user_CLKFX, CLKFX180 => user_CLKFX180, LOCKED => user_LOCKED) PSDONE => user_PSDONE, STATUS => user_STATUS, CLKFB => user_CLKFB, CLKIN => user_CLKIN, DSSEN => user_DSSEN, PSCLK => user_PSCLK, PSEN => user_PSEN, PSINCDEC => user_PSINCDEC,

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405

DCM

RST => user_RST);

Verilog Instantiation Template


DCM DCM_instance_name (.CLK0 (user_CLK0), .CLK180 (user_CLK180), .CLK270 (user_CLK270), .CLK2X (user_CLK2X), .CLK2X180 (user_CLK2X180), .CLK90 (user_CLK90), .CLKDV (user_CLKDV), .CLKFX (user_CLKFX), .CLKFX180 (user_CLKFX180), .LOCKED (user_LOCKED), .PSDONE (user_PSDONE), .STATUS (user_STATUS), .CLKFB (user_CLKFB), .CLKIN (user_CLKIN), .DSSEN (user_DSSEN), .PSCLK (user_PSCLK), .PSEN (user_PSEN), .PSINCDEC (user_PSINCDEC), .RST (user_RST));

defparam DCM_instance_name.CLK_FEEDBACK => "string_value"; defparam DCM_instance_name.CLKDV_DIVIDE = integer_value; //(1.5,2,2.5,3,4,5,8,16) defparam DCM_instance_name.CLKFX_DIVIDE => integer_value; defparam DCM_instance_name.CLKFX_MULTIPLY => integer_value; defparam DCM_instance_name.CLKIN_DIVIDE_BY_2 => boolean_value; // (TRUE, FALSE) defparam DCM_instance_name.CLKOUT_PHASE_SHIFT => "string_value"; defparam DCM_instance_name.DESKEW_ADJUST => "string_value"; defparam DCM_instance_name.DFS_FREQUENCY_MODE => "string_value"; defparam DCM_instance_name.DLL_FREQUENCY_MODE => "string_value"; defparam DCM_instance_name.DSS_MODE => "string_value"; defparam DCM_instance_name.DUTY_CYCLE_CORRECTION => "string_value";// (TRUE, FALSE)

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DCM

defparam DCM_instance_name.PHASE_SHIFT => integer_value; defparam DCM_instance_name.STARTUP_WAIT => boolean_value; // (TRUE, FALSE) Note: Additional syntax may be necessary in order to pass the DCM attributes via the synthesis tool. The above defparam statements may need to be isolated from the synthesis tool with translate_off/translate_on directives. See your synthesis tool documentation for more information on Verilog attribute passing to ensure that you properly pass these attributes to the synthesis tool. Otherwise, you may pass these attributes to the UCF file.

Commonly Used Constraints


CLKDV_DIVIDE CLK_FEEDBACK CLKFX_DIVIDE CLKFX_MULTIPLY CLKIN_DIVIDE_BY_2 CLKOUT_PHASE_SHIFT DUTY_CYCLE_CORRECTION DFS_FREQUENCY_MODE DLL_FREQUENCY_MODE LOC PHASE_SHIFT STARTUP_WAIT DESKEW_ADJUST

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407

DCM

408

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Libraries Guide ISE 6.li

DEC_CC4, 8, 16

DEC_CC4, 8, 16
4-, 8-, 16-Bit Active Low Decoders
Architectures Supported
DEC_CC4, DEC_CC8, DEC_CC16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

A0 A1 A2 A3 C_IN

DEC_CC4

X4927

These decoders are used to build wide-decoder functions. They are implemented by cascading CY_MUX elements driven by lookup tables (LUTs). The C_IN pin can only be driven by the output (O) of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all the inputs are High and the C_IN input is High, the output is High. You can decode patterns by adding inverters to inputs.
Inputs Outputs Az 1 X X X 0 C_IN 1 0 X X X O 1 0 0 0 0

A0 A1 A2 A3 A4 A5 A6 A7 C_IN

DEC_CC8

A0 1 X 0
O

A1 1 X X 0 X

1 X X X X

X X

X4928

z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16


O

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 C_IN

DEC_CC16
A3 A2 A1 A0 AND4 S0 MUXCY O S DI 0 1 CI

GND C_IN The C_IN pin can only be initialized by a CY_INIT or by the output of a previous decode stage.

X8717

DEC_CC4 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

X4929

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409

DEC_CC4, 8, 16

DEC_CC4
A0 A1 A0 A3 A0 A1 A2 A3 C_IN O O

DEC_CC4
A4 A5 A6 A7 C_IN A0 A1 A2 A3 C_IN O

The C_IN pin can only be initialized by a CY_INIT or by the output of a previous decode stage. X6396

DEC_CC8 Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
DEC_CC4 cannot be directly inferred or instantiated. The proper way to use a DEC_CC4 is to infer the primitive components that make up the DEC_CC4.

410

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Libraries Guide ISE 6.li

DECODE4, 8, 16

DECODE4, 8, 16
4-, 8-, 16-Bit Active-Low Decoders
Architectures Supported
DECODE4, DECODE8, DECODE16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

A0 A1 A2 A3

DECODE4

A0 A1 O A2 A3 A4 A5 A6 A7

DECODE16

A0 A1 A2 A3 A4 A5 A6 A7

DECODE8

A8 A9 A10 A11 A12 A13 A14 O A15 O

X9807

DECODE Representations In Spartan-II, , Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X decoders are implemented using combinations of LUTs and MUXCYs.

Inputs A0 1 0 X X A1 1 X 0 X 1 X X X Az 1 X X 0

Outputs* O 1 0 0 0

z = 3 for DECODE4, z = 7 for DECODE8; z = 15 for DECODE16 *A pull-up resistor must be connected to the output to establish High-level drive current.

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411

DECODE4, 8, 16

FMAP
I4 I3 S1 S0 A7 A6 A5 A4 AND4 A7 O AND2 A3 A2 A1 A0 AND4 S0 A6 A5 A4 S1 I2 I1 MAP=PUO RLOC=R0C0.S0 O O

FMAP
I4 I3 I2 I1 MAP=PUO RLOC=R0C0.S1 O S1

FMAP
A3 A2 A1 A0 X8703 I4 I3 I2 I1 MAP=PUO RLOC=R0C0.S1 O S0

DECODE8 Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E


FMAP
I4 I3 S1 S0 I2 I1 MAP=PUO RLOC=X0Y1 A7 A6 A5 A4 AND4 S1 O O

FMAP
A7 A6 A5 A4 O AND2 MAP=PUO RLOC=X0Y0 I4 I3 I2 I1 O S1

A3 A2 A1 A0 AND4 S0 A3 A2 A1 A0 I4 I3 I2 I1

FMAP

S0

MAP=PUO RLOC=X0Y0 X9316

DECODE8 Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferrred rather than instantiated.

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DECODE4, 8, 16

VHDL Inference Code


architecture Behavioral of decode4 is begin process (A) begin case A is when "1111" => O <= '1'; when others => O <= '0'; end case; end process; end Behavioral;

Verilog Inference Code


always @(A) begin case (A) 4'h0 : O <= 1; default : O <= 0; endcase end

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413

DECODE4, 8, 16

414

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DECODE32, 64

DECODE32, 64
32- and 64-Bit Active-Low Decoders
Architectures Supported
DECODE3, DECODE2, DECODE64 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
A[31:0] DECODE32 O

Macro Macro Macro No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

DECODE32 and DECODE64 are 32- and 64-bit active-low decoders. These decoders are implemented using combinations of LUTs and MUXCYs. See DECODE4, 8, 16 for a representative schematic.

X8203

Inputs
A[63:0] DECODE64

Outputs 1 X X X Az 1 X X 0 O 1 0 0 0

A0
O

A1 1 X 0 X

1
X8204

0 X X

z = 31 for DECODE32, z = 63 for DECODE64

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of decode32 is begin process (A) begin case A is when x"11111111" => O <= '1'; when others => O <= '0'; end case; end process; end Behavioral;

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415

DECODE32, 64

Verilog Inference Code


always @(A) begin case (A) 32'h00000000 : O <= 1; default : O <= 0; endcase end

416

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FD

FD
D Flip-Flop
Architectures Supported
FD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FD

FD is a single D-type flip-flop with data input (D) and data output (Q). The data on the D inputs is loaded into the flip-flop during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.

X3715

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. See FD4, 8, 16 for information on multiple D flip-flops for XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II.
Inputs D 0 1
FDCP
D C PRE Q

Outputs C Q 0 1

D C

CLR Q

X7797 GND

FD Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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417

FD

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fd is begin process (C) begin if C'event and C='1' then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FD should be placed -- after architecture statement but before begin keyword component FD -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FD -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FD_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FD should be placed -- in architecture after the begin keyword FD_INSTANCE_NAME : FD -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D);

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FD

Verilog Instantiation Template


FD FD_instance_name (.Q (user_Q), .C (user_C), .D (user_D)); defparam FD_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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419

FD

420

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FD_1

FD_1
D Flip-Flop with Negative-Edge Clock
Architectures Supported
FD_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FD_1

FD_1 is a single D-type flip-flop with data input (D) and data output (Q). The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.

X3726

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs D 0 1 C Outputs Q 0 1

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fd_1 is begin process (C) begin if C' event and C = '0' then Q <= D; end if; end process; end Behavioral;

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FD_1

Verilog Inference Code


always @ (negedge C) begin Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FD_1 should be placed -- after architecture statement but before begin keyword component FD_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FD_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FD_1_instance_name : label is "0"; -- values can be (0 or 1)

begin FD_1_INSTANCE_NAME : FD_1 -- synthesis translate_off generic map ( INIT => bit_value) -- INIT value can be '0' or '1' -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D); end Behavioral

Verilog Instantiation Template


FD_1 FD_1_instance_name (.Q (user_Q), .C (user_C), .D (user_D)); defparam FD_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM

422

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FD4, 8, 16

FD4, 8, 16
Multiple D Flip-Flops
Architectures Supported
FD4, FD8, FD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D0 D1 D2 D3 C

FD4

Q0 Q1 Q2 Q3

FD4, FD8, FD16 are multiple D-type flip-flops with data inputs (D) and data outputs (Q). FD4, FD8, and FD16 are, respectively, 4-bit, 8-bit, and 16-bit registers, each with a common clock (C). The data on the D inputs is loaded into the flip-flop during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

X4608

D[7:0]

FD8

Q[7:0]

Inputs
C

Outputs C Qz Q0 0 1

Dz D0
X4609

0 1
z = 3 for FD4; z = 7 for FD8; z = 15 for FD16

D[15:0]

FD16

Q[15:0]

C X4610

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423

FD4, 8, 16

Q[7:0] FD D0
D C Q

FD Q0 D4
D C Q

Q4

Q0 FD D1
D C Q

Q4 FD Q1 D5
D C Q

Q5

Q1 FD D2
D C Q

Q5 FD Q2 D6
D C Q

Q6

Q2 FD D3
D C Q

Q6 FD Q3 D7
D C Q

Q7

D[7:0] C

Q3

Q7

X8128

FD8 Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fd4 is begin process (C) begin if C' event and C='1' then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin Q <= D; end

424

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FD4CE, FD8CE, FD16CE

FD4CE, FD8CE, FD16CE


4-, 8-, 16-Bit Data Registers with Clock Enable and Asynchronous Clear
Architectures Supported
FD4CE, FD8CE, FD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D0 D1 D2 D3 CE C

FD4CE

Q0 Q1 Q2 Q3

FD4CE, FD8CE, and FD16CE are, respectively, 4-, 8-, and 16-bit data registers with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputs and resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

CLR

X3733

D[7:0] CE C

FD8CE

Q[7:0]

CLR

X3850

D[15:0] CE C

FD16CE

Q[15:0]

GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR CE X 0 1 Dz D0 X X Dn C X X Outputs Qz Q0 0 No Chg Dn

CLR

X3736

1 0 0

z = 3 for FD4CE; z = 7 for FD8CE; z = 15 for FD16CE.

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425

FD4CE, FD8CE, FD16CE

Q[7:0]

FDCE FDCE
D0 D CE C CLR Q0 Q Q0 D4 D CE C CLR Q4 Q Q4

FDCE FDCE
D1 D CE C CLR Q1 Q Q1 D5 D CE C CLR Q5 Q Q5

FDCE FDCE
D2 D CE C CLR Q2 Q Q2 D6 D CE C CLR Q6 Q Q6

FDCE FDCE
D3 D CE C CLR Q3 D[7:0] CE C CLR X7799 Q Q3 D7 D CE C CLR Q7 Q Q7

FD8CE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

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FD4CE, FD8CE, FD16CE

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 4'b0000; else begin if (CE) Q <= D; end end

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427

FD4CE, FD8CE, FD16CE

428

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FD4RE, FD8RE, FD16RE

FD4RE, FD8RE, FD16RE


4-, 8-, 16-Bit Data Registers with Clock Enable and Synchronous Reset
Architectures Supported
FD4RE, FD8RE, FD16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D0 D1 D2 D3 CE C

FD4RE

Q0 Q1 Q2 Q3

X3734

FD4RE, FD8RE, and FD16RE are, respectively, 4-, 8-, and 16-bit data registers. When the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during the Low-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q) Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied.

D[7:0] CE C

FD8RE

Q[7:0]

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active.

X3735

D[15:0] CE C

FD16RE

Q[15:0]

GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R CE X 0 1 Dz D0 X X Dn C X Outputs Qz Q0 0 No Chg Dn

X3737

1 0 0

z = 3 for FD4RE; z = 7 for FD8RE; z = 15 for FD16RE

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429

FD4RE, FD8RE, FD16RE

Q[7:0]

FDRE
D0 D CE C R Q0 Q Q0 D4

FDRE
D CE C R Q4 Q Q4

FDRE
D1 D CE C R Q1 Q Q1 D5

FDRE
D CE C R Q5 Q Q5

FDRE
D2 D CE C R Q2 Q Q2 D6

FDRE
D CE C R Q6 Q Q6

FDRE
D3 D CE C R Q3 D[7:0] CE C R Q Q3 D7

FDRE
D CE C R Q7 Q Q7

X8195

FD8RE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fd4re is begin process (C) begin if (C' event and C = '1') then if (R = '1') then Q <= "0000"; elsif (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

430

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FD4RE, FD8RE, FD16RE

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 4'b0000; else begin if (CE) Q <= D; end end

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431

FD4RE, FD8RE, FD16RE

432

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Libraries Guide ISE 6.li

FDC

FDC
D Flip-Flop with Asynchronous Clear
Architectures Supported
FDC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FDC

FDC is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q). The asynchronous CLR, when High, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low on the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 D X 1 0
FDCP
D C CLR PRE Q

CLR

X3716

Outputs C X Q 0 1 0

D C

CLR Q

X7801 GND

FDC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

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FDC

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdc is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event and C = '1') then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or posedge CLR) begin if (CLR) Q <= 0; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDC should be placed -- after architecture statement but before begin keyword component FDC -- synthesis translate_off generic (INIT : bit:= '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDC -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDC_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDC should be placed -- in architecture after the begin keyword FDC_INSTANCE_NAME : FDC -- synthesis translate_off

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FDC

generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D);

Verilog Instantiation Template


FDC FDC_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D)); defparam FDC_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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435

FDC

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FDC_1

FDC_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
Architectures Supported
FDC_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FDC_1

FDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q). The asynchronous CLR, when active, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 D X 1 0 C X Outputs Q 0 1 0

CLR X3847

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdc_1 is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event and C = '0') then Q <= D; end if;

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437

FDC_1

end process; end Behavioral;

Verilog Inference Code


always @ (negedge C or posedge CLR) begin if (CLR) Q <= 0; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDC_1 should be placed -- after architecture statement but before begin keyword component FDC_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDC_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDC_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDC_1 should be placed -- in architecture after the begin keyword FDC_1_INSTANCE_NAME : FDC_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D);

Verilog Instantiation Template


FDC_1 FDC_1_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D)); defparam FDC_1_instance_name.INIT = bit_value;

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FDC_1

Commonly Used Constraints


BLKNM, HBLKNM, U_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM

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FDC_1

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FDCE

FDCE
D Flip-Flop with Clock Enable and Asynchronous Clear
Architectures Supported
FDCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDCE

FDCE is a single D-type flip-flop with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of FDCE is transferred to the corresponding data output (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For XC9500XL and XC9500XV devices, logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDCE and FDPE flip-flops primitives may take advantage of the clock-enable p-term. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 CE X 0 1 1 D X X 1 0 C X X Outputs Q 0 No Chg 1 0

CLR

X3717

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

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FDCE

VHDL Inference Code


architecture Behavioral of fdce is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge CLR or posedge C) begin if (CLR) Q <= 0; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDCE should be placed -- after architecture statement but before begin keyword component FDCE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDCE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCE_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDCE should be placed -- in architecture after the begin keyword FDCE_INSTANCE_NAME : FDCE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C,

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FDCE

CE => user_CE, CLR => user_CLR, D => user_D);

Verilog Instantiation Template


FDCE FDCE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D)); defparam FDCE_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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FDCE

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FDCE_1

FDCE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Clear
Architectures Supported
FDCE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDCE_1

CLR

X3727

FDCE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs, and data output (Q). The asynchronous CLR input, when High, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 0 No Chg 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdce_1 is begin process (C, CLR) begin if (CLR = '1') then

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FDCE_1

Q <= '0'; elsif (C' event and C = '0') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge CLR or negedge C) begin if (CLR) Q <= 0; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDCE_1 should be placed -- after architecture statement but before begin keyword component FDCE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDCE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCE_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDCE_1 should be placed -- in architecture after the begin keyword FDCE_1_INSTANCE_NAME : FDCE_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D);

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FDCE_1

Verilog Instantiation Template


FDCE_1 FDCE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D)); defparam FDCE_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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FDCP

FDCP
D Flip-Flop Asynchronous Preset and Clear
Architectures Supported
FDCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

PRE

FDCP
Q

FDCP is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low on the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 PRE X 1 0 0 D X X 0 1 C X X Outputs Q 0 1 0 1

CLR X4397

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdcp is begin process (C, CLR, PRE) begin if (CLR = '1') then

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FDCP

Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge CLR or posedge PRE or posedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDCP should be placed -- after architecture statement but before begin keyword component FDCP -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCP_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDCP should be placed -- in architecture after the begin keyword FDCP_INSTANCE_NAME : FDCP -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D, PRE => user_PRE);

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FDCP

Verilog Instantiation Template


FDCP FDCP_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCP_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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FDCP

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FDCP_1

FDCP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and Clear
Architectures Supported
FDCP_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

FDCP_1
Q

FDCP_1 is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low on the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR X8357

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 PRE X 1 0 0 D X X 0 1 C X X Outputs Q 0 1 0 1

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdcp_1 is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0';

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FDCP_1

elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '0') then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge CLR or posedge PRE or negedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDCP_1 should be placed -- after architecture statement but before begin keyword component FDCP_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCP_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCP_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDCP_1 should be placed -- in architecture after the begin keyword FDCP_1_INSTANCE_NAME : FDCP_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D, PRE => user_PRE);

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FDCP_1

Verilog Instantiation Template


FDCP_1 FDCP_1_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCP_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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FDCP_1

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FDCPE

FDCPE
D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
Architectures Supported
FDCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Macro Macro Primitive

PRE

D CE C

FDCPE
Q

FDCPE is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR X4389

For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 PRE X 1 0 0 0 CE X X 0 1 1 D X X X 0 1 C X X X Outputs Q 0 1 No Chg 0 1

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FDCPE

VCC

CE AND2 AND2B1

D AND2 PRE OR2

FDCP
D PRE Q

C CLR

C CLR Q

X7804

FDCPE Implementation XC9500/XV/XL, CoolRunner XPLA3

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdcpe is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge CLR or posedge PRE or posedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDCPE should be placed -- after architecture statement but before begin keyword

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FDCPE

component FDCPE -- synthesis translate_off generic (INIT : bit:= '1'); -- synthesis translate_on port(Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCPE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCPE_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDCPE should be placed -- in architecture after the begin keyword FDCPE_INSTANCE_NAME : FDCPE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDCPE FDCPE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCPE_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM.

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FDCPE

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FDCPE_1

FDCPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset and Clear
Architectures Supported
FDCPE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

PRE

D CE C

FDCPE_1
Q

FDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied.

CLR X8360

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 PRE X 1 0 0 0 CE X X 0 1 1 D X X X 0 1 C X X X Outputs Q 0 1 No Chg 0 1

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

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461

FDCPE_1

VHDL Inference Code


architecture Behavioral of fdcpe_1 is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event and C = '0') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge CLR or posedge PRE or negedge C) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDCPE_1 should be placed -- after architecture statement but before begin keyword component FDCPE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDCPE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDCPE_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDCPE_1 should be placed -- in architecture after the begin keyword FDCPE_1_INSTANCE_NAME : FDCPE_1

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FDCPE_1

-- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDCPE_1 FDCPE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDCPE_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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463

FDCPE_1

464

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Libraries Guide ISE 6.li

FDD

FDD
Dual Edge Triggered D Flip-Flop
Architectures Supported
FDD Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
FDD

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDD is a single dual edge triggered D-type flip-flop with data input (D) and data output (Q). The data on the D input is loaded into the flip-flop during the Low-toHigh and the High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net. See FDD4,8,16 for information on multiple D flip-flops for CoolRunner-II.

X9661

Inputs D 0 1 0 1
FDDCP
D C PRE Q

Outputs C Q 0 1 0 1

D C

CLR Q

GND

X9662

FDD Implementation CoolRunner-II

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465

FDD

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdd is begin process (C) begin if C' event then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDD should be placed -- after architecture statement but before begin keyword component FDD -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDD -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDD_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDD should be placed -- in architecture after the begin keyword FDD_INSTANCE_NAME : FDD -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D);

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FDD

Verilog Instantiation Template


FDD FDD_instance_name (.Q (user_Q), .C (user_C), .D (user_D)); defparam FDD_instance_name.INIT = bit_value;

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467

FDD

468

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Libraries Guide ISE 6.li

FDD4,8,16

FDD4,8,16
Multiple Dual Edge Triggered D Flip-Flops
Architectures Supported
FDD4, FDD8, FDD16 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D0 D1 D2 D3 C

FDD4

Q0 Q1 Q2 Q3

FDD4, FDD8, FDD16 are multiple dual edge triggered D-type flip-flops with data inputs (D) and data outputs (Q). FDD4, FDD8, and FDD16 are, respectively, 4-bit, 8bit, and 16-bit registers, each with a common clock (C). The data on the D inputs is loaded into the flip-flop during the Low-to-High and High-to-Low clock (C) transitions. The flip-flops are asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

X9663

D[7:0]

FDD8

Q[7:0]

Inputs
X9664

Outputs C Qz Q0 0 1 0 1

Dz D0 0

D[15:0]

FDD16

Q[15:0]

1 0 1

X9665

z = 3 for FDD4; z = 7 for FDD8; z = 15 for FDD16

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469

FDD4,8,16

Q[7:0]

FDD
D0 D C Q0 Q Q0 D4 D C

FDD
Q Q4

Q4

FDD
D1 D C Q1 Q Q1 D5 D C

FDD
Q Q5

Q5

FDD
D2 D C Q2 Q Q2 D6 D C

FDD
Q Q6

Q6

FDD
D3 D C D[7:0] Q3 Q Q3 D7 D C

FDD
Q Q7

Q7

X9666

FDD8 Implementation CoolRunner-II

Usage
For HDL, these deign elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fdd4 is begin process (C) begin if C' event then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin Q[3:0] <= D[3:0] ; end

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FDD4CE, FDD8CE, FDD16CE

FDD4CE, FDD8CE, FDD16CE


4-, 8-, 16-Bit Dual Edge Triggered Data Registers with Clock Enable and Asynchronous Clear
Architectures Supported
FDD4CE, FDD8CE, FDD16CE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D0 D1 D2 D3 CE C

FDD4CE

Q0 Q1 Q2 Q3

FDD4CE, FDD8CE, and FDD16CE are, respectively, 4-, 8-, and 16-bit data registers with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q) during the Low-to-High and High-to-Low clock (C) transitions. When CLR is High, it overrides all other inputs and resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

CLR

X9667

D[7:0] CE C

FDD8CE

Q[7:0]

Inputs
CLR
X9668

Outputs Dz D0 X X Dn Dn C X X Qz Q0 0 No Chg Dn Dn

CLR 1

CE X 0 1 1

D[15:0] CE C

FDD16CE

Q[15:0]

0 0 0

CLR

X9669

z = 3 for FDD4CE; z = 7 for FDD8CE; z = 15 for FDD16CE.

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471

FDD4CE, FDD8CE, FDD16CE

Q[7:0]

FDDCE FDDCE
D0 D CE C CLR Q0 Q Q0 D4 D CE C CLR Q4 Q Q4

FDDCE FDDCE
D1 D CE C CLR Q1 Q Q1 D5 D CE C CLR Q5 Q Q5

FDDCE FDDCE
D2 D CE C CLR Q2 Q Q2 D6 D CE C CLR Q6 Q Q6

FDDCE FDDCE
D3 D CE C CLR Q3 D[7:0] CE C CLR
X9670

D7 Q Q3

D CE C CLR

Q7

Q7

FDD8CE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fdd4ce is begin process (C, CLR) begin if (CLR = '1') then Q <= "0000"; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 4'b0; else if (CE) Q[3:0] <= D[3:0]; end

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FDD4RE, FDD8RE, FDD16RE

FDD4RE, FDD8RE, FDD16RE


4-, 8-, 16-Bit Dual Edge Triggered Data Registers with Clock Enable and Synchronous Reset
Architectures Supported
FDD4RE, FDD8RE, FDD16RE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D0 D1 D2 D3 CE C

FDD4RE

Q0 Q1 Q2 Q3

R
X9671

FDD4RE, FDD8RE, and FDD16RE are, respectively, 4-, 8-, and 16-bit data registers. When the clock enable (CE) input is High, and the synchronous reset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during the Low-to-High or High-to-Low clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q) Low on the Low-to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flops are asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

D[7:0] CE C

FDD8RE

Q[7:0]

Inputs
R
X9672

Outputs Dz D0 X X X Dn Dn C X Qz Q0 0 0 No Chg Dn Dn

R
D[15:0] CE C

CE X X 0 1 1

FDD16RE

Q[15:0]

1 1 0 0 0

X9673

z = 3 for FDD4RE; z = 7 for FDD8RE; z = 15 for FDD16RE

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473

FDD4RE, FDD8RE, FDD16RE

Q[7:0]

FDDRE
D0 D CE C R Q0 Q Q0 D4

FDDRE
D CE C R Q4 Q Q4

FDDRE
D1 D CE C R Q1 Q Q1 D5

FDDRE
D CE C R Q5 Q Q5

FDDRE
D2 D CE C R Q2 Q Q2 D6

FDDRE
D CE C R Q6 Q Q6

FDDRE
D3 D CE C R Q3 D[7:0] CE C R Q Q3 D7

FDDRE
D CE C R Q7 Q Q7

X9674

FDD8RE Implementation CoolRunner-II

Usage
For HDL, these design elements are inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fdd4re is begin process (C) begin if (C' event) then if (CE = '1') then if (R = '1') then Q <= "0000"; else Q <= D; end if; end if; end if; end process; end Behavioral;

474

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FDD4RE, FDD8RE, FDD16RE

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 4'b0; else if (CE) Q[3:0] <= D[3:0] ; end

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475

FDD4RE, FDD8RE, FDD16RE

476

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Libraries Guide ISE 6.li

FDDC

FDDC
D Dual Edge Triggered Flip-Flop with Asynchronous Clear
Architectures Supported
FDDC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDDC

CLR

X9675

FDDC is a single dual edge triggered D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and data output (Q). The asynchronous CLR, when High, overrides all other inputs and sets the Q output Low. The data on the D input is loaded into the flip-flop when CLR is Low on the Low-to-High and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 D X 1 1 0 0
FDDCP
D C CLR PRE Q

Outputs C X Q 0 1 1 0 0

D C

CLR Q

GND

X9676

FDDC Implementation CoolRunner-II

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477

FDDC

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fddc is begin process (C,CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event) then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 1'b0; else Q <= D ; end

VHDL Instantiation Template


-- Component Declaration for FDDC should be placed -- after architecture statement but before begin keyword component FDDC -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDDC -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDC_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDDC should be placed -- in architecture after the begin keyword FDDC_INSTANCE_NAME : FDDC

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FDDC

-- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D);

Verilog Instantiation Template


FDDC FDDC_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D)); defparam FDDC_instance_name.INIT = bit_value;

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479

FDDC

480

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FDDCE

FDDCE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Clear
Architectures Supported
FDDCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDDCE

CLR

X9677

FDDCE is a single dual edge triggered D-type flip-flop with clock enable and asynchronous clear. When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of FDDCE is transferred to the corresponding data output (Q) during the Low-to-High and High-to-Low clock (C) transitions. When CLR is High, it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net. Logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDDCE and FDDPE flip-flops primitives may take advantage of the clock-enable p-term.

Inputs CLR 1 0 0 0 0 0 CE X 0 1 1 1 1 D X X 1 0 1 0 C X X

Outputs Q 0 No Chg 1 0 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

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481

FDDCE

VHDL Inference Code


architecture Behavioral of fddce is begin process (C, CLR) begin if (CLR = '1') then Q <= '0'; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 1'b0; else if (CE) Q <= D ; end

VHDL Instantiation Template


-- Component Declaration for FDDCE should be placed -- after architecture statement but before begin keyword component FDDCE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDDCE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here

-- Component Instantiation for FDDCE should be placed -- in architecture after the begin keyword FDDCE_INSTANCE_NAME : FDDCE port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D);

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FDDCE

Verilog Instantiation Template


FDDCE FDDCE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D));

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483

FDDCE

484

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FDDCP

FDDCP
Dual EdgeArchitectures Supported Triggered D Flip-Flop Asynchronous Preset and Clear
Architectures Supported
FDDCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

No No No No No Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

FDDCP
Q

FDDCP is a single dual edge triggered D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR) inputs, and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low on the Low-toHigh and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

CLR
X9678

Inputs CLR 1 0 0 0 0 0 PRE X 1 0 0 0 0 D X X 0 1 0 1 C X X

Outputs Q 0 1 0 1 0 1

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fddcp is begin process (C, CLR, PRE) begin if (CLR = '1') then

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485

FDDCP

Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event) then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 1'b0; else if (PRE) Q <= 1'b1; else Q <= D ; end

VHDL Instantiation Template


-- Component Declaration for FDDCP should be placed -- after architecture statement but before begin keyword component FDDCP -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDCP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDCP_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDDCP should be placed -- in architecture after the begin keyword FDDCP_INSTANCE_NAME : FDDCP -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CLR => user_CLR, D => user_D,

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FDDCP

PRE => user_PRE);

Verilog Instantiation Template


FDDCP FDDCP_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .D (user_D), .PRE (user_PRE)); defparam FDDCP_instance_name.INIT = bit_value;

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487

FDDCP

488

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FDDCPE

FDDCPE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
Architectures Supported
FDDCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

PRE

D CE C

FDDCPE
Q

FDDCPE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High and High-to-Low clock (C) transitions. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

CLR
X9679

Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 CE X X 0 1 1 1 1 D X X X 0 1 0 1 C X X X

Outputs Q 0 1 No Chg 0 1 0 1

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489

FDDCPE

VCC

CE AND2 AND2B1

D AND2 PRE OR2

FDDCP
PRE Q

D C CLR C

CLR Q

X9680

FDDCPE Implementation CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fddcpe is begin process (C, CLR, PRE) begin if (CLR = '1') then Q <= '0'; elsif (PRE = '1') then Q <= '1'; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 1'b0; else if (PRE) Q <= 1'b1; else if (CE) Q <= D ; end

VHDL Instantiation Template


-- Component Declaration for FDDCPE should be placed -- after architecture statement but before begin keyword

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FDDCPE

component FDDCPE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDCPE -- should be placed after architecture declaration but -- before the begin keyword

-- Enter values here

-- Component Instantiation for FDDCPE should be placed -- in architecture after the begin keyword FDDCPE_INSTANCE_NAME : FDDCPE port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDDCPE FDDCPE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .D (user_D), .PRE (user_PRE));

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491

FDDCPE

492

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Libraries Guide ISE 6.li

FDDP

FDDP
Dual Edge Triggered D Flip-Flop with Asynchronous Preset
Architectures Supported
FDDP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDDP

FDDP is a single dual edge triggered D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the Low-to-High and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

X9681

Inputs PRE 1 0 0 0 0 C X D X 1 0 1 0

Outputs Q 1 1 0 1 0

PRE D C

FDDCP
PRE Q

D C

CLR Q

GND

X9682

FDDP Implementation CoolRunner-II

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493

FDDP

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Inference Code


architecture Behavioral of fddp is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event) then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge PRE) begin if (PRE) Q <= 1'b1; else Q <= D ; end

VHDL Instantiation Template


-- Component Declaration for FDDP should be placed -- after architecture statement but before begin keyword component FDDP -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDP -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDP_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDDP should be placed -- in architecture after the begin keyword FDDP_INSTANCE_NAME : FDDP -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on

494

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FDDP

port map (Q => user_Q, C => user_C, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDDP FDDP_instance_name (.Q (user_Q), .C (user_C), .D (user_D), .PRE (user_PRE)); defparam FDDP_instance_name.INIT = bit_value;

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495

FDDP

496

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Libraries Guide ISE 6.li

FDDPE

FDDPE
Dual Edge Triggered D Flip-Flop with Clock Enable and Asynchronous Preset
Architectures Supported
FDDPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

No No No No No Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDDPE

FDDPE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the Low-toHigh and High-to-Low clock (C) transitions. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net. Logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDDCE and FDDPE flip-flops primitives may take advantage of the clock-enable p-term.

X9683

Inputs PRE 1 0 0 0 0 0 CE X 0 1 1 1 1 D X X 0 1 0 1 C X X

Outputs Q 1 No Chg 0 1 0 1

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

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497

FDDPE

VHDL Inference Code


architecture Behavioral of fddpe is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event) then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C or posedge PRE) begin if (PRE) Q <= 1'b1; else if (CE) Q <= D ; end

VHDL Instantiation Template


-- Component Declaration for FDDPE should be placed -- after architecture statement but before begin keyword component FDDPE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDPE -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes here -- Component Instantiation for FDDPE should be placed -- in architecture after the begin keyword FDDPE_INSTANCE_NAME : FDDPE port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDDPE FDDPE_instance_name (.Q (user_Q),

498

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FDDPE

.C (user_C), .CE (user_CE), .D (user_D), .PRE (user_PRE)); defparam FDDPE_instance_name.INIT = bit_value;

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499

FDDPE

500

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FDDR

FDDR
Dual Edge Triggered D Flip-Flop with Synchronous Reset
Architectures Supported
FDDR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDDR

X9684

FDDR is a single dual edge triggered D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High and Highto-Low clock (C) transitions. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High or High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

Inputs R 1 1 0 0 0 0 D X X 1 0 1 0
FDD
D_R AND2B1 C
X9685

Outputs C Q 0 0 1 0 1 0

D R C

FDDR Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

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501

FDDR

VHDL Inference Code


architecture Behavioral of fddr is begin process (C) begin if (C' event) then if (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else Q <= D ; end

502

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FDDRCPE

FDDRCPE
Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
Architectures Supported
FDDRCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE D0 D1 CE C0 C1 CLR X9399 FDDRCPE Q

No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

FDDRCPE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). It also has clock enable (CE), asynchronous preset (PRE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the Q output High; CLR, when High, resets the output Low. Data on the D0 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when PRE and CLR are Low and CE is High on the Low-to-High C1 clock transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. Use the INIT attribute to initialize FDDRCPE during configuration.

Inputs C0 X X X X X C1 X X X X X CE X X X 0 1 1 D0 X X X X D0 X D1 X X X X X D1 CLR 1 0 1 0 0 0 PRE 0 1 1 0 0 0

Outputs Q 0 1 0 No Chg D0 D1

Usage
For HDL, this design element is instantiated rather than inferred.

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503

FDDRCPE

VHDL Instantiation Template


-- Component Declaration for FDDRCPE should be placed -- after architecture statement but before begin keyword component FDDRCPE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDDRCPE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDRCPE_instance_name : label is "0"; -- values can be (0 or 1) -- Component Instantiation for FDDRCPE should be placed -- in architecture after the begin keyword FDDRCPE_INSTANCE_NAME : FDDRCPE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C0 => user_C0, C1 => user_C1, CE => user_CE, CLR => user_CLR, D0 => user_D0, D1 => user_D1, PRE => user_PRE);

504

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FDDRCPE

Verilog Instantiation Template


FDDRCPE FDDRCPE_instance_name (.Q (user_Q), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .CLR (user_CLR), .D0 (user_D0), .D1 (user_D1), .PRE (user_PRE)); defparam FDDRCPE_instance_name.INIT = bit_value;

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505

FDDRCPE

506

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FDDRE

FDDRE
Dual Edge Triggered D Flip-Flop with Clock Enable and Synchronous Reset
Architectures Supported
FDDRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDDRE

X9686

FDDRE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High or High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High and High-toLow clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 0 CE X X 0 1 1 1 1 D X X X 1 0 1 0 C X Outputs Q 0 0 No Chg 1 0 1 0

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507

FDDRE

VCC

CE AND2 R AND3B2

D D

FDD
OR2 AND3B1 Q Q

C Q
X9687

FDDRE Implementation CoolRunner-II

Usage
For HDL, this design element can be inferred but not instantiated.

VHDL Inference Code


architecture Behavioral of fddre is begin process (C) begin if (C event) then if (R = 1) then Q <= 0; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else if (CE) Q <= D ; end

508

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FDDRRSE

FDDRRSE
Dual Data Rate D Flip-Flop with Clock Enable and Synchronous Reset and Set
Architectures Supported
FDDRRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S D0 D1 CE C0 C1 R X9254 FDDRRSE Q

No Primitive No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

FDDRRSE is a Dual Data Rate (DDR) D flip-flop with two separate clocks (C0 and C1) phase shifted 180 degrees that allow selection of two separate data inputs (D0 and D1). It also has synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during any Low-to-High clock transition (C0 or C1). (Reset has precedence over Set.) When the S input is High and R is Low, the flip-flop is set, output High, during a Low-to-High clock transition (C0 or C1). Data on the D0 input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High C0 clock transition. Data on the D1 input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High C1 clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Use the INIT attribute to initialize FDDRRSE during configuration.

Inputs C0 X X X X X C1 X X X X X CE X X X X X X 0 1 1 D0 X X X X X X X D0 X D1 X X X X X X X X D1 R 1 0 1 1 0 1 0 0 0 S 0 1 1 0 1 1 0 0 0

Outputs Q 0 1 0 0 1 0 No Chg D0 D1

Usage
For HDL, this design element is instantiated rather than inferred.

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509

FDDRRSE

VHDL Instantiation Template


-- Component Declaration for FDDRRSE should be placed -- after architecture statement but before begin keyword component FDDRRSE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C0 : in STD_ULOGIC; C1 : in STD_ULOGIC; CE : in STD_ULOGIC; D0 : in STD_ULOGIC; D1 : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDDRRSE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDDRRSE_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDDRRSE should be placed -- in architecture after the begin keyword FDDRRSE_INSTANCE_NAME : FDDRRSE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C0 => user_C0, C1 => user_C1, CE => user_CE, D0 => user_D0, D1 => user_D1, R => user_R, S => user_S);

510

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FDDRRSE

Verilog Instantiation Template


FDDRRSE FDDRRSE_instance_name (.Q (user_Q), .C0 (user_C0), .C1 (user_C1), .CE (user_CE), .D0 (user_D0), .D1 (user_D1), .R (user_R), .S (user_S)); defparam FDDRRSE_instance_name.INIT = bit_value;

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511

FDDRRSE

512

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FDDRS

FDDRS
Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set
Architectures Supported
FDDRS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDDRS

X9688

FDDRS is a single dual edge triggered D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High or High-to-Low clock (C) transitions. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the Low-toHigh or High-to-Low clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High and High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.
Inputs R 1 1 0 0 0 0 0 0 S X X 1 1 0 0 0 0 D X X X X 1 1 0 0 C Outputs Q 0 0 1 1 1 1 0 0

D R AND2B1 S AND2B1 C OR2 D C Q


X9689

FDD
Q Q

FDDRS Implementation CoolRunner-II

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513

FDDRS

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fddrs is begin process (C) begin if (C' event) then if (R = '1') then Q <= '0'; elsif (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else if (S) Q <= 1'b1; else Q <= D ; end

VHDL Instantiation Template


-- Component Declaration for FDDRS should be placed -- after architecture statement but before begin keyword component FDDRS -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDDRS -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string;

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FDDRS

attribute INIT of FDDRS_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDDRS should be placed -- in architecture after the begin keyword FDDRS_INSTANCE_NAME : FDDRS -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R, S => user_S);

Verilog Instantiation Template


FDDRS FDDRS_instance_name (.Q .C .D .R .S (user_Q), (user_C), (user_D), (user_R), (user_S));

defparam FDDRS_instance_name.INIT = bit_value;

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515

FDDRS

516

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FDDRSE

FDDRSE
Dual Edge Triggered D Flip-Flop with Synchronous Reset and Set and Clock Enable
Architectures Supported
FDDRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDDRSE

X9690

FDDRSE is a single dual edge triggered D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High or High-to-Low clock transitions. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High or High-to-Low clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High and Highto-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

Inputs R 1 1 0 0 0 0 0 0 0 S X X 1 1 0 0 0 0 0 CE X X X X 0 1 1 1 1 D X X X X X 1 0 1 0 C X

Outputs Q 0 0 1 1 No Chg 1 0 1 0

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517

FDDRSE

VCC CE AND2 S OR3 AND2B1

D AND2 R C AND2B1 C D

FDD
Q Q

X9691

FDDRSE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fddrse is begin process (C) begin if (C event) then if (R = 1) then Q <= 0; elsif (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (R) Q <= 1'b0; else if (S) Q <= 1'b1; else if (CE) Q <= D ; end

518

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FDDS

FDDS
Dual Edge Triggered D Flip-Flop with Synchronous Set
Architectures Supported
FDDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDDS

FDDS is a single dual edge triggered D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q output High on the Low-to-High or High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low during the Low-to-High and Highto-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

X9692

Inputs S 1 1 0 0 0 0 D X X 1 0 1 0 C

Outputs Q 1 1 1 0 1 0

D S C OR2 D

FDD
Q Q

C Q
X9693

FDDS Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide ISE 6.li

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519

FDDS

VHDL Inference Code


architecture Behavioral of fdds is begin process (C) begin if (C' event) then if (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else Q <= D ; end

520

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FDDSE

FDDSE
D Flip-Flop with Clock Enable and Synchronous Set
Architectures Supported
FDDSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDDSE

X9694

FDDSE is a single dual edge triggered D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the Low-to-High or High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the Low-to-High and High-to-Low clock (C) transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

Inputs S 1 1 0 0 0 0 0 CE X X 0 1 1 1 1 D X X X 1 0 1 0 C X

Outputs Q 1 1 No Chg 1 0 1 0

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521

FDDSE

VCC CE AND2 S OR3 AND2B1

D AND2 D C

FDD
Q Q Q

C Q
X9695

FDDSE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fddse is begin process (C) begin if (C event) then if (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else if (CE) Q <= D ; end

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FDDSR

FDDSR
Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset
Architectures Supported
FDDSR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDDSR

R
X9696

FDDSR is a single dual edge triggered D-type flip-flop with data (D), synchronous reset (R) and synchronous set (S) inputs and data output (Q). When the set (S) input is High, it overrides all other inputs and sets the Q output High during the Low-to-High or High-to-Low clock transition. (Set has precedence over Reset.) When reset (R) is High and S is Low, the flip-flop is reset, output Low, on the Low-to-High or High-toLow clock transition. Data on the D input is loaded into the flip-flop when S and R are Low on the Low-to-High and High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

Inputs S 1 1 0 0 0 0 0 0 R X X 1 1 0 0 0 0 D X X X X 1 0 1 0 C

Outputs Q 1 1 0 0 1 0 1 0

D R AND2B1 S C OR2 C Q
X9697

FDD
D Q Q

FDDSR Implementation CoolRunner-II

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523

FDDSR

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fddsr is begin process (C) begin if (C' event) then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else if (R) Q <= 1'b0; else Q <= D; end

524

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FDDSRE

FDDSRE
Dual Edge Triggered D Flip-Flop with Synchronous Set and Reset and Clock Enable
Architectures Supported
FDDSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDDSRE

R
X9698

FDDSRE is a single dual edge triggered D-type flip-flop with synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, it overrides all other inputs and sets the Q output High during the Low-to-High or High-to-Low clock transition. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low during the Low-to-High or High-to-Low clock transition. Data is loaded into the flipflop when S and R are Low and CE is High during the Low-to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated in Verilog by applying a High-level pulse on the PRLD global net.

Inputs S 1 1 0 0 0 0 0 0 0 R X X 1 1 0 0 0 0 0 CE X X X X 0 1 1 1 1 D X X X X X 1 0 1 0 C X

Outputs Q 1 1 0 0 No Chg 1 0 1 0

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525

FDDSRE

VCC

CE AND2 R AND3B2 S OR3 D C D

FDD
Q Q

AND3B1 C
X9699

FDDSRE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fddsre is begin process (C) begin if (C' event) then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; elsif (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C or negedge C) begin if (S) Q <= 1'b1; else if (R) Q <= 1'b0; else if (CE) Q <= D; end

526

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Libraries Guide ISE 6.li

FDE

FDE
D Flip-Flop with Clock Enable
Architectures Supported
FDE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDE
Q

FDE is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q). When clock enable is High, the data on the D input is loaded into the flipflop during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.

X8361

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CE 0 1 1 D X 0 1 C X Outputs Q No Chg 0 1

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fde is begin process (C) begin if (C' event and C='1') then if (CE = '1') then Q <= D; end if; end if;

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527

FDE

end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDE should be placed -- after architecture statement but before begin keyword component FDE -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDE_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDE should be placed -- in architecture after the begin keyword FDE_INSTANCE_NAME : FDE -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D);

Verilog Instantiation Template


FDE FDE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D)); defparam FDE_instance_name.INIT = bit_value;

528

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FDE

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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529

FDE

530

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FDE_1

FDE_1
D Flip-Flop with Negative-Edge Clock and Clock Enable
Architectures Supported
FDE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDE_1
Q

FDE_1 is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q). When clock enable is High, the data on the D input is loaded into the flipflop during the High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied.

X8362

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CE 0 1 1 D X 0 1 C X Outputs Q No Chg 0 1

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fde_1 is begin process (C) begin if (C' event and C='0') then if (CE = '1') then Q <= D; end if; end if;

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531

FDE_1

end process; end Behavioral;

Verilog Inference Code


always @ (negedge C) begin if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDE_1 should be placed -- after architecture statement but before begin keyword component FDE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for FDE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDE_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDE_1 should be placed -- in architecture after the begin keyword FDE_1_INSTANCE_NAME : FDE_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D);

Verilog Instantiation Template


FDE_1 FDE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D)); defparam FDE_1_instance_name.INIT = bit_value;

532

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FDE_1

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET,INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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533

FDE_1

534

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Libraries Guide ISE 6.li

FDP

FDP
D Flip-Flop with Asynchronous Preset
Architectures Supported
FDP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FDP

FDP is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the Low-to-High clock (C) transition. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 C X D X 1 0 Outputs Q 1 1 0

X3720

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535

FDP

PRE D C

FDCP
PRE Q

D C

CLR Q

GND

X7805

FDP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdp is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then Q <= D; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge PRE or posedge C) begin if (PRE) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDP should be placed -- after architecture statement but before begin keyword component FDP -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDP

536

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FDP

-- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDP_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDP should be placed -- in architecture after the begin keyword FDP_INSTANCE_NAME : FDP -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDP FDP_instance_name (.Q (user_Q), .C (user_C), .D (user_D), .PRE (user_PRE)); defparam FDP_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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537

FDP

538

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Libraries Guide ISE 6.li

FDP_1

FDP_1
D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
Architectures Supported
FDP_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FDP_1

FDP_1 is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. The data on the D input is loaded into the flip-flop when PRE is Low on the High-to-Low clock (C) transition. The flip-flop is asynchronously preset, output High, when power is applied.

X3728

Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 C X D X 1 0 Outputs Q 1 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdp_1 is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event and C = '0') then Q <= D; end if;

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539

FDP_1

end process; end Behavioral;

Verilog Inference Code


always @ (posedge PRE or negedge C) begin if (PRE) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDP_1 should be placed -- after architecture statement but before begin keyword component FDP_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDP_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDP_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDP_1 should be placed -- in architecture after the begin keyword FDP_1_INSTANCE_NAME : FDP_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDP_1 FDP_1_instance_name (.Q (user_Q), .C (user_C), .D (user_D), .PRE (user_PRE)); defparam FDP_1_instance_name.INIT = bit_value;

540

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FDP_1

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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541

FDP_1

542

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Libraries Guide ISE 6.li

FDPE

FDPE
D Flip-Flop with Clock Enable and Asynchronous Preset
Architectures Supported
FDPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Primitive Primitive Primitive Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDPE

FDPE is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For XC9500XL and XC9500XV devices, logic connected to the clock enable (CE) input may be implemented using the clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented using the single p-term available for clock enable without requiring feedback from another macrocell. Only FDCE and FDPE flip-flop primitives may take advantage of the clock-enable p-term. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. These devices simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 CE X 0 1 1 D X X 0 1 C X X Outputs Q 1 No Chg 0 1

X3721

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543

FDPE

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdpe is begin process (C,PRE) begin if (PRE = '1') then Q <= '1'; elsif (C' event and C = '1') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge PRE or posedge C) begin if (PRE) Q <= 1; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDPE should be placed -- after architecture statement but before begin keyword component FDPE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDPE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDPE_instance_name : label is "0"; -- values can be (0 or 1)

544

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FDPE

-- Component Instantiation for FDPE should be placed -- in architecture after the begin keyword FDPE_INSTANCE_NAME : FDPE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, PRE => user_PRE);

Verilog Instantiation Template


FDPE FDPE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .PRE (user_PRE)); defparam FDPE_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM

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545

FDPE

546

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Libraries Guide ISE 6.li

FDPE_1

FDPE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset
Architectures Supported
FDPE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

PRE

D CE C

FDPE_1

FDPE_1 is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the Q output High. Data on the D input is loaded into the flip-flop when PRE is Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-III, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X simulate power-on when global set/reset (GSR) is active. The active level of the GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 CE X 0 1 1 D X X 1 0 C X X Outputs Q 1 No Chg 1 0

X3852

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdpe_1 is begin process (C,PRE) begin if (PRE = '1') then

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547

FDPE_1

Q <= '1'; elsif (C' event and C = '0') then if (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge PRE or negedge C) begin if (PRE) Q <= 1; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDPE_1 should be placed -- after architecture statement but before begin keyword component FDPE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC); end component; -- Component Attribute specification for FDPE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDPE_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDPE_1 should be placed -- in architecture after the begin keyword -FDPE_1_INSTANCE_NAME : FDPE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, PRE => user_PRE);

548

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FDPE_1

Verilog Instantiation Template


FDPE_1 FDPE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .PRE (user_PRE)); defparam FDPE_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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549

FDPE_1

550

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FDR

FDR
D Flip-Flop with Synchronous Reset
Architectures Supported
FDR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FDR

X3718

FDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 D X 1 0 C Outputs Q 0 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdr is begin process (C) begin if (C' event and C = '1') then

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551

FDR

if (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDR should be placed -- after architecture statement but before begin keyword component FDR -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDR -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDR_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDR should be placed -- in architecture after the begin keyword FDR_INSTANCE_NAME : FDR -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R);

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FDR

Verilog Instantiation Template


FDR FDR_instance_name (.Q .C .D .R (user_Q), (user_C), (user_D), (user_R));

defparam FDR_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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553

FDR

554

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Libraries Guide ISE 6.li

FDR_1

FDR_1
D Flip-Flop with Negative-Edge Clock and Synchronous Reset
Architectures Supported
FDR_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
FDR_1
Q C

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

R X8363

FDR_1 is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the High-to-Low clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 D X 1 0 C Outputs Q 0 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdr_1 is begin process (C) begin if (C' event and C = '0') then if (R = '1') then Q <= '0'; else

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555

FDR_1

Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (negedge C) begin if (R) Q <= 0; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDR_1 should be placed -- after architecture statement but before begin keyword component FDR_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDR_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDR_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDR_1 should be placed -- in architecture after the begin keyword FDR_1_INSTANCE_NAME : FDR_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R);

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FDR_1

Verilog Instantiation Template


FDR_1 FDR_1_instance_name (.Q .C .D .R (user_Q), (user_C), (user_D), (user_R));

defparam FDR_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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557

FDR_1

558

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Libraries Guide ISE 6.li

FDRE

FDRE
D Flip-Flop with Clock Enable and Synchronous Reset
Architectures Supported
FDRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDRE

X3719

FDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 0 No Chg 1 0

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559

FDRE

VCC

CE AND2 R AND3B2

D D

FD
OR2 AND3B1 Q Q

C Q
X7808

FDRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdre is begin process (C) begin if (C event and C = 1) then if (R = 1) then Q <= 0; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDRE should be placed -- after architecture statement but before begin keyword component FDRE -- synthesis translate_off generic (

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FDRE

INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDRE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRE_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDRE should be placed -- in architecture after the begin keyword FDRE_INSTANCE_NAME : FDRE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R);

Verilog Instantiation Template


FDRE FDRE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R)); defparam FDRE_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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561

FDRE

562

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Libraries Guide ISE 6.li

FDRE_1

FDRE_1
D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset
Architectures Supported
FDRE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
FDRE_1
Q

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

R X8364

FDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the High-to-Low clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 0 No Chg 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdre_1 is begin process (C) begin if (C event and C = 0) then

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563

FDRE_1

if (R = 1) then Q <= 0; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (negedge C) begin if (R) Q <= 0; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDRE_1 should be placed -- after architecture statement but before begin keyword component FDRE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC); end component; -- Component Attribute specification for FDRE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRE_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDRE_1 should be placed -- in architecture after the begin keyword FDRE_1_INSTANCE_NAME : FDRE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R);

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FDRE_1

Verilog Instantiation Template


FDRE_1 FDRE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R)); defparam FDRE_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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565

FDRE_1

566

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Libraries Guide ISE 6.li

FDRS

FDRS
D Flip-Flop with Synchronous Reset and Set
Architectures Supported
FDRS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FDRS

X3731

FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flipflop is set, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 S X 1 0 0 D X X 1 0 C Outputs Q 0 1 1 0

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567

FDRS

D R AND2B1 S AND2B1 C OR2 D C Q X7811

FD
Q Q

FDRS Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdrs is begin process (C) begin if (C' event and C = '1') then if (R = '1') then Q <= '0'; elsif (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDRS should be placed -- after architecture statement but before begin keyword component FDRS -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC;

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FDRS

C : in D : in R : in S : in end component;

STD_ULOGIC; STD_ULOGIC; STD_ULOGIC; STD_ULOGIC);

-- Component Attribute specification for FDRS -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRS_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDRS should be placed -- in architecture after the begin keyword FDRS_INSTANCE_NAME : FDRS -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R, S => user_S);

Verilog Instantiation Template


FDRS FDRS_instance_name (.Q .C .D .R .S (user_Q), (user_C), (user_D), (user_R), (user_S));

defparam FDRS_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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569

FDRS

570

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FDRS_1

FDRS_1
D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set
Architectures Supported
FDRS_1

Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

FDRS_1
Q

R X8365

FDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Highto-Low clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the High-to-Low clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the High-toLow clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 S X 1 0 0 D X X 1 0 C Outputs Q 0 1 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

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571

FDRS_1

VHDL Inference Code


architecture Behavioral of fdrs_1 is begin process (C) begin if (C' event and C = '0') then if (R = '1') then Q <= '0'; elsif (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDRS_1 should be placed -- after architecture statement but before begin keyword component FDRS_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDRS_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRS_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDRS_1 should be placed -- in architecture after the begin keyword FDRS_1_INSTANCE_NAME : FDRS_1

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FDRS_1

-- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, R => user_R, S => user_S);

Verilog Instantiation Template


FDRS_1 FDRS_1_instance_name (.Q .C .D .R .S (user_Q), (user_C), (user_D), (user_R), (user_S));

defparam FDRS_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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573

FDRS_1

574

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Libraries Guide ISE 6.li

FDRSE

FDRSE
D Flip-Flop with Synchronous Reset and Set and Clock Enable
Architectures Supported
FDRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDRSE

X3732

FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 S X 1 0 0 0 CE X X 0 1 1 D X X X 1 0 C X Outputs Q 0 1 No Chg 1 0

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575

FDRSE

VCC CE AND2 S OR3 AND2B1

D AND2 R C AND2B1 C D

FD
Q Q

FDRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdrse is begin process (C) begin if (C event and C = 1) then if (R = 1) then Q <= 0; elsif (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE) Q <= D; end

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FDRSE

VHDL Instantiation Template


-- Component Declaration for FDRSE should be placed -- after architecture statement but before begin keyword component FDRSE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDRSE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRSE_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDRSE should be placed -- in architecture after the begin keyword FDRSE_INSTANCE_NAME : FDRSE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R, S => user_S);

Verilog Instantiation Template


FDRSE FDRSE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R), .S (user_S)); defparam FDRSE_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET and XBLKNM

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577

FDRSE

578

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Libraries Guide ISE 6.li

FDRSE_1

FDRSE_1
D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set, and Clock Enable
FDRSE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDRSE_1
Q

R X8366

FDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the High-to-Low clock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the High-to-Low clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the High-to-Low clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 S X 1 0 0 0 CE X X 0 1 1 D X X X 1 0 C X Outputs Q 0 1 No Chg 1 0

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

Libraries Guide ISE 6.li

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579

FDRSE_1

VHDL Inference Code


architecture Behavioral of fdrse_1 is begin process (C) begin if (C event and C = 0) then if (R = 1) then Q <= 0; elsif (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else Q => D; end

VHDL Instantiation Template


-- Component Declaration for FDRSE_1 should be placed -- after architecture statement but before begin keyword component FDRSE_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; R : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDRSE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDRSE_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDRSE_1 should be placed -- in architecture after the begin keyword

580

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FDRSE_1

FDRSE_1_INSTANCE_NAME : FDRSE_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, R => user_R, S => user_S);

Verilog Instantiation Template


FDRSE_1 FDRSE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .R (user_R), .S (user_S)); defparam FDRSE_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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581

FDRSE_1

582

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Libraries Guide ISE 6.li

FDS

FDS
D Flip-Flop with Synchronous Set
Architectures Supported
FDS Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D C

FDS

FDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q output High on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low during the Low-to-High clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. For all other devices (XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II), the flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDS will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 D X 1 0 C Outputs Q 1 1 0

X3722

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

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583

FDS

VHDL Inference Code


architecture Behavioral of fds is begin process (C) begin if (C' event and C = '1') then if (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (S) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDS should be placed -- after architecture statement but before begin keyword component FDS -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDS -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDS_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDS should be placed -- in architecture after the begin keyword FDS_INSTANCE_NAME : FDS -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q,

584

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FDS

C => user_C, D => user_D, S => user_S);

Verilog Instantiation Template


FDS FDS_instance_name (.Q .C .D .S (user_Q), (user_C), (user_D), (user_S));

defparam FDS_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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585

FDS

586

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Libraries Guide ISE 6.li

FDS_1

FDS_1
D Flip-Flop with Negative-Edge Clock and Synchronous Set
Architectures Supported
FDS_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

FDS_1
Q

FDS_1 is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). The synchronous set input, when High, sets the Q output High on the High-to-Low clock (C) transition. The data on the D input is loaded into the flipflop when S is Low during the High-to-Low clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDS_1 will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 D X 1 0 C Outputs Q 1 1 0

X8367

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fds_1 is begin process (C) begin if (C' event and C = '0') then

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587

FDS_1

if (S = '1') then Q <= '1'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (negedge C) begin if (S) Q <= 1; else Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDS_1 should be placed -- after architecture statement but before begin keyword component FDS_1 -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDS_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDS_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDS_1 should be placed -- in architecture after the begin keyword FDS_1_INSTANCE_NAME : FDS_1 -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, D => user_D, S => user_S);

588

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FDS_1

Verilog Instantiation Template


FDS_1 FDS_1_instance_name (.Q .C .D .S (user_Q), (user_C), (user_D), (user_S));

defparam FDS_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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589

FDS_1

590

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Libraries Guide ISE 6.li

FDSE

FDSE
D Flip-Flop with Clock Enable and Synchronous Set
Architectures Supported
FDSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Primitive Primitive Primitive Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

D CE C

FDSE

FDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the Low-to-High clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. For all other devices (XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II), the flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDSE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 1 No Chg 1 0

X3723

Libraries Guide ISE 6.li

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591

FDSE

VCC CE AND2 S OR3 AND2B1

D AND2 D C C

FD
Q Q Q

Q
X7815

FDSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

VHDL Inference Code


architecture Behavioral of fdse is begin process (C) begin if (C event and C = 1) then if (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) begin if (S) Q <= 1; else if (CE) Q <= D; end

592

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FDSE

VHDL Instantiation Template


-- Component Declaration for FDSE should be placed -- after architecture statement but before begin keyword component FDSE -- synthesis translate_off generic ( INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDSE -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDSE_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDSE should be placed -- in architecture after the begin keyword FDSE_INSTANCE_NAME : FDSE -- synthesis translate_off generic map ( INIT => bit_value) -- synthesis translate_on port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, S => user_S);

Verilog Instantiation Template


FDSE FDSE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .S (user_S)); defparam FDSE_instance_name.INIT = bit_value;

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593

FDSE

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

594

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FDSE_1

FDSE_1
D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set
Architectures Supported
FDSE_1 Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDSE_1
Q

FDSE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output High during the High-toLow clock (C) transition. The data on the D input is loaded into the flip-flop when S is Low and CE is High during the High-to-Low clock (C) transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FDSE_1 will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 CE X 0 1 1 D X X 1 0 C X Outputs Q 1 No Chg 1 0

X8368

Usage
This design element typically should be inferred in the design code; however, the element can be instantiated for cases where strict placement control, relative placement control, or initialization attributes need to be applied.

Libraries Guide ISE 6.li

www.xilinx.com 1-800-255-7778

595

FDSE_1

VHDL Inference Code


architecture Behavioral of fdse_1 is begin process (C) begin if (C event and C = 0) then if (S = 1) then Q <= 1; elsif (CE = 1) then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (negedge C) begin if (S) Q <= 1; else if (CE) Q <= D; end

VHDL Instantiation Template


-- Component Declaration for FDSE_1 should be placed -- after architecture statement but before begin keyword component FDSE_1 -- synthesis translate_off generic (INIT : bit := '1'); -- synthesis translate_on port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; D : in STD_ULOGIC; S : in STD_ULOGIC); end component; -- Component Attribute specification for FDSE_1 -- should be placed after architecture declaration but -- before the begin keyword attribute INIT : string; attribute INIT of FDSE_1_instance_name : label is "0"; -- values can be (0 or 1)

-- Component Instantiation for FDSE_1 should be placed -- in architecture after the begin keyword

FDSE_1_INSTANCE_NAME : FDSE_1 -- synthesis translate_off generic map (INIT => bit_value) -- synthesis translate_on

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FDSE_1

port map (Q => user_Q, C => user_C, CE => user_CE, D => user_D, S => user_S);

Verilog Instantiation Template


FDSE_1 FDSE_1_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .D (user_D), .S (user_S)); defparam FDSE_1_instance_name.INIT = bit_value;

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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597

FDSE_1

598

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Libraries Guide ISE 6.li

FDSR

FDSR
D Flip-Flop with Synchronous Set and Reset
Architectures Supported
FDSR Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D C

FDSR

X3729

FDSR is a single D-type flip-flop with data (D), synchronous reset (R) and synchronous set (S) inputs and data output (Q). When the set (S) input is High, it overrides all other inputs and sets the Q output High during the Low-to-High clock transition. (Set has precedence over Reset.) When reset (R) is High and S is Low, the flip-flop is reset, output Low, on the Low-to-High clock transition. Data on the D input is loaded into the flip-flop when S and R are Low on the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs S 1 0 0 0
D R AND2B1 S C OR2 C Q X7817 D

Outputs D X X 1 0 C Q 1 0 1 0

R X 1 0 0

FD
Q Q

FDSR Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide ISE 6.li

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599

FDSR

VHDL Inference Code


architecture Behavioral of fdsr is begin process (C) begin if (C' event and C = '1') then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; else Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) if (S) Q <= else if (R) Q <= else Q <= end begin 1; 0; D;

600

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FDSRE

FDSRE
D Flip-Flop with Synchronous Set and Reset and Clock Enable
Architectures Supported
FDSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D CE C

FDSRE

X3730

FDSRE is a single D-type flip-flop with synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, it overrides all other inputs and sets the Q output High during the Low-to-High clock transition. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low during the Low-to-High clock transition. Data is loaded into the flip-flop when S and R are Low and CE is High during the Low-to-high clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs S 1 0 0 0 0 R X 1 0 0 0 CE X X 0 1 1 D X X X 1 0 C X Outputs Q 1 0 No Chg 1 0

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601

FDSRE

VCC

CE AND2 R AND3B2 S OR3 D C D

FD
Q Q

AND3B1 C
X7819

FDSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fdsre is begin process (C) begin if (C' event and C = '1') then if (S = '1') then Q <= '1'; elsif (R = '1') then Q <= '0'; elsif (CE = '1') then Q <= D; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @ (posedge C) if (S) Q <= else if (R) Q <= else if (CE) Q <= end begin 1; 0; D;

602

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FJKC

FJKC
J-K Flip-Flop with Asynchronous Clear
Architectures Supported
FJKC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

J K C

FJKC
Q

FJKC is a single J-K-type flip-flop with J, K, and asynchronous clear (CLR) inputs and data output (Q). The asynchronous clear (CLR) input, when High, overrides all other inputs and resets the Q output Low. When CLR is Low, the output responds to the state of the J and K inputs, as shown in the following truth table, during the Low-toHigh clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 J X 0 0 1 1 K X 0 1 0 1 C X Outputs Q 0 No Chg 0 1 Toggle

CLR

X3753

Libraries Guide ISE 6.li

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603

FJKC

AND3B2

A0 A1 A2 AD OR3

AND3B1 J K AND2B1 C CLR

FDC
D C CLR Q Q

X7820

FJKC Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-II Pro X

K AND2B1

FDC
J AND2B1 C CLR OR2 C CLR Q X7821 D Q Q

FJKC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fjkc is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q;

604

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FJKC

end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end

Libraries Guide ISE 6.li

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605

FJKC

606

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FJKCE

FJKCE
J-K Flip-Flop with Clock Enable and Asynchronous Clear
Architectures Supported
FJKCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

J K CE C

FJKCE
Q

CLR

X3756

FJKCE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous clear (CLR) inputs and data output (Q). The asynchronous clear (CLR), when High, overrides all other inputs and resets the Q output Low. When CLR is Low and CE is High, Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition. When CE is Low, the clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 CE X 0 1 1 1 1 J X X 0 0 1 1 K X X 0 1 0 1 C X X X Outputs Q 0 No Chg No Chg 0 1 Toggle

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607

FJKCE

AND3B2

A0 A1 A2 AD OR3

AND3B1 J K AND2B1

FDCE
D CE C CLR X7822 CE C CLR Q Q

FJKCE Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, VirtexII, Virtex-II Pro, Virtex-II Pro X
VCC

CE AND2 AND2B1 J

FDC
AND3B1 K AND2B1 C CLR
X782

D OR3 C CLR

FJKCE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fjkce is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then

608

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Libraries Guide ISE 6.li

FJKCE

if (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end

Libraries Guide ISE 6.li

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609

FJKCE

610

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Libraries Guide ISE 6.li

FJKCP

FJKCP
J-K Flip-Flop with Asynchronous Clear and Preset
Architectures Supported
FJKCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

J K C

FJKCP
Q

CLR

FJKCP is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), and asynchronous preset (PRE) inputs and data output (Q). When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. The asynchronous preset (PRE), when High, and CLR set to Low overrides all other inputs and sets the Q output High. When CLR and PRE are Low, Q responds to the state of the J and K inputs during the Low-to-High clock transition, as shown in the following truth table. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 0 PRE X 1 0 0 0 0 J X X 0 0 1 1 K X X 0 1 0 1 C X X X Outputs Q 0 1 No Chg 0 1 Toggle

X4390

Libraries Guide ISE 6.li

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611

FJKCP

AND2B1 PRE

FDCP
PRE Q

D K OR2 AND2B1 C CLR C

CLR Q

X8124

FJKCP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fjkcp is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1;

612

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FJKCP

else begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end

613

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FJKCP

614

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Libraries Guide ISE 6.li

FJKCPE

FJKCPE
J-K Flip-Flop with Asynchronous Clear and Preset and Clock Enable
Architectures Supported
FJKCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

J K CE C

FJKCPE
Q

CLR X4391

FJKCPE is a single J-K-type flip-flop with J, K, asynchronous clear (CLR), asynchronous preset (PRE), and clock enable (CE) inputs and data output (Q). When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. The asynchronous preset (PRE), when High, and CLR set to Low overrides all other inputs and sets the Q output High. When CLR and PRE are Low and CE is High, Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock transition. Clock transitions are ignored when CE is Low. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 CE X X 0 1 1 1 1 J X X 0 0 0 1 1 K X X X 0 1 0 1 C X X X X Outputs Q 0 1 No Chg No Chg 0 1 Toggle

Libraries Guide ISE 6.li

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615

FJKCPE

VCC 5

CE AND2B1 J AND2

FDCP
PRE D AND3B1 OR3 C CLR AND2B1 Q Q Q

K PRE C CLR

X7687

FJKCPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fjkcpe is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

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FJKCPE

Verilog Inference Code


always @(posedge C or posedge CLR begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) begin if (!J) begin if (K) Q end else begin if (!K) Q else Q end end end or posedge PRE)

<= 0;

<= 1; <= !Q;

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617

FJKCPE

618

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Libraries Guide ISE 6.li

FJKP

FJKP
J-K Flip-Flop with Asynchronous Preset
Architectures Supported
FJKP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

J K C

FJKP
Q

FJKP is a single J-K-type flip-flop with J, K, and asynchronous preset (PRE) inputs and data output (Q). The asynchronous preset (PRE) input, when High, overrides all other inputs and sets the Q output High. When PRE is Low, the Q output responds to the state of the J and K inputs, as shown in the following truth table, during the Low-toHigh clock transition. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs PRE 1 0 0 0 0 J X 0 0 1 1 K X 0 1 0 1 C X X Outputs Q 1 No Chg 0 1 Toggle

X3754

Libraries Guide ISE 6.li

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619

FJKP

AND3B2

A0 A1 A2 AD OR3

AND3B1 J K AND2B1 PRE

FDP
D PRE Q

C RLOC=R0C0 X7824

FJKP Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0 A1 A2 AD

AND3B1 J K AND2B1 PRE

OR3

FDP
PRE D Q Q

C RLOC=X0Y0 X9317

FJKP Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


J

AND2B1 PRE

FDP
PRE Q

D K OR2 AND2B1 C C

X8125

FJKP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

620

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Libraries Guide ISE 6.li

FJKP

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fjkp is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end

Libraries Guide ISE 6.li

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621

FJKP

622

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Libraries Guide ISE 6.li

FJKPE

FJKPE
J-K Flip-Flop with Clock Enable and Asynchronous Preset
Architectures Supported
FJKPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

PRE

J K CE C

FJKPE
Q

FJKPE is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous preset (PRE), when High, overrides all other inputs and sets the Q output High. When PRE is Low and CE is High, the Q output responds to the state of the J and K inputs, as shown in the truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset, output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs PRE 1 0 0 0 0 0 CE X 0 1 1 1 1 J X X 0 0 1 1 K X X 0 1 0 1 C X X X Outputs Q 1 No Chg No Chg 0 1 Toggle

X3757

Libraries Guide ISE 6.li

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623

FJKPE

AND3B2

A0 A1 A2 AD OR3

AND3B1 J K AND2B1 PRE

FDPE
D CE C RLOC=R0C0 X7825 PRE Q

CE C

FJKPE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0 A1 A2 AD OR3

AND3B1 J K AND2B1 PRE

FDPE
D PRE Q Q

CE C

CE C RLOC=X0Y0 X9318

FJKPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

624

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FJKPE

VCC

CE AND2 K AND2B1 J AND3B1 OR3 C AND2B1

FDP
D PRE Q

C PRE

X7826

FJKPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of fjkpe is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (CE)

Libraries Guide ISE 6.li

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625

FJKPE

begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end

626

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Libraries Guide ISE 6.li

FJKRSE

FJKRSE
J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
Architectures Supported
FJKRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

J K CE C

FJKRSE
Q

FJKRSE is a single J-K-type flip-flop with J, K, synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). When synchronous reset (R) is High, all other inputs are ignored and output Q is reset Low. (Reset has precedence over Set.) When synchronous set (S) is High and R is Low, output Q is set High. When R and S are Low and CE is High, output Q responds to the state of the J and K inputs, according to the following truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 0 0 S X 1 0 0 0 0 0 CE X X 0 1 1 1 1 J X X X 0 0 1 1 K X X X 0 1 1 0 C X X Outputs Q 0 1 No Chg No Chg 0 Toggle 1

X3760

Libraries Guide ISE 6.li

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627

FJKRSE

AND3B2

A0 A1 A2 AD_S

AND3B1 J K AND2B1 S CE C R RLOC=R0C0 X7827 OR2 S_CE D CE C R OR4

FDRE
Q Q

FJKRSE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0 A1 A2 AD_S OR4

AND3B1 J K S CE C R AND2B1

FDRE
D S_CE OR2 CE C R RLOC=X0Y0 X9319 Q Q

FJKRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro


VCC

CE K S AND2

AND4B1

AND3B3 D J AND3B3 R NOR4 C

FD
Q Q

Q C
X8126

FJKRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

628

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Libraries Guide ISE 6.li

FJKRSE

VHDL Inference Code


architecture Behavioral of fjkrse is begin process (C) begin if (C'event and C='1') then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE) begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end

Libraries Guide ISE 6.li

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629

FJKRSE

630

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Libraries Guide ISE 6.li

FJKSRE

FJKSRE
J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
Architectures Supported
FJKSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

J K CE C

FJKSRE
Q

FJKSRE is a single J-K-type flip-flop with J, K, synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, all other inputs are ignored and output Q is set High. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low. When S and R are Low and CE is High, output Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FJKSRE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 0 0 0 R X 1 0 0 0 0 0 CE X X 0 1 1 1 1 J X X X 0 0 1 1 K X X X 0 1 0 1 C X X Outputs Q 1 0 No Chg No Chg 0 1 Toggle

X3759

Libraries Guide ISE 6.li

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631

FJKSRE

AND3B2

A0 A1 A2 AD OR3 AD_R AND2B1

AND3B1 J K S AND2B1

FDSE
S Q

R CE C OR2

R_CE

D CE C

X7828

FJKSRE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

AND3B2

A0 A1 A2 OR3 AD AD_R AND2B1

AND3B1 J K AND2B1 S R CE C

FDSE
S D R_CE OR2 CE C RLOC=X0Y0 X9320 Q Q

FJKSRE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


VCC

CE AND2 K AND3 J R S C NAND2B1 C Q


X8127

AND2B2

AND2B2

OR4 D

FD
Q Q

FJKSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

632

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FJKSRE

VHDL Inference Code


architecture Behavioral of fjksre is begin process (C) begin if (C'event and C='1') then if (S='1') then Q <= '1'; elsif (R='1') then Q <= '0'; elsif (CE='1') then if (J='0') then if (K='1') then Q <= '0'; end if; else if (K='0') then Q <= '1'; else Q <= not Q; end if; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C) begin if (S) Q <= 1; else if (R) Q <= 0; else if (CE) begin if (!J) begin if (K) Q <= 0; end else begin if (!K) Q <= 1; else Q <= !Q; end end end

Libraries Guide ISE 6.li

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633

FJKSRE

634

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Libraries Guide ISE 6.li

FMAP

FMAP
F Function Generator Partitioning Control Symbol
Architectures Supported
FMAP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

I4 I3 I2 I1

FMAP
O

The FMAP symbol is used to map logic to the function generator of a slice. See the appropriate CAE tool interface user guide for information about specifying this attribute in your schematic design editor. The MAP=type parameter can be used with the FMAP symbol to further define how much latitude you want to give the mapping program. The following table shows MAP option characters and their meanings.
MAP Option Character P C L O U Pins. Closed Adding logic to or removing logic from the CLB is not allowed. Locked Locking CLB pins. Open Adding logic to or removing logic from the CLB is allowed. Unlocked No locking on CLB pins. Function

X4646

Possible types of MAP parameters for FMAP are MAP=PUC, MAP=PLC, MAP=PLO, and MAP=PUO. The default parameter is PUO. If one of the open parameters is used (PLO or PUO), only the output signals must be specified. Note: Currently, only PUC and PUO are observed. PLC and PLO are translated into PUC and PUO, respectively. The FMAP symbol can be assigned to specific CLB locations using LOC attributes.

Usage
FMAPs are generally inferred with the logic portions of the HDL code. Xilinx suggests that you instantiate FMAPs only if you have a need to implicitly specify the logic mapping, or if you need to manually place or relationally place the logic.

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635

FMAP

VHDL Instantiation Template


-- Component Declaration for FMAP should be placed -- after architecture statement but before begin keyword component FMAP port (I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC; I4 : in STD_ULOGIC; O : in STD_ULOGIC); end component; -- Component Attribute specification for FMAP -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here

-- Component Instantiation for FMAP should be placed -- in architecture after the begin keyword FMAP_INSTANCE_NAME : FMAP port map (I1 => user_I1, I2 => user_I2, I3 => user_I3, I4 => user_I4, O => user_O);

Verilog Instantiation Template


FMAP FMAP_instance_name (.I1 (user_I1), .I2 (user_I2), .I3 (user_I3), .I4 (user_I4), .O (user_O));

Commonly Used Constraints


BEL BLKNM HBLKNM HU_SET LOC MAP U_SET

636

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FTC

FTC
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear
Architectures Supported
FTC Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

T C

FTC

FTC is a synchronous, resettable toggle flip-flop. The asynchronous clear (CLR) input, when High, overrides all other inputs and resets the data output (Q) Low. The Q output toggles, or changes state, when the toggle enable (T) input is High and CLR is Low during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 T X 0 1 C X X Outputs Q 0 No Chg Toggle

CLR

X3761

FDC
T C CLR X7830 XOR2 C CLR TQ D Q Q

FTC Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

Libraries Guide ISE 6.li

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637

FTC

FDC
T C CLR RLOC=X0Y0 X9321 XOR2 C CLR TQ D Q Q

FTC Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


FTCP
T C CLR PRE Q

D C

CLR Q

X7831 GND

FTC Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be instantiated or inferred.

VHDL Inference Code


architecture Behavioral of ftc is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (T) Q <= !Q; end

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FTC

VHDL Instantiation Template


-- Component Declaration for FTC should be placed -- after architecture statement but before begin keyword component FTC port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTC -- should be placed after architecture declaration but -- before the begin keyword

-- Enter attributes here

-- Component Instantiation for FTC should be placed -- in architecture after the begin keyword FTC_INSTANCE_NAME : FTC port map (Q => user_Q, C => user_C, CLR => user_CLR, T => user_T);

Verilog Instantiation Template


FTC FTC_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .T (user_T));

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, XBLKNM

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639

FTC

640

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Libraries Guide ISE 6.li

FTCE

FTCE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
Architectures Supported
FTCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

T CE C

FTCE

CLR

X3764

FTCE is a toggle flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the data output (Q) is reset Low. When CLR is Low and toggle enable (T) and clock enable (CE) are High, Q output toggles, or changes state, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 CE X 0 1 1 T X X 0 1 C X X X Outputs Q 0 No Chg No Chg Toggle

T CE C CLR XOR2

TQ D

FDCE
Q Q

CE C CLR

X7832

FTCE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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641

FTCE

T CE C CLR XOR2

TQ

FDCE
D CE C CLR X9322 Q Q

RLOC=X0Y0

FTCE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


FTCP
T CE C CLR AND2 C CLR Q PRE Q

X7833 GND

FTCE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Inference Code


architecture Behavioral of ftce is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; Q <= Q; end Behavioral;

642

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FTCE

Verilog Inference Code


always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (T) Q <= !Q; end

VHDL Instantiation Template


-- Component Declaration for FTCE should be placed -- after architecture statement but before begin keyword component FTCE port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CE : in STD_ULOGIC; CLR : in STD_ULOGIC; PRE : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTCE -- should be placed after architecture declaration but -- before the begin keyword

-- Enter attributes here

-- Component Instantiation for FTCE should be placed -- in architecture after the begin keyword FTCE_INSTANCE_NAME : FTCE port map (Q => user_Q, C => user_C, CE => user_CE, CLR => user_CLR, PRE => user_PRE, T => user_T);

Verilog Instantiation Template


FTCE FTCE_instance_name (.Q (user_Q), .C (user_C), .CE (user_CE), .CLR (user_CLR), .PRE (user_PRE), .T (user_T));

Commonly Used Constraints


BLKNM, HBLKNM, HU_SET, INIT, IOB, LOC, REG, RLOC, TIMEGRP, TNM, U_SET, and XBLKNM.

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643

FTCE

644

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FTCLE

FTCLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
Architectures Supported
FTCLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D L T CE C

FTCLE

CLR

X3769

FTCLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High and CLR is Low, clock enable (CE) is overridden and the data on data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 L X 1 1 0 0 0 CE X X X 0 1 1 T X X X X 0 1 D X 1 0 X X X C X X X Outputs Q 0 1 0 No Chg No Chg Toggle

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645

FTCLE

T XOR2

TQ

D0 D L D1 S0

M2_1
O MD

FDCE
D CE C CLR Q Q

CE OR2

L_CE

C CLR RLOC=R0C0 X8147

FTCLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

T XOR2 D L

TQ

M2_1
D0 D1 S0 O MD

FDCE
CE C CLR RLOC=X0Y0 X9323 OR2 L_CE D CE C CLR Q Q

FTCLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


VCC CE L AND3 AND3B2 OR2 GRD AND4B2 T AND3B2 OR4

FDC
D AND2 C C CLR CLR Q
X7561

FTCLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

646

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FTCLE

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftcle is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

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647

FTCLE

648

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FTCLEX

FTCLEX
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
Architectures Supported
FTCLEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D L T CE C

FTCLEX

CLR X7601

FTCLEX is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High, CLR is Low, and CE is High, the data on data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs CLR 1 0 0 0 0 0 L X 1 1 0 0 0 CE X 1 1 0 1 1 T X X X X 0 1 D X 1 0 X X X C X X X Outputs Q 0 1 0 No Chg No Chg Toggle

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649

FTCLEX

TQ T XOR2 D L CE C CLR X6995 D0 D1 S0 M2_1 0 MD FDCE D CE C CLR Q Q

FTCLEX Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

T XOR2 D L

TQ

M2_1
D0 D1 S0 O MD

FDCE
CE D CE C CLR RLOC=X0Y0 X9324 C CLR Q Q

FTCLEX Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftclex is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event and C='1') then if (CE='1') then if (L='1') then Q <= D; elsif (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

650

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FTCLEX

Verilog Inference Code


always @(posedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

651

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FTCLEX

652

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Libraries Guide ISE 6.li

FTCP

FTCP
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset
Architectures Supported
FTCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

No No No Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

FTCP
Q

FTCP is a toggle flip-flop with toggle enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the toggle enable input (T) is High and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 PRE X 1 0 0 T X X 0 1 C X X X Outputs Q 0 1 No Chg Toggle

CLR X4392

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Inference Code


architecture Behavioral of ftcp is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then

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653

FTCP

if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (T) Q <= !Q; end

VHDL Instantiation Template


-- Component Declaration for FTCP should be placed -- after architecture statement but before begin keyword component FTCP port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; PRE : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTCP -- should be placed after architecture declaration but -- before the begin keyword

-- Enter attributes here

-- Component Instantiation for FTCP should be placed -- in architecture after the begin keyword FTCP_INSTANCE_NAME : FTCP port map (Q => user_Q, C => user_C, CLR => user_CLR, PRE => user_PRE, T => user_T);

654

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FTCP

Verilog Instantiation Template


FTCP FTCP_instance_name (.Q (user_Q), .C (user_C), .CLR (user_CLR), .PRE (user_PRE), .T (user_T));

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET XBLKNM

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655

FTCP

656

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Libraries Guide ISE 6.li

FTCPE

FTCPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset
Architectures Supported
FTCPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

T CE C

FTCPE
Q

CLR X4393

FTCPE is a toggle flip-flop with toggle and clock enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the toggle enable input (T) and the clock enable input (CE) are High and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. Clock transitions are ignored when CE is Low. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0
PRE T CE C CLR AND2 C CLR Q X7681 T

Outputs T X X X 0 1 C X X X X Q 0 1 No Chg No Chg Toggle

PRE X 1 0 0 0

CE X X 0 1 1

FTCP
PRE Q Q

FTCPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

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657

FTCPE

VHDL Inference Code


architecture Behavioral of ftcpe is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (CE) if (T) Q <= !Q; end

658

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Libraries Guide ISE 6.li

FTCPLE

FTCPLE
Loadable Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear and Preset
Architectures Supported
FTCPLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

PRE

D L T CE C

FTCPLE

CLR

X4394

FTCPLE is a loadable toggle flip-flop with toggle and clock enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the load input (L) is High, the clock enable input (CE) is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enable input (T) and the clock enable input (CE) are High and CLR, PRE, and L are Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. Clock transitions are ignored when CE is Low. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 0 0 PRE X 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 T X X X X X 0 1 C X X X X D X X 0 1 X X X Outputs Q 0 1 0 1 No Chg No Chg Toggle

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659

FTCPLE

VCC

CE AND2 L OR2 AND3B2

GND AND4B2 T

FDCP
AND3B2 PRE Q

D C

D AND2 PRE C CLR

OR4

CLR

X7845

FTCPLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftcple is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

660

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FTCPLE

Verilog Inference Code


always @(posedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

Libraries Guide ISE 6.li

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661

FTCPLE

662

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Libraries Guide ISE 6.li

FTDCE

FTDCE
Dual Edge Triggered Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
Architectures Supported
FTDCE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

T CE C

FTDCE

CLR

X9751

FTDCE is a dual edge triggered toggle flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the data output (Q) is reset Low. When CLR is Low and toggle enable (T) and clock enable (CE) are High, Q output toggles, or changes state, during the Low-to-High and High-to-Low clock (C) transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 CE X 0 1 1 1 T X X 0 1 1 C X X X Outputs Q 0 No Chg No Chg Toggle Toggle

FTCP
T CE C CLR AND2 C CLR Q PRE Q

X7833 GND

FTDCE Implementation CoolRunner-II

Libraries Guide ISE 6.li

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663

FTDCE

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftdce is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event) then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (CE) if (T) Q <= !Q; end

664

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Libraries Guide ISE 6.li

FTDCLE

FTDCLE
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
Architectures Supported
FTDCLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D L T CE C

FTDCLE

CLR

X9752

FTDCLE is a dual edge triggered toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High and CLR is Low, clock enable (CE) is overridden and the data on data input (D) is loaded into the flip-flop during the Low-to-High and High-to-Low clock (C) transitions. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Inputs CLR 1 0 0 0 0 0 0 0 0 L X 1 1 1 1 0 0 0 0 CE X X X X X 0 1 1 1 T X X X X X X 0 1 1 D X 1 1 0 0 X X X X C X X X

Outputs Q 0 1 1 0 0 No Chg No Chg Toggle Toggle

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665

FTDCLE

VCC

CE L AND3 AND3B2 OR2 GRD AND4B2 T AND3B2 OR4

FDDC
D AND2 C C CLR CLR Q
X9753

FTDCLE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftdcle is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event) then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D;

666

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FTDCLE

else if (CE) if (T) Q <= !Q; end

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667

FTDCLE

668

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Libraries Guide ISE 6.li

FTDCLEX

FTDCLEX
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Clear
Architectures Supported
FTCLEX Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

D L T CE C

FTDCLEX

CLR
X9754

FTDCLEX is a dual edge triggered toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. When the asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When load enable input (L) is High, CLR is Low, and CE is High, the data on data input (D) is loaded into the flipflop during the Low-to-High and High-to-Low clock (C) transitions. When toggle enable (T) and CE are High and L and CLR are Low, output Q toggles, or changes state, during the Low- to-High and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied.
Inputs CLR 1 0 0 0 0 0 0 0 0 L X 1 1 1 1 0 0 0 0 CE X 1 1 1 1 0 1 1 1 T X X X X X X 0 1 1 D X 1 1 0 0 X X X X C X X X Outputs Q 0 1 1 0 0 No Chg No Chg Toggle Toggle

Usage
For HDL, this design element is inferred rather than instantiated.

Libraries Guide ISE 6.li

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669

FTDCLEX

VHDL Inference Code


architecture Behavioral of ftdclex is begin process (C, CLR) begin if (CLR='1') then Q <= '0'; elsif (C'event) then if (CE='1') then if (L='1') then Q <= D; elsif (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or negedge C or posedge CLR) begin if (CLR) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

670

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FTDCP

FTDCP
Toggle Flip-Flop with Toggle Enable and Asynchronous Clear and Preset
Architectures Supported
FTDCP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

PRE

FTDCP
Q

FTDCP is a toggle flip-flop with toggle enable and asynchronous clear and preset. When the asynchronous clear (CLR) input is High, all other inputs are ignored and the output (Q) is reset Low. When the asynchronous preset (PRE) is High and CLR is Low, all other inputs are ignored and Q is set High. When the toggle enable input (T) is High and CLR and PRE are Low, output Q toggles, or changes state, during the Low-to-High and High-to-Low clock (C) transition. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.
Inputs CLR 1 0 0 0 0 PRE X 1 0 0 0 T X X 0 1 1 C X X X Outputs Q 0 1 No Chg Toggle Toggle

CLR
X9777

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671

FTDCP

FTDCP
T CE C CLR AND2 C CLR Q PRE Q

GND

X9778

FTDCP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftdcp is begin process (C, CLR, PRE) begin if (CLR='1') then Q <= '0'; elsif (PRE='1') then Q <= '1'; elsif (C'event) then if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or negedge C or posedge CLR or posedge PRE) begin if (CLR) Q <= 0; else if (PRE) Q <= 1; else if (T) Q <= !Q; end

672

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Libraries Guide ISE 6.li

FTDRSE

FTDRSE
Dual Edge Triggered Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
Architectures Supported
FTDRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X No

T CE C

FTDRSE

FTDRSE is a dual edge triggered toggle flip-flop with toggle and clock enable and synchronous reset and set. When the synchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When the synchronous set input (S) is High and R is Low, clock enable input (CE) is overridden and output Q is set High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High and R and S are Low, output Q toggles, or changes state, during the Low-to-High and High-to-Low clock transitions. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

X9755

Inputs R 1 1 0 0 0 0 0 0 S X X 1 1 0 0 0 0 CE X X X X 0 1 1 1 T X X X X X 0 1 1 C X X

Outputs Q 0 0 1 1 No Chg No Chg Toggle Toggle

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673

FTDRSE

VCC

CE AND2 T AND2B1

AND3B1 S OR4

FDD
AND3B1 R C AND2B1 C
X9756

FTDRSE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftdrse is begin process (C) begin if (C'event) then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE)

674

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FTDRSE

if (T) Q <= !Q; end

Libraries Guide ISE 6.li

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675

FTDRSE

676

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Libraries Guide ISE 6.li

FTDRSLE

FTDRSLE
Dual Edge Triggered Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
Architectures Supported
FTDRSLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D L T CE C

FTDRSLE

X9757

FTDRSLE is a dual edge triggered toggle/loadable flip-flop with toggle and clock enable and synchronous reset and set. The synchronous reset input (R), when High, overrides all other inputs and resets the data output (Q) Low. (Reset has precedence over Set.) When R is Low and synchronous set input (S) is High, the clock enable input (CE) is overridden and output Q is set High. When R and S are Low and load enable input (L) is High, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High and High-to-Low clock transitions. When R, S, and L are Low and CE is High, output Q toggles, or changes state, during the Low-toHigh and High-to-Low clock transitions. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net.

Inputs R 1 1 0 0 0 0 0 0 0 0 0 0 S 0 0 1 1 0 0 0 0 0 0 0 0 L X X X X 1 1 1 1 0 0 0 0 CE X X X X X X X X 0 1 1 1 T X X X X X X X X X 0 1 1 D X X X X 1 1 0 0 X X X X C X X

Outputs Q 0 0 1 1 1 1 0 0 No Chg No Chg Toggle Toggle

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677

FTDRSLE

VCC

CE AND2 L D OR2 AND3B2 C GND T AND4B2 S AND2B1 OR5 Q

FDD
Q

AND4B2 D R C
X9758

AND2

FTDRSLE Implementation CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftdrsle is begin process (C) begin if (C'event) then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

678

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Libraries Guide ISE 6.li

FTDRSLE

Verilog Inference Code


always @(posedge C or negedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

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679

FTDRSLE

680

www.xilinx.com 1-800-255-7778

Libraries Guide ISE 6.li

FTP

FTP
Toggle Flip-Flop with Toggle Enable and Asynchronous Preset
Architectures Supported
FTP Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

T C

FTP

FTP is a toggle flip-flop with toggle enable and asynchronous preset. When the asynchronous preset (PRE) input is High, all other inputs are ignored and output Q is set High. When toggle-enable input (T) is High and PRE is Low, output Q toggles, or changes state, during the Low-to-High clock (C) transition. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_VIRTEX, STARTUP_SPARTAN3, or the STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 T X 0 1 C X X Outputs Q 1 No Chg Toggle

X3762

PRE TQ XOR2 C

FDP
PRE Q

T C

RLOC=R0C0 X6371

FTP Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

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681

FTP

PRE TQ XOR2 C D

FDP
PRE Q Q

T C

RLOC=X0Y0

X9325

FTP Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


PRE

FTCP
PRE T Q Q

T C

C CLR

GND

X7680

FTP Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element can be inferred or instantiated.

VHDL Inference Code


architecture Behavioral of ftp is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (T='1') then Q <= not Q; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (T) Q <= !Q; end

682

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Libraries Guide ISE 6.li

FTP

VHDL Instantiation Template


-- Component Declaration for FTP should be placed -- after architecture statement but before begin keyword component FTP port (Q : out STD_ULOGIC; C : in STD_ULOGIC; PRE : in STD_ULOGIC; T : in STD_ULOGIC); end component; -- Component Attribute specification for FTP -- should be placed after architecture declaration but -- before the begin keyword

-- Enter attributes here

-- Component Instantiation for FTP should be placed -- in architecture after the begin keyword FTP_INSTANCE_NAME : port map (Q => C => PRE => T => FTP user_Q, user_C, user_PRE, user_T);

Verilog Instantiation Template


FTP FTP_instance_name (.Q (user_Q), .C (user_C), .PRE (user_PRE), .T (user_T));

Commonly Used Constraints


BLKNM HBLKNM HU_SET INIT IOB LOC REG RLOC TIMEGRP TNM U_SET, XBLKNM

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683

FTP

684

www.xilinx.com 1-800-255-7778

Libraries Guide ISE 6.li

FTPE

FTPE
Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Preset
Architectures Supported
FTPE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

T CE C

FTPE

FTPE is a toggle flip-flop with toggle and clock enable and asynchronous preset. When the asynchronous preset (PRE) input is High, all other inputs are ignored and output Q is set High. When the toggle enable input (T) is High, clock enable (CE) is High, and PRE is Low, output Q toggles, or changes state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 CE X 0 1 1 T X X 0 1 C X X X Outputs Q 1 No Chg No Chg Toggle

X3765

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685

FTPE

PRE TQ XOR2 CE C

FDPE
D PRE Q Q

CE C RLOC=R0C0 X8694

FTPE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E


FDPE
TQ XOR2 PRE D CE C RLOC=X0Y0 X9326 Q Q

PRE

T CE C

FTPE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


PRE T CE C AND2 C CLR Q T

FTCP
PRE Q Q

GND

X7683

FTPE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftpe is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

686

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Libraries Guide ISE 6.li

FTPE

Verilog Inference Code


always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (CE) if (T) Q <= !Q; end

687

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Libraries Guide ISE 6.li

FTPE

688

www.xilinx.com 1-800-255-7778

Libraries Guide ISE 6.li

FTPLE

FTPLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Asynchronous Preset
Architectures Supported
FTPLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
PRE

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D L T CE C

FTPLE

FTPLE is a toggle/loadable flip-flop with toggle and clock enable and asynchronous preset. When the asynchronous preset input (PRE) is High, all other inputs are ignored and output Q is set High. When the load enable input (L) is High and PRE is Low, the clock enable (CE) is overridden and the data (D) is loaded into the flip-flop during the Low-to-High clock transition. When L and PRE are Low and toggle-enable input (T) and CE are High, output Q toggles, or changes state, during the Low-toHigh clock transition. When CE is Low, clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously cleared, output Low, when power is applied. The power-on condition can be simulated by applying a High-level pulse on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously preset to output High, when power is applied. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs PRE 1 0 0 0 0 0 L X 1 1 0 0 0 CE X X X 0 1 1 T X X X X 0 1 D X 1 0 X X X C X X X Outputs Q 1 1 0 No Chg No Chg Toggle

X3770

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689

FTPLE

TQ T XOR2 D L PRE D0 D1 S0 M2_1 O MD

FDPE
D OR2 CE C RLOC=R0C0 X6372 PRE Q Q

CE C

FTPLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

T XOR2 D L

TQ

M2_1
D0 D1 S0 O MD

PRE D OR2

FDPE
PRE Q Q

CE C

CE C RLOC=X0Y0 X9327

FTPLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


VCC

CE AND2 L OR2 GND AND4B2 T AND3B2

FDP
AND3B2 PRE Q

D C

D AND2 PRE C

OR4

X7846

FTPLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

690

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Libraries Guide ISE 6.li

FTPLE

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftple is begin process (C, PRE) begin if (PRE='1') then Q <= '1'; elsif (C'event and C='1') then if (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C or posedge PRE) begin if (PRE) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

Libraries Guide ISE 6.li

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691

FTPLE

692

www.xilinx.com 1-800-255-7778

Libraries Guide ISE 6.li

FTRSE

FTRSE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
Architectures Supported
FTRSE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

T CE C

FTRSE

FTRSE is a toggle flip-flop with toggle and clock enable and synchronous reset and set. When the synchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When the synchronous set input (S) is High and R is Low, clock enable input (CE) is overridden and output Q is set High. (Reset has precedence over Set.) When toggle enable input (T) and CE are High and R and S are Low, output Q toggles, or changes state, during the Low-to-High clock transition. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 S X 1 0 0 0 CE X X 0 1 1 T X X X 0 1 C X X Outputs Q 0 1 No Chg No Chg Toggle

X3768

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693

FTRSE

TQ T XOR2 S OR2 D CE C R RLOC=R0C0 X7658 OR2 CE_S CE C R Q Q D_S

FDRE

FTRSE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

T S XOR2

TQ D_S OR2

FDRE
D Q Q CE_S

CE C R OR2

CE C R

RLOC=X0Y0 X9328

FTRSE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X

VCC

CE AND2 T AND2B1

AND3B1 S OR4

FD
AND3B1 R C AND2B1 C
X7847

FTRSE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

694

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Libraries Guide ISE 6.li

FTRSE

VHDL Inference Code


architecture Behavioral of ftrse is begin process (C) begin if (C'event and C='1') then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (CE) if (T) Q <= !Q; end

Libraries Guide ISE 6.li

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695

FTRSE

696

www.xilinx.com 1-800-255-7778

Libraries Guide ISE 6.li

FTRSLE

FTRSLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Reset and Set
Architectures Supported
FTRSLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D L T CE C

FTRSLE

X3773

FTRSLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous reset and set. The synchronous reset input (R), when High, overrides all other inputs and resets the data output (Q) Low. (Reset has precedence over Set.) When R is Low and synchronous set input (S) is High, the clock enable input (CE) is overridden and output Q is set High. When R and S are Low and load enable input (L) is High, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-toHigh clock transition. When R, S, and L are Low, CE is High and T is High, output Q toggles, or changes state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.
Inputs R 1 0 0 0 0 0 0 S 0 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 T X X X X X 0 1 D X X 1 0 X X X C X X Outputs Q 0 1 1 0 No Chg No Chg Toggle

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697

FTRSLE

TQ T XOR2 D L S OR2 CE_S_L CE OR3 C D0 D1 S0 MD_S M2_1 O MD

FDRE
Q D CE C Q

R RLOC=R0C0 X7641

FTRSLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

T XOR2 D L S

TQ

M2_1
D0 D1 S0 O MD

MD_S OR2

FDRE
CE_S_L CE OR3 C R RLOC=X0Y0 X9329 D CE C R Q Q

FTRSLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


VCC

CE AND2 L D OR2 AND3B2 C GND T AND4B2 S AND2B1 OR5 Q

FD
Q

AND4B2 D R C AND2
X7848

FTRSLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

698

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Libraries Guide ISE 6.li

FTRSLE

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftrsle is begin process (C) begin if (C'event and C='1') then if (R='1') then Q <= '0'; elsif (S='1') then Q <= '1'; elsif (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C) begin if (R) Q <= 0; else if (S) Q <= 1; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

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699

FTRSLE

700

www.xilinx.com 1-800-255-7778

Libraries Guide ISE 6.li

FTSRE

FTSRE
Toggle Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset
Architectures Supported
FTSRE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

T CE C

FTSRE

X3767

FTSRE is a toggle flip-flop with toggle and clock enable and synchronous set and reset. The synchronous set input, when High, overrides all other inputs and sets data output (Q) High. (Set has precedence over Reset.) When synchronous reset input (R) is High and S is Low, clock enable input (CE) is overridden and output Q is reset Low. When toggle enable input (T) and CE are High and S and R are Low, output Q toggles, or changes state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored. The flip-flop is asynchronously cleared, output Low, when power is applied. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and VirtexII Pro X simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FTSRE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 0 R X 1 0 0 0 CE X X 0 1 1 T X X X 0 1 C X X Outputs Q 1 0 No Chg No Chg Toggle

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701

FTSRE

TQ T XOR2 R S AND2B1 D_R

FDSE
S D Q Q

CE C OR2

CE_R CE C RLOC=R0C0

X7643

FTSRE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

T R S XOR2

TQ D_R AND2B1

FDSE
D S Q Q

CE C OR2

CE_R

CE C RLOC=X0Y0 X9330

FTSRE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


VCC

CE AND2

R AND3B2

AND4B2

FD
D AND3B2 S C
X7849

OR4

FTSRE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

Usage
For HDL, this design element is inferred rather than instantiated.

702

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FTSRE

VHDL Inference Code


architecture Behavioral of ftsre is begin process (C) begin if (C'event and C='1') then if (S='1') then Q <= '1'; elsif (R='1') then Q <= '0'; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C) begin if (S) Q <= 1; else if (R) Q <= 0; else if (CE) if (T) Q <= !Q; end

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703

FTSRE

704

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FTSRLE

FTSRLE
Toggle/Loadable Flip-Flop with Toggle and Clock Enable and Synchronous Set and Reset
Architectures Supported
FTSRLE Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II
S FTSRLE

Macro Macro Macro Macro Macro Macro

Virtex-II, Virtex-II Pro, Virtex-II Pro X Macro

D L T CE C

X3772

FTSRLE is a toggle/loadable flip-flop with toggle and clock enable and synchronous set and reset. The synchronous set input (S), when High, overrides all other inputs and sets data output (Q) High. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, clock enable input (CE) is overridden and output Q is reset Low. When load enable input (L) is High and S and R are Low, CE is overridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enable input (T) and CE are High and S, R, and L are Low, output Q toggles, or changes state, during the Low-to- High clock transition. When CE is Low, clock transitions are ignored. For XC9500/XV/XL, CoolRunner XPLA3, and CoolRunner-II, the flip-flop is asynchronously preset when a High-level pulse is applied on the PRLD global net. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is asynchronously cleared, output Low, when global set/reset (GSR) is active. The GSR active level defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. FTSRLE will set when GSR is active. For Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, the flip-flop is preset to active high when GSR is active.
Inputs S 1 0 0 0 0 0 0 R X 1 0 0 0 0 0 L X X 1 1 0 0 0 CE X X X X 0 1 1 T X X X X X 0 1 D X X 1 0 X X X C X X Outputs Q 1 0 1 0 No Chg No Chg Toggle

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705

FTSRLE

T
XOR2

TQ

M2_1
D0 D1 S0 O MD

D L R

MD_S AND2B1

FDSE
D CE C Q

CE_R_L

CE
OR3

RLOC=R0C0
X7642

FTSRLE Implementation Spartan-II, Spartan-IIE, Virtex, Virtex-E

T XOR2 D L R S

TQ

M2_1
D0 D1 S0 O MD

MD_S AND2B1

FDSE
D S Q Q

CE_R_L CE C OR3

CE C RLOC=R0C0 X9331

FTSRLE Implementation Spartan-3, Virtex-II, Virtex-II Pro, Virtex-II Pro X


VCC

CE AND2

R AND4B3 T L OR2 GND

AND5B3

FD
D AND4B3 D C Q
X7850

AND3B1 S C

OR5

FTSRLE Implementation XC9500/XV/XL, CoolRunner XPLA3, CoolRunner-II

706

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FTSRLE

Usage
For HDL, this design element is inferred rather than instantiated.

VHDL Inference Code


architecture Behavioral of ftsrle is begin process (C) begin if (C'event and C='1') then if (S='1') then Q <= '1'; elsif (R='1') then Q <= '0'; elsif (L='1') then Q <= D; elsif (CE='1') then if (T='1') then Q <= not Q; end if; end if; end if; end process; end Behavioral;

Verilog Inference Code


always @(posedge C) begin if (S) Q <= 1; else if (R) Q <= 0; else if (L) Q <= D; else if (CE) if (T) Q <= !Q; end

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707

FTSRLE

708

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GND

GND
Ground-Connection Signal Tag
Architectures Supported
GND Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II Primitive Primitive Primitive Primitive Primitive Primitive

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive

The GND signal tag, or parameter, forces a net or input function to a Low logic level. A net tied to GND cannot have any other source.
X3858

When the logic-trimming software or fitter encounters a net or input function tied to GND, it removes any logic that is disabled by the GND signal. The GND signal is only implemented when the disabled logic cannot be removed.

Usage
For HDL, this design element can be instantiated or inferred.

VHDL Inference Code:


gnd_signal <= '0';

Verilog Inference Code:


assign gnd_signal = 0;

VHDL Instantiation Template


-- Component Declaration for GND should be placed -- after architecture statement but before begin keyword component GND port (G : out STD_ULOGIC); end component; -- Component Attribute specification for GND -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here

-- Component Instantiation for GND should be placed -- in architecture after the begin keyword

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709

GND

GND_INSTANCE_NAME : GND port map (G => user_G);

Verilog Instantiation Template


GND GND_instance_name (.G (user_G));

Commonly Used Constraints


None

710

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GT_AURORA_n

GT_AURORA_n
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_AURORA_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

*Supported for Virtex-II Pro but not for Virtex-II or Virtex-II Pro X.

This Xilinx protocol gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributesand their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.

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711

GT_AURORA_n

GT_AURORA_1
BREFCLK BREFCLK2 CHBONDI(3:0) CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(0:0) TXCHARDISPMODE(0:0) TXCHARDISPVAL(0:0) TXCHARISK(0:0) TXDATA(7:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9888

CHBONDDONE CHBONDO(3:0) CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(0:0) RXCHARISK(0:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(7:0) RXDISPERR(0:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(0:0) RXREALIGN RXRECCLK RXRUNDISP(0:0) TXBUFERR TXKERR(0:0) TXN TXP TXRUNDISP(0:0)

712

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GT_AURORA_n

GT_AURORA_2
BREFCLK BREFCLK2 CHBONDI(3:0) CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(1:0) TXCHARDISPMODE(1:0) TXCHARDISPVAL(1:0) TXCHARISK(1:0) TXDATA(15:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9889

CHBONDDONE CHBONDO(3:0) CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(1:0) RXCHARISK(1:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(15:0) RXDISPERR(1:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(1:0) RXREALIGN RXRECCLK RXRUNDISP(1:0) TXBUFERR TXKERR(1:0) TXN TXP TXRUNDISP(1:0)

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713

GT_AURORA_n

GT_AURORA_4
BREFCLK BREFCLK2 CHBONDI(3:0) CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(3:0) TXCHARDISPMODE(3:0) TXCHARDISPVAL(3:0) TXCHARISK(3:0) TXDATA(31:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9890

CHBONDDONE CHBONDO(3:0) CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(3:0) RXCHARISK(3:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(31:0) RXDISPERR(3:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(3:0) RXREALIGN RXRECCLK RXRUNDISP(3:0) TXBUFERR TXKERR(3:0) TXN TXP TXRUNDISP(3:0)

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates


GT_AURORA_1 VHDL Code
-- Component Attribute specification for GT_AURORA_1 -- should be placed after architecture declaration but -- before the begin keyword

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GT_AURORA_n

component GT_AURORA_1 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00111110111"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111111"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000101"; boolean := TRUE; bit_vector := "0011111010"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 1; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 1;

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715

GT_AURORA_n

TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

: integer := 500; : integer := 0);

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);

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GT_AURORA_n

end component; -- Component Attribute specification for GT_AURORA_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_AURORA_1 should be placed -- in architecture after the begin keyword GT_AURORA_1_INSTANCE_NAME : GT_AURORA_1 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value, CRC_END_OF_PKT => string_value, CRC_FORMAT => string_value, CRC_START_OF_PKT => string_value, DEC_MCOMMA_DETECT => boolean_value, DEC_PCOMMA_DETECT => boolean_value, DEC_VALID_COMMA_ONLY => boolean_value, MCOMMA_10B_VALUE => bit_value, MCOMMA_DETECT => boolean_value, PCOMMA_10B_VALUE => bit_value, PCOMMA_DETECT => boolean_value, REF_CLK_V_SEL => integer_value, RX_BUFFER_USE => boolean_value, RX_CRC_USE => boolean_value,

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717

GT_AURORA_n

RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B

=> => => => => => => => => => => => =>

integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B,

718

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GT_AURORA_n

TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

=> => => => => => => => => =>

user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_AURORA_2 VHDL Code


-- Component Attribute specification for GT_AURORA_2 -- should be placed after architecture declaration but -- before the begin keyword component GT_AURORA_2 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00111110111"; bit_vector := "00111110111"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "1111111111"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000101";

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719

GT_AURORA_n

MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN

: : : : : : : : : : : : : : : : : : :

boolean := bit_vector boolean := integer := boolean := boolean := integer := boolean := integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=

TRUE; := "0011111010"; TRUE; 0; TRUE; FALSE; 2; TRUE; 1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 2; 500; 0);

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;

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RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;

: : : : : : : : : : : : : : : :

in in in in in in in in in in in in in in in in

std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(15 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);

-- Component Attribute specification for GT_AURORA_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_AURORA_2 should be placed -- in architecture after the begin keyword GT_AURORA_2_INSTANCE_NAME : GT_AURORA_2 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value,

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CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)

=> => => => => => => => => => => => => => => => => => => => => => => => =>

user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI,

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CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

=> => => => => => => => => => => => => => => => => => => => => => => => => => =>

user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_AURORA_4 VHDL Code


-- Component Attribute specification for GT_AURORA_4 -- should be placed after architecture declaration but -- before the begin keyword component GT_AURORA_4 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2

: : : : : : : : : : : : : : : : : : : : :

boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00101111100"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00111110111"; bit_vector := "00111110111";

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CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

bit_vector := "00111110111"; bit_vector := "00111110111"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 4; boolean := TRUE; bit_vector := "1111111111"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000101"; boolean := TRUE; bit_vector := "0011111010"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 4; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 4; integer := 500; integer := 0);

: : : : : : : : : : : : : : : : : : :

out out out out out out out out out out out out out out out out out out out

std_ulogic; std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(2 downto 0); std_ulogic; std_ulogic; std_logic_vector(31 downto 0); std_logic_vector(3 downto 0); std_logic_vector(1 downto 0); std_logic_vector(3 downto 0); std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_ulogic; std_logic_vector(3 downto 0);

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TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(3 downto 0); in std_logic_vector(31 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic);

-- Component Attribute specification for GT_AURORA_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_AURORA_4 should be placed -- in architecture after the begin keyword GT_AURORA_4_INSTANCE_NAME : GT_AURORA_4 -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value,

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CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)

=> => => => => => => =>

user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT,

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RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

Verilog Instantiation Templates


GT_AURORA_1 Verilog Code
GT_AURORA_1 GT_AURORA_1_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC),

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.RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000;

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defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam

user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111111; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000101; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 1; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 1; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_AURORA_2 Verilog Code


GT_AURORA_2 GT_AURORA_2_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT),

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.RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000;

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defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam

user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111111; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000101; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_AURORA_4 Verilog Code


GT_AURORA_4 GT_AURORA_4_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET),

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.RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00101111100; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000;

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GT_AURORA_n

defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam

user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00111110111; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 4; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111111; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000101; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111010; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 4; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 4; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

Commonly Used Constraints


None

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GT_CUSTOM

GT_CUSTOM
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_CUSTOM Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No Primitive* No No No

*Supported for Virtex-II Pro but not for Virtex-II or Virtex-II Pro X.

This gigabit transceiver is fully customizable. You can set attributes for the primitives. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributesand their default attribute values. The following figure lists the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.

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GT_CUSTOM

GT_CUSTOM
BREFCLK BREFCLK2 CHBONDI(3:0) CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(3:0) TXCHARDISPMODE(3:0) TXCHARDISPVAL(3:0) TXCHARISK(3:0) TXDATA(31:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9891

CHBONDDONE CHBONDO(3:0) CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(3:0) RXCHARISK(3:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(31:0) RXDISPERR(3:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(3:0) RXREALIGN RXRECCLK RXRUNDISP(3:0) TXBUFERR TXKERR(3:0) TXN TXP TXRUNDISP(3:0)

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GT_CUSTOM

Usage
This design element is instantiated rather than inferred in the design code.

VHDL Instantiation Templates


GT_CUSTOM VHDL Code
-- Component Attribute specification for GT_CUSTOM -- should be placed after architecture declaration but -- before the begin keyword component GT_CUSTOM -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

boolean := FALSE; integer := 16; string := "OFF"; integer := 8; boolean := FALSE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 8; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "USER_MODE"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0;

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RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK

: : : : : : : : : : : : : : :

boolean := boolean := integer := boolean := integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=

TRUE; FALSE; 2; TRUE; 1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 2; 500; 0);

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_logic_vector(3 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;

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GT_CUSTOM

RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;

: : : : : : : : : : : :

in in in in in in in in in in in in

std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);

-- Component Attribute specification for GT_CUSTOM -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_CUSTOM should be placed -- in architecture after the begin keyword GT_CUSTOM_INSTANCE_NAME : GT_CUSTOM -- synopsys translate_off generic map ( ALIGN_COMMA_MSB => boolean_value, CHAN_BOND_LIMIT => integer_value, CHAN_BOND_MODE => string_value, CHAN_BOND_OFFSET => integer_value, CHAN_BOND_ONE_SHOT => boolean_value, CHAN_BOND_SEQ_1_1 => bit_value, CHAN_BOND_SEQ_1_2 => bit_value, CHAN_BOND_SEQ_1_3 => bit_value, CHAN_BOND_SEQ_1_4 => bit_value, CHAN_BOND_SEQ_2_1 => bit_value, CHAN_BOND_SEQ_2_2 => bit_value, CHAN_BOND_SEQ_2_3 => bit_value, CHAN_BOND_SEQ_2_4 => bit_value, CHAN_BOND_SEQ_2_USE => boolean_value, CHAN_BOND_SEQ_LEN => integer_value, CHAN_BOND_WAIT => integer_value, CLK_COR_INSERT_IDLE_FLAG => boolean_value, CLK_COR_KEEP_IDLE => boolean_value, CLK_COR_REPEAT_WAIT => integer_value, CLK_COR_SEQ_1_1 => bit_value, CLK_COR_SEQ_1_2 => bit_value, CLK_COR_SEQ_1_3 => bit_value, CLK_COR_SEQ_1_4 => bit_value, CLK_COR_SEQ_2_1 => bit_value, CLK_COR_SEQ_2_2 => bit_value, CLK_COR_SEQ_2_3 => bit_value, CLK_COR_SEQ_2_4 => bit_value, CLK_COR_SEQ_2_USE => boolean_value, CLK_COR_SEQ_LEN => integer_value, CLK_CORRECT_USE => boolean_value, COMMA_10B_MASK => bit_value,

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CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CHBONDDONE CHBONDO CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CHBONDI CONFIGENABLE CONFIGIN ENCHANSYNC ENMCOMMAALIGN

=> => => => => => => => => => => => => => => => => => => => => => => => => =>

string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

user_CHBONDDONE, user_CHBONDO, user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CHBONDI, user_CONFIGENABLE, user_CONFIGIN, user_ENCHANSYNC, user_ENMCOMMAALIGN,

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GT_CUSTOM

ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

=> => => => => => => => => => => => => => => => => => => => => => =>

user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

Verilog Instantiation Templates


GT_CUSTOM Verilog Code
GT_CUSTOM GT_CUSTOM_name( .CHBONDDONE (user_CHBONDDONE), .CHBONDO (user_CHBONDO), .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CHBONDI (user_CHBONDI), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN),

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.ENCHANSYNC (user_ENCHANSYNC), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 16; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 8; user_instance_name.CHAN_BOND_ONE_SHOT = "FALSE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 8; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 1; user_instance_name.CLK_CORRECT_USE = "TRUE"; user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7";

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GT_CUSTOM

defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam

user_instance_name.CRC_FORMAT = "USER_MODE"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 2; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 2; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

Commonly Used Constraints


None

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743

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GT_ETHERNET_n

GT_ETHERNET_n
Gigabit Transceiver for High-Speed I/O
Architectures Supported
GT_ETHERNET_n Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E XC9500, XC9500XV, XC9500XL CoolRunner XPLA3 CoolRunner-II No No No No No No

Virtex-II, Virtex-II Pro, Virtex-II Pro X Primitive*

*Supported for Virtex-II Pro but not for Virtex-II or Virtex-II Pro X.

This Ethernet gigabit transceiver supports 1, 2, and 4-byte data paths. The letter n represents number of bytes of the data path. Valid values are 1, 2 or 4. You can also set attributes for the primitives. See the RocketIO Transceiver User Guide for a description of these attributesand their default attribute values. The following figures list the input and output ports for all values of n. For a description of each of the ports, see the RocketIO Transceiver User Guide.

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GT_ETHERNET_n

GT_ETHERNET_1
BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(0:0) TXCHARDISPMODE(0:0) TXCHARDISPVAL(0:0) TXCHARISK(0:0) TXDATA(7:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9892

CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(0:0) RXCHARISK(0:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(7:0) RXDISPERR(0:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(0:0) RXREALIGN RXRECCLK RXRUNDISP(0:0) TXBUFERR TXKERR(0:0) TXN TXP TXRUNDISP(0:0)

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GT_ETHERNET_n

GT_ETHERNET_2
BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(1:0) TXCHARDISPMODE(1:0) TXCHARDISPVAL(1:0) TXCHARISK(1:0) TXDATA(15:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2
X9893

CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(1:0) RXCHARISK(1:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(15:0) RXDISPERR(1:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(1:0) RXREALIGN RXRECCLK RXRUNDISP(1:0) TXBUFERR TXKERR(1:0) TXN TXP TXRUNDISP(1:0)

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GT_ETHERNET_n

GT_ETHERNET_4
BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK(1:0) POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B(3:0) TXCHARDISPMODE(3:0) TXCHARDISPVAL(3:0) TXCHARISK(3:0) TXDATA(31:0) TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 CONFIGOUT RXBUFSTATUS(1:0) RXCHARISCOMMA(3:0) RXCHARISK(3:0) RXCHECKINGCRC RXCLKCORCNT(2:0) RXCOMMADET RXCRCERR RXDATA(31:0) RXDISPERR(3:0) RXLOSSOFSYNC(1:0) RXNOTINTABLE(3:0) RXREALIGN RXRECCLK RXRUNDISP(3:0) TXBUFERR TXKERR(3:0) TXN TXP TXRUNDISP(3:0)

X9894

Usage
This design element is instantiated rather than inferred in the design code.

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GT_ETHERNET_n

VHDL Instantiation Templates


GT_ETHERNET_1 VHDL Code
-- Component Attribute specification for GT_ETHERNET_1 -- should be placed after architecture declaration but -- before the begin keyword component GT_ETHERNET_1 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00110111100"; bit_vector := "00001010000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "ETHERNET"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 1; boolean := TRUE;

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GT_ETHERNET_n

RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT

: : : : : : : : : : :

integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=

1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 1; 500; 0);

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(7 downto 0); out std_logic_vector(0 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_logic_vector(0 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(0 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(0 downto 0); in std_logic_vector(7 downto 0); in std_ulogic; in std_ulogic;

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GT_ETHERNET_n

TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;

: : : :

in in in in

std_ulogic; std_ulogic; std_ulogic; std_ulogic);

-- Component Attribute specification for GT_ETHERNET_1 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_ETHERNET_1 should be placed -- in architecture after the begin keyword GT_ETHERNET_1_INSTANCE_NAME : -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT GT_ETHERNET_1

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value,

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GT_ETHERNET_n

PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2

=> => => => => => => => => => => => => => => => => =>

bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2,

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GT_ETHERNET_n

TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

=> => => => => => => => => => =>

user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_ETHERNET_2 VHDL Code


-- Component Attribute specification for GT_ETHERNET_2 -- should be placed after architecture declaration but -- before the begin keyword component GT_ETHERNET_2 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00110111100"; bit_vector := "00001010000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 2; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "ETHERNET"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE;

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GT_ETHERNET_n

MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET

: : : : : : : : : : : : : : : : : : : :

bit_vector boolean := bit_vector boolean := integer := boolean := boolean := integer := boolean := integer := integer := boolean := boolean := integer := boolean := bit_vector boolean := integer := integer := integer :=

:= "1100000000"; TRUE; := "0011111000"; TRUE; 0; TRUE; FALSE; 2; TRUE; 1; 4; TRUE; FALSE; 50; TRUE; := "11010110"; FALSE; 2; 500; 0);

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :

out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(15 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_logic_vector(1 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(1 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_logic_vector(1 downto 0); in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;

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GT_ETHERNET_n

RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;

: : : : : : : : : : : : :

in in in in in in in in in in in in in

std_ulogic; std_ulogic; std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(1 downto 0); std_logic_vector(15 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);

-- Component Attribute specification for GT_ETHERNET_2 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_ETHERNET_2 should be placed -- in architecture after the begin keyword GT_ETHERNET_2_INSTANCE_NAME : -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE GT_ETHERNET_2

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value,

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COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN

=> => => => => => => => => => => => => => => => => => => => => => => => => => =>

bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)

=> => => => => => => => => => => => => => => => => => => => => => => => => => => =>

user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP, user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN,

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REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

=> => => => => => => => => => => => => => => => => => => =>

user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

GT_ETHERNET_4 VHDL Code


-- Component Attribute specification for GT_ETHERNET_4 -- should be placed after architecture declaration but -- before the begin keyword component GT_ETHERNET_4 -- synopsys translate_off generic ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE

: : : : : : : : : : : : : : : : : : : : : : : : : : : :

boolean := FALSE; integer := 1; string := "OFF"; integer := 0; boolean := TRUE; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE; integer := 1; integer := 7; boolean := FALSE; boolean := FALSE; integer := 1; bit_vector := "00110111100"; bit_vector := "00001010000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; bit_vector := "00000000000"; boolean := FALSE;

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CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN

: : : : : : : : : : : : : : : : : : : : : : : : : : : : :

integer := 2; boolean := TRUE; bit_vector := "1111111000"; string := "K29_7"; string := "ETHERNET"; string := "K27_7"; boolean := TRUE; boolean := TRUE; boolean := TRUE; bit_vector := "1100000000"; boolean := TRUE; bit_vector := "0011111000"; boolean := TRUE; integer := 0; boolean := TRUE; boolean := FALSE; integer := 4; boolean := TRUE; integer := 1; integer := 4; boolean := TRUE; boolean := FALSE; integer := 50; boolean := TRUE; bit_vector := "11010110"; boolean := FALSE; integer := 4; integer := 500; integer := 0);

: : : : : : : : : : : : : : : : : : : : : : : : : :

out std_ulogic; out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(2 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(31 downto 0); out std_logic_vector(3 downto 0); out std_logic_vector(1 downto 0); out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_logic_vector(3 downto 0); out std_ulogic; out std_ulogic; out std_logic_vector(3 downto 0); in std_ulogic := 'X'; in std_ulogic := 'X'; in std_ulogic; in std_ulogic; in std_ulogic; in std_ulogic;

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GT_ETHERNET_n

LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2 end component;

: : : : : : : : : : : : : : : : : : : : : :

in in in in in in in in in in in in in in in in in in in in in in

std_logic_vector(1 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic_vector(31 downto 0); std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic; std_ulogic);

-- Component Attribute specification for GT_ETHERNET_4 -- should be placed after architecture declaration but -- before the begin keyword -- Enter constraints here -- Component Instantiation for GT_ETHERNET_4 should be placed -- in architecture after the begin keyword GT_ETHERNET_4_INSTANCE_NAME : -- synopsys translate_off generic map ( ALIGN_COMMA_MSB CHAN_BOND_LIMIT CHAN_BOND_MODE CHAN_BOND_OFFSET CHAN_BOND_ONE_SHOT CHAN_BOND_SEQ_1_1 CHAN_BOND_SEQ_1_2 CHAN_BOND_SEQ_1_3 CHAN_BOND_SEQ_1_4 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_2_3 CHAN_BOND_SEQ_2_4 CHAN_BOND_SEQ_2_USE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 CLK_COR_SEQ_1_2 GT_ETHERNET_4

=> => => => => => => => => => => => => => => => => => => => =>

boolean_value, integer_value, string_value, integer_value, boolean_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, bit_value, bit_value,

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CLK_COR_SEQ_1_3 CLK_COR_SEQ_1_4 CLK_COR_SEQ_2_1 CLK_COR_SEQ_2_2 CLK_COR_SEQ_2_3 CLK_COR_SEQ_2_4 CLK_COR_SEQ_2_USE CLK_COR_SEQ_LEN CLK_CORRECT_USE COMMA_10B_MASK CRC_END_OF_PKT CRC_FORMAT CRC_START_OF_PKT DEC_MCOMMA_DETECT DEC_PCOMMA_DETECT DEC_VALID_COMMA_ONLY MCOMMA_10B_VALUE MCOMMA_DETECT PCOMMA_10B_VALUE PCOMMA_DETECT REF_CLK_V_SEL RX_BUFFER_USE RX_CRC_USE RX_DATA_WIDTH RX_DECODE_USE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM SERDES_10B TERMINATION_IMP TX_BUFFER_USE TX_CRC_FORCE_VALUE TX_CRC_USE TX_DATA_WIDTH TX_DIFF_CTRL TX_PREEMPHASIS -- synopsys translate_on port map ( CONFIGOUT RXBUFSTATUS RXCHARISCOMMA RXCHARISK RXCHECKINGCRC RXCLKCORCNT RXCOMMADET RXCRCERR RXDATA RXDISPERR RXLOSSOFSYNC RXNOTINTABLE RXREALIGN RXRECCLK RXRUNDISP TXBUFERR TXKERR TXN TXP

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

bit_value, bit_value, bit_value, bit_value, bit_value, bit_value, boolean_value, integer_value, boolean_value, bit_value, string_value, string_value, string_value, boolean_value, boolean_value, boolean_value, bit_value, boolean_value, bit_value, boolean_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, integer_value, integer_value, boolean_value, boolean_value, integer_value, boolean_value, bit_value, boolean_value, integer_value, integer_value, integer_value)

=> => => => => => => => => => => => => => => => => => =>

user_CONFIGOUT, user_RXBUFSTATUS, user_RXCHARISCOMMA, user_RXCHARISK, user_RXCHECKINGCRC, user_RXCLKCORCNT, user_RXCOMMADET, user_RXCRCERR, user_RXDATA, user_RXDISPERR, user_RXLOSSOFSYNC, user_RXNOTINTABLE, user_RXREALIGN, user_RXRECCLK, user_RXRUNDISP, user_TXBUFERR, user_TXKERR, user_TXN, user_TXP,

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GT_ETHERNET_n

TXRUNDISP BREFCLK BREFCLK2 CONFIGENABLE CONFIGIN ENMCOMMAALIGN ENPCOMMAALIGN LOOPBACK POWERDOWN REFCLK REFCLK2 REFCLKSEL RXN RXP RXPOLARITY RXRESET RXUSRCLK RXUSRCLK2 TXBYPASS8B10B TXCHARDISPMODE TXCHARDISPVAL TXCHARISK TXDATA TXFORCECRCERR TXINHIBIT TXPOLARITY TXRESET TXUSRCLK TXUSRCLK2

=> => => => => => => => => => => => => => => => => => => => => => => => => => => => =>

user_TXRUNDISP, user_BREFCLK, user_BREFCLK2, user_CONFIGENABLE, user_CONFIGIN, user_ENMCOMMAALIGN, user_ENPCOMMAALIGN, user_LOOPBACK, user_POWERDOWN, user_REFCLK, user_REFCLK2, user_REFCLKSEL, user_RXN, user_RXP, user_RXPOLARITY, user_RXRESET, user_RXUSRCLK, user_RXUSRCLK2, user_TXBYPASS8B10B, user_TXCHARDISPMODE, user_TXCHARDISPVAL, user_TXCHARISK, user_TXDATA, user_TXFORCECRCERR, user_TXINHIBIT, user_TXPOLARITY, user_TXRESET, user_TXUSRCLK, user_TXUSRCLK2);

Verilog Instantiation Templates


GT_ETHERNET_1 Verilog Code
GT_ETHERNET_1 GT_ETHERNET_1_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK),

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.BREFCLK2 (user_BREFCLK2), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN), .LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam user_instance_name.ALIGN_COMMA_MSB = "FALSE"; user_instance_name.CHAN_BOND_LIMIT = 1; user_instance_name.CHAN_BOND_MODE = "OFF"; user_instance_name.CHAN_BOND_OFFSET = 0; user_instance_name.CHAN_BOND_ONE_SHOT = "TRUE"; user_instance_name.CHAN_BOND_SEQ_1_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_1_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_1 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_2 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_3 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_4 = 11'b00000000000; user_instance_name.CHAN_BOND_SEQ_2_USE = "FALSE"; user_instance_name.CHAN_BOND_SEQ_LEN = 1; user_instance_name.CHAN_BOND_WAIT = 7; user_instance_name.CLK_COR_INSERT_IDLE_FLAG = "FALSE"; user_instance_name.CLK_COR_KEEP_IDLE = "FALSE"; user_instance_name.CLK_COR_REPEAT_WAIT = 1; user_instance_name.CLK_COR_SEQ_1_1 = 11'b00110111100; user_instance_name.CLK_COR_SEQ_1_2 = 11'b00001010000; user_instance_name.CLK_COR_SEQ_1_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_1_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_1 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_2 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_3 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_4 = 11'b00000000000; user_instance_name.CLK_COR_SEQ_2_USE = "FALSE"; user_instance_name.CLK_COR_SEQ_LEN = 2; user_instance_name.CLK_CORRECT_USE = "TRUE";

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defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam

user_instance_name.COMMA_10B_MASK = 10'b1111111000; user_instance_name.CRC_END_OF_PKT = "K29_7"; user_instance_name.CRC_FORMAT = "ETHERNET"; user_instance_name.CRC_START_OF_PKT = "K27_7"; user_instance_name.DEC_MCOMMA_DETECT = "TRUE"; user_instance_name.DEC_PCOMMA_DETECT = "TRUE"; user_instance_name.DEC_VALID_COMMA_ONLY = "TRUE"; user_instance_name.MCOMMA_10B_VALUE = 10'b1100000000; user_instance_name.MCOMMA_DETECT = "TRUE"; user_instance_name.PCOMMA_10B_VALUE = 10'b0011111000; user_instance_name.PCOMMA_DETECT = "TRUE"; user_instance_name.REF_CLK_V_SEL = 0; user_instance_name.RX_BUFFER_USE = "TRUE"; user_instance_name.RX_CRC_USE = "FALSE"; user_instance_name.RX_DATA_WIDTH = 1; user_instance_name.RX_DECODE_USE = "TRUE"; user_instance_name.RX_LOS_INVALID_INCR = 1; user_instance_name.RX_LOS_THRESHOLD = 4; user_instance_name.RX_LOSS_OF_SYNC_FSM = "TRUE"; user_instance_name.SERDES_10B = "FALSE"; user_instance_name.TERMINATION_IMP = 50; user_instance_name.TX_BUFFER_USE = "TRUE"; user_instance_name.TX_CRC_FORCE_VALUE = 8'b11010110; user_instance_name.TX_CRC_USE = "FALSE"; user_instance_name.TX_DATA_WIDTH = 1; user_instance_name.TX_DIFF_CTRL = 500; user_instance_name.TX_PREEMPHASIS = 0;

GT_ETHERNET_2 Verilog Code


GT_ETHERNET_2 GT_ETHERNET_2_name( .CONFIGOUT (user_CONFIGOUT), .RXBUFSTATUS (user_RXBUFSTATUS), .RXCHARISCOMMA (user_RXCHARISCOMMA), .RXCHARISK (user_RXCHARISK), .RXCHECKINGCRC (user_RXCHECKINGCRC), .RXCLKCORCNT (user_RXCLKCORCNT), .RXCOMMADET (user_RXCOMMADET), .RXCRCERR (user_RXCRCERR), .RXDATA (user_RXDATA), .RXDISPERR (user_RXDISPERR), .RXLOSSOFSYNC (user_RXLOSSOFSYNC), .RXNOTINTABLE (user_RXNOTINTABLE), .RXREALIGN (user_RXREALIGN), .RXRECCLK (user_RXRECCLK), .RXRUNDISP (user_RXRUNDISP), .TXBUFERR (user_TXBUFERR), .TXKERR (user_TXKERR), .TXN (user_TXN), .TXP (user_TXP), .TXRUNDISP (user_TXRUNDISP), .BREFCLK (user_BREFCLK), .BREFCLK2 (user_BREFCLK2), .CONFIGENABLE (user_CONFIGENABLE), .CONFIGIN (user_CONFIGIN), .ENMCOMMAALIGN (user_ENMCOMMAALIGN), .ENPCOMMAALIGN (user_ENPCOMMAALIGN),

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.LOOPBACK (user_LOOPBACK), .POWERDOWN (user_POWERDOWN), .REFCLK (user_REFCLK), .REFCLK2 (user_REFCLK2), .REFCLKSEL (user_REFCLKSEL), .RXN (user_RXN), .RXP (user_RXP), .RXPOLARITY (user_RXPOLARITY), .RXRESET (user_RXRESET), .RXUSRCLK (user_RXUSRCLK), .RXUSRCLK2 (user_RXUSRCLK2), .TXBYPASS8B10B (user_TXBYPASS8B10B), .TXCHARDISPMODE (user_TXCHARDISPMODE), .TXCHARDISPVAL (user_TXCHARDISPVAL), .TXCHARISK (user_TXCHARISK), .TXDATA (user_TXDATA), .TXFORCECRCERR (user_TXFORCECRCERR), .TXINHIBIT (user_TXINHIBIT), .TXPOLARITY (user_TXPOLARITY), .TXRESET (user_TXRESET), .TXUSRCLK (user_TXUSRCLK), .TXUSRCLK2 (user_TXUSRCLK2)); defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defparam defpara