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Switching
Acknowledgments: These slides were originally developed by Prof. Jean Walrand for EE122. The past and current EE122 instructors including Profs. Kevin Fall, Abhay Parekh, Shyam Parekh, and Adam Wolisz have contributed to their evolution.
TOC Switching
Why?
Direct vs. Switched Networks:
Single link n links
Direct
Direct Network Limitations:
Shared medium
Switches
Switched
Distance (coordination delay; propagation limitation) Number of hosts (collisions; shared bandwidth; address tables) Single link technology (cannot mix optical, wireless, ) O(n2) links
Point-to-point links
Techniques
Circuit-Switching (e.g., Telephone net.) Packet-Switching
Datagram (e.g., IP, Ethernet) Virtual Circuits (e.g., MPLS, ATM) Source Routing
Comparison
Circuit-Switching
Mechanism:
Features:
Packets not switched independently (establish circuit before sending data) Dedicated path and resources from source to destination Setup time; low delays and guaranteed resources thereafter
TOC Switching Techniques Circuit
Packet-Switching
Mechanism:
Whole link shared by all packets
Packet Switch
Features:
Data separated into packets Switching decision (output port) for each individual packet Statistical multiplexing: Sum of peak rates may exceed link bandwidth (as long as mean does not)
TOC Switching Techniques Packet
PS - Datagram
General idea: no connection establishment, but each packet contains enough info to specify destination Switches contain forwarding tables (but no perconnection state) Forwarding tables contain info on which outgoing port to use for each destination Two types of addressing:
Layer 2 or Layer 3
b e|b| To From
01000000 11100000
11001001
TOC Switching Techniques Packet Datagram L3
E.g. 1
10100111 10100000 11001100 B 11010000 B Fixed Longest D A Other 11001000 C 11011001 01000000 11100000
11001001
TOC Switching Techniques Packet Datagram L3
10100111 10100000 11001100 B 11010000 B Fixed A Longest D Other 11001000 C 11001001 01000000 11100000
11001001
TOC Switching Techniques Packet Datagram L3
11010001
01000000 11100000
11001001
PS Virtual Circuit
Connection setup establishes a path through switches
A virtual circuit ID (VCI) identifies path Uses packet switching, with packets containing VCI VCIs are often indices into per-switch connection tables; change at each hop Statistical multiplexing is typically used
VC1 VC2 1 4 3 VC1 VC2 2 VC1 In, VC Out, VC 1, 1 4, 1 1, 2 4, 3 2, 1 4, 2
TOC Switching Techniques Packet VC
4 VC1
VC3 2 VC1
3 VC2
Source Routing
Each packet specifies the sequence of routers (or of output ports) from source to destination
source 1 2 3 4 1 2 3 4
4 3 4
1 2 3 4
1 2 3 4 1 2 3 4 1 2 3 4
4 3 4
4 3 4
Comparison
Datagram Virtual circuit switching low flexible flexible low Circuit switching none low yes low
*The idea is that in case of failure, circuit and VC are lost; datagram routing can adapt after routing update .
TOC Switching Techniques Comparison
Characteristics of Switch/Router
Ports
Fast Ethernet, OC-3, ATM,
Protocols
ST, Link Agg., VLAN, OSPF, RIP, BGP, VPN, Load Balancing, WRED, WFQ
Performance
Throughput, Reliability, Power,
Examples
Juniper M160 Cisco GSR Cisco 7600 Cisco catalyst 6500 Extreme Summit Foundry ServerIron
2ft
Juniper M160
WAN Router Large throughput; SONET links Crossbar Fabric Line Cards: Juniper M160 1-port OC-192c 19 4-port OC48c Many others Capacity: (ATM, Ethernet, )
3ft
2.5ft
TOC Switching Examples M160
Cisco 7600
MAN-WAN Router Up to 128 Gbps with Crossbar Fabric 10Mbps 10Gbps LAN Interfaces OC-3 to OC-48 SONET Interfaces MPLS, WFQ, LLQ, WRED, Traffic Shaping
Extreme - Summit
48 10/100 ports 2 GE (SX, LX, or LX-70) 17.5Gbps non-blocking 10.1 Mpps Wire speed L2 Wire speed L3 static or RIP OSPF, DVRMP, PIM,
Foundry - ServerIron
Server Load Balancing Transparent Cache Switching Firewall Load Balancing Global Server Load Balancing Extended Layer 4-7 functionality including URL-, Cookie-, and SSL Session ID-based switching Secure Network Address Translation (NAT) and Port address translation (PAT)
Architectures
Generic Architecture First Generation Second Generation Third Generation Input Functions Output Functions Interconnection Designs
OUT IN VOB Combined IN/OUT
TOC Switching Architectures
Generic
Input and output interfaces are connected through an interconnect A interconnect can be implemented by
Shared memory
low capacity routers (e.g., PC-based routers)
input interface output interface
Interconnect
Shared bus
Medium capacity routers
First Generation
Shared Backplane CPU
Route Table Buffer Memory
Line Interface
MAC
Line Interface
MAC
Line Interface
MAC
Second Generation
CPU
Route Table Buffer Memory
Third Generation
Switched Backplane
Line Card
Li In CP n e t Uer fa ce M em or y
CPU Card
Routing Table
Input Functions
Packet forwarding: decide to which output interface to forward each packet based on the information in packet header
examine packet header lookup in forwarding table update packet header
Output Functions
Buffer management: decide when and which packet to drop Scheduler: decide when and which packet to transmit
Buffer
Scheduler
Output Queued
Only output interfaces store packets Advantage
Easy to design algorithms: only one congestion point
input interface
output interface
Disadvantage
Requires an output speedup Ro/C = N, where N is the number of interfaces not feasible for large N
Backplane
RO
TOC Switching Architectures Output Queued
Input Queues
Only input interfaces store packets Advantages
Easy to build Simple algorithms
input interface output interface
Disadvantages
HOL Blocking In practice: Speedup of 2 suffices
Backplane
RO
Being transferred
TOC Switching Architectures Input Queued: HOL
Crossbar
A = 14 B = 11
C = 15 D = 10
Request 3 1 2 2 1 3
Grant
Accept
Iter
Last Accept
Last Grant
Combined IN/OUT
Both input and output interfaces store packets Advantages input interface output interface
Easy to built
Utilization 1 can be achieved with limited input/output speedup (<= 2)
Backplane
Disadvantages
Harder to design algorithms
Two congestion points Need to design flow control
RO C
Summary
Switching needed for big networks Internetworking externality Circuit Packet VC: QoS possible Packet Datagram
L2: Limited by flat address space L3:
Exact Match: Easy lookup less efficient Longest Prefix Match