Fundamentals of Digital Logic andhficrocomputer Design. M.

Rafiquzzaman
Copyright 02005 John Wiley & Sons, Inc.

Index
1
16L8, 127.
PAL16L8. 127.

2
2732, 206,426,434435,453,510-513,529-532,
674.

4
4-stage look-ahead circuit, 248.

6
6116, 427,434436,453456,510-513,529-531,
658460.
68000 I 68HC000, 3 1, 198,205,218,220-223,
284286,457-542,576-580,585,649-650.
68008, 457458.
68010, 457458.
68012, 457458.
68020, 285,354,576410.
68030 168040 168060, 18,285,354,576-577,
610411.
6821, 514517,529-530,652457.
68230, 516-520,610,651,

7
7447, 102.
7448, 104.
74HC00 174LS00, 58-59.
74HC02 174LS02, 58-59.
74HC04 174LS04, 54.
74HC08 174LS08, 57.
74HC138 l74LSl38, 113-1 14, 1 I9
74HC151 174LS151, 119.
74HC266 174LS266, 61-62.
74HC283 I 74LS283, 119.
74HC32 174LS32, 55-56.
74HC373 174LS373, 143,423.
74HC86 l74LS86, 61.
74HCT244 I 74HCT245, 15.

8
80186 180188, 187,368-369.
80286, 369.
80386, 369,545-571.
80486, 189, 198,369,545,565-571.
8086, 187,200-201,204-205,211-212,341-342,
367456,671.
8088, 368.

8255, 429432,434436,675.
8284, 417420,672.
8288. 673.

A
A/D converter, 339-341,344345,44&441,
524526,579,594,634,
ABEL, 128,634.
Accumulator, 188-189,218,634.
Active high, 63.
Active low, 63.
Adder, 106-1 19,244-25 1.
BCD, 108-109
Binary, 106, 119.
Carry look ahead, 247-248.
Carry save, 250,347.
Full, 106-107,244,246,250,638.
Half, 105-108,244.
Ripple c a y adder, 108.
Adder I Subtractor, 119-120.
Address, 3, 121, 123, 167, 187, 189,204-205,
21 6-2 18,634.
Addressing modes, 220,373-376,461466,
550-551,583-587,634.
Address bus, 3, 187,458,.
Algorithmic State Machines (ASM) Chart. See ASM
charts.
Alphanumeric codes, 32-34.
Altera Quartus 11, 129.
AltiVec, 20,619,620.
AltiVec vs. MMX, 620.
ALU, 2,37, 188-189,254257,349-350,634,
Analog to Digital Converter. See AID Converter.
Analysis of a Combinational Logic Circuit,
100-1 01.
Analysis of a Synchronous Sequential Circuit,
145-1 47.
AND, 4,55-58,633.
Arithmetic and logic unit. See ALU.
Array multipliers, 252-253.
Array processors, 349-35 1.
ASCII, 33-34,212,378,380-381,383-384,596,
597,601,633.
ASIC, 20-21,634.
ASM charts, 135, 168-176.
Assemblers, 213-214,223,231,633.
Assembler Directives, 214-216, 396-399.
Assembly Language, 210-223,398,400,402414,
492498,559-560,588-601,634.
Assembly Language Instruction Formats, 216-21 8.
Assembly Language vs. C Language, 223
Associative cache, 329.
Asynchronous sequential circuit, 135, 176-178,
184,634.

813

13-14. 142. Characteristics table D flip-flop. 142. Computer Instructions. 330. Counter.349-350.635. 30. 142. 6 8 4 9 . CMOS. I . Alphanumeric.200-204. 198-199.503-504. BICMOS. Cache Memory.186-187. C++. 142. Carry Lookahead. 24. 101-105. 262-264. Carry Look-ahead Adder. 2.520-521. Valid bit. 334. 144.6. 159. 166. Characteristic equation of RS-FF. CISC.474. 21. 242-244. 4. Verilog. Write-back. BJT. Complement of a Boolean Function.46. 3 8 4 6 .495. 13-17. Complementary MOS. 1-2.483. 3 8 4 9 . 305. 4.33 1. CPLD. 345-346. Combinational shifter. 1. 64. Compiler.280.257-259.64-65. 35-36.22&227. 1. Design.32.773-777.251. CPU Design. Carry Propagate adder. BCD Arithmetic.580. See Adders. Efficiency.483. Code Converter.437. T flip-flop. Excess-3. 605.285. 231. 328.545.258-259.28-32. 547. 735-740.260-263. 4. 15. Boolean Identities.636. 257-277. 237-239.635. 330-33 1.583. Characteristic equation of JK-FF.417418. 2. 497. 186.543-546.258. 164-1 66. Binary Arithmetic. Canonical forms.569. Gray Code. Binary number. 165. 101-105. Analysis. Comparator. 33-34. 144. JK flip-flop. Design.24-33. CAD Tools.275. 164. Modulo-n. Complement. Byte. 70-71.284-286. 354. 258.300. Combined pagingkegmentation.814 Fundamentals of Digital Logic and Microcomputer Design B Barrel shifter.270-277. 127. Central processing unit.27&273.223. 277-283. 1.187.603. 634. 100-101. Characteristic equation of T-FF. Ring.483. Computer. C C Language.735-740. Control Unit. Cache. 99-101. 258. Binary.200. CMOS Inverter. VHDL. 4748. Bit. Register. EBCDIC. Direct Mapping. 348-349. Control Unit.635. Bus.379. See Adder. Hardwired Control. 33. 773-777. Clock. Block transfer DMA. 330.254-257. Bipolar junction transistor. 635. 32-36.268. 162-1 64. 33-34. 126128. Write-through. 327.3840. 4.543.441. 198. 461. 330-33 1. 6.263-270. 635.41 I. 326-335.546. 240-241. 18.404.37. Boolean function.247. 144. 326-335.565-569. 327. BCD Subtraction. 2.635.634. Organization. Binary. 2. 156-161. Cany Save addition. 329. Consensus Theorem. Big-endian.611.431432. 3.385. 164-166.242-244 .634.635. BCD Adder. BCD to seven-segment decoder. Characteristic equation of D-FF. Carry flag. Miss. BCD. Binary Adders. 101.635.634. 144.602. 242-245.140.635. 143. 1. 110-1 12. 326-335. Self-correcting. Control memory. Combinational logic circuit.570.222-223. 257-259. See CPU. 248. 188-189. 330. Carry Look-ahead Circuit. 3. 188-1 89. Control signals. 20. 2. 262-264. 53. BCD code.8. Boolean algebra. 4748. 577. Control Unit Design. Set Associative.237. Motorola 68020 cache. 156-161. 223-226.460. ASCII. 549. 284-286.610. 33-34.635.275. RS flip-flop. 1977198. Buffer. 185.201-204. 65. Associative. 2. 32-34. Basic Microprocessor Registers.636. 491. Microprogrammed Control. 198. Johnson.271-275. ALU.457. 71. Hit Ratio.578. 198.280. 201-202. Nanomemory.270-273. Codes. Breakpoint. Control bus. BCD Addition. 33 1. 364. 583.70-71.400. 6. See CMOS. Computer Architectures. 250. CPU. 34-35.237. Chip. 329-330. 48. CD-memories. 187. 108-109.38. 245. 635.

Cross Assembler. Block Transfer. 127. 115-1 16. 33-34. 16. 193. 70. E E2PROM. 141-143. 62. 1. See EEPROM.143-144. 160.346345.300.138-144. 35-36. 162-164. 88.460. D D Flip-Flop. EEPROM.277. 206. 329. 6 5 4 6 . 300. 118. .634. Define Byte (DB).440. Summary.634. EBCDIC. Define Constant (DC).637.637.741-743.526.638. 258. 2. 142. 2 13. DeMorgan’s Theorem. Glitch. 306-307. 345-346. Cycle Stealing. 815 Error Correction and Detection. 345-346. Fixed-Point Numbers.96. Exclusive-OR. 31. 489490. Design of Counters.636. See DRAM. 6041. See Adder. JK flip-flop. 138-139.206.. 139. 81-82. Don’t Care Conditions. 636.637. Diode. 109. 190-193. D flip-flop. 127. 61 1. DIP. 215. Firmware.423. Data.636. Description.67. G Gates.206. Preset and Clear. Floating-point Numbers. EQU. 70-71. 638. Hardware. 83. 2 15-2 16. Distributive Law. 139. T flip-flop.3.93. H Half-Adder. 118-120. Foldback. 140. Even function. 79. 214. Expanding op-code technique.636. 142.46.637. 142. 21. Division of unsigned and signed numbers. Flash memory.67. 109-1 10 Fully associative cache mapping. Half subtractor. Five-Variable K-map. 144. JK flip-flop. Four-Variable K-map.55-57. Excess-3 Code. 37. See EEPROM.777-778. 189. Design of a Combinational Circuit. Delay Routine. 142.436-440. 3. 206-207. Fragmentation. D flip-flop. RS flip-flop. 101. 253-254. 637. 777-778. 142. Excitation table.638. Flip-flops. 341-345. 19. Daisy Chain Interrupt. 3 4 3 5 .637. See DIP. 137. Dual of a Boolean Function. 142. Field Programmable Devices. 140-141.636. Dual In-line Package. Full. 65. Half. 70. Hardware breakpoint. General-purpose Register. See D/A. DMA. 49-50. 197-198. Full subtractor. Digital to Analog converter. 84-86. 9-10. 342. Exclusive-NOR. DVD. 65-66. Embedded Application. Design of Synchronous Sequential Circuits. 156-161. 166. 61-62. See DMA. 1.636.6. 93-94. 142. Dynamic RAM. 66-67 General-purpose Resister-based Micorprocessor.521-526. 189. Encoders. Debouncer. Flowcharts. Excitation table. 515.207. 345-346. Essential prime implicants. Floppy disk. 139. 189. Flag register. 123. 193. 228.91. 23 I. 304.638. Demultiplexers.209.637. lp2. Master-Slave. 5. 336-337. Cycle stealing DMA. 127.638. Full adder. Gray Code. RS flip-flop. 2 15. 112-114. 142-144. 54. Data direction register. EDODRAM. 16. Gates with multiple inputs. Delimiters. External Interrupts. 372-373. 399400. FPGA. 141-143. VHDL. Equivalence. See Adder.637. 124. 142. Fetch timing diagram.347. 4. Interleaved. 2 15. Direct cache mapping. Data bus. DRAM. 345-346. 150-156. 328. DIA. Characteristic table. 11. 182.637.220. 9. 143-144. Decoder. T flip-flop.636. 121-122. 185. ECL. EAROM. 238-239.Index Verilog. 129. 83-85. 187. 345-347. F Fan-out. Direct Memory Access. Define Word. 123-127. 37. 93.9. 136.741-743. 139-140. 548-549.

4 0 M 1 4 . 200. Behavioral. 436440. Intel 80386. 128. Hard disk. 560-561. Latches. Stack. Registers. 142. Reset. . 548. 368. 136. Pins and Signals. Clock generation. Data types. 545. Inverter.434436.436446. 340-341. Interrupt Priorities. 562-564. 425428. 369. 563. 227. Intel Merced/IA/64. 18. Interrupt Address Vector.335-347. 376395.575.719-720. 18. Hardwired control. 194.340-345. 347. 4 3 1 4 3 2 .551-558. Kamaugh Maps. Intel 8086. I/O. 568-572. 80486. L2 Cache. 185-186. Characteristic table. Intel 801 86. I/O map.639. DMA. DMA. J Java. 342. 564-565. Intel 32. 142.367451. Hazard. Ready.218-219. 446451. 429430. HCT chips.514521.717-719. K-map. Intel 80188. 237-239.640.639. 504. 446450. I/O summary. 7-9. Intel 8086-based Microcomputer schematic. HCMOS. See Instruction. 434436. C Programming Example. 428432. 341-342.53-54.526. 237-239.286. Instruction Encoding. 573-574.719. 574575. 514-526.404. 62. Programmed I/O. Excitation table. 423.638. 7. 75-86.343. Expanding opcode. 127-129. 335-346. 4. 565-568. Addressing Modes. LED.375. Structural. 206207. 128.701-711.638.587-601. 433. Instruction Register. Intel Pentium 111 / Pentium 4. 562. Demultiplexing addreddata bus using 74LS373. 419420. 421422. Intel 8255. 546565.573. 399400. 18. Interleaved DMA. 370-373. Intel Pentium Pro.251. 263-270. Memory map. Johnson Counter. 342-345.639. 18. Memory & 110 interface.462. 551-558. 345-347.428432. Hexadecimal Numbers. 190-193. 335.457. 547. 345-346. Instruction format. 435436. 467487. 639.436446. Internal interrupts. 166. Intel Pentium. 335. 41 1 4 1 2 .20. Instruction set. 340-345. 25. Interrupt I/O. Description. 237. IEEE Symbols for Logic Gates. 188. See Karnaugh Maps. 434-435. See I/O. Instruction. High-level language. I VO. 545-546. 200-201.27-28. 433. Intempt 110. 300. 139-140. 41 8. JK Flip-Flop. See IC. I/O ports. 216-218. 548-549.376-395. L LI Cache. 414417. Intel Pentium I1 / Celeron / Xeon. Intel 80386 vs. 368. See Hardware Description Language. 2. 139-1 40.638.574. Memory Organization.521-526. 400401. 373-376. 1. Display Interface. Instruction Set. Keyboard / Display Interface. Interfacing with memories. 222-227. IC. Functional unites. Assembler directives.464465. See HCMOS. 418420. HDL.638. High-speed CMOS. 336.457. Interrupt Types. Block code. Addressing modes. System Design.521-526. 396399. 701-711.436446.and 64-bit microprocessors. Interrupts.639.816 Fundamentals of Digital Logic and Microcomputer Design Hardware Description Language. Intel 80486. Instruction Set. Interrupt service routine. InpuUOutput. HMOS.428432. Integrated Circuit. Microcomputer schematic. Functional units.675. 440. 549-550 System Design. 341.639. Programming examples. Dataflow. Dynamic Bus sizing. 434436. 4. Intel 80286. Delay routine. 70. 572-573. 399. Timing Diagram. Index Register. 14. 566.672. 128.547. Pins and Signals. 420. 142.638. 550-55 1.238-239. Instruction Fetch Timing Diagram. Registers.440. 639. Intel 8284.

MC68008. 185-186. MOS. Monitors. Programmed YO. Microprogramming. 4 9 W 9 8 . 499-503. DELAY Routine.326-335.575. Motorola MC68008. 526. 300-304.206. Memory Addressing. Motorola 32. Microcomputer schematic.307.649450. MC68000. 123. LS-TTL. Memory Address Register. 337-338.270-277.204-209.270-283. 205. 644. 188-189. 641. 1. Motorola 68000-based Microcomputer. 210-212. M Machine language. Multiprocessing. 166. I/Omap. Motorola 68000-based microcomputer schematic. 517. 489490. Memory management. 619420. 201.369-370.658460. Microprogram.3. 15. 528-532.270-283. ROM. Moore circuit.433435.121. Nonvolatile. MMU. 526-529. Maxterms. 164. See MC6116. 162. 123. 15. Metal-Oxide Semiconductor. DRAM. 193-198. 529. C Programming Example. 214. 166. 528. 185-189. 1-2. 166. 517-519.495. Microcomputer.83. 219. LSI. Pins and Signals. Macroprogram. MOS outputs. 166168. Memory map.206. Instruction Execution Times. Motorola MC68000/68HC00.and 64-bit microprocessors. Masking operation. 505-509. DTACK delay circuit.205-209. Memory mapped I/O.640. See Bus. 434435.641. 5 16-520. 521-526.185.585. Master-Slave Flip-Flop. 121. 4.2. EAROM. 2. Meta-assembler. 13.512-513. 458.637. 341-342. Cache. 576-620. PROM. 458. Microprogrammed Control Unit Design. Motorola 61 16. 457-542. 188-201.299-304. 491492.511-514. 9-l0. 1. Main Memory Array Design. 487489. Memory. RAM.166-168. Microcontrollers. 31.220-223. DMA. 127. 166168. 661-669. 71-74.127. 370.121-123. Logical shift operation. MIPS.32&335. 65. Volatile. Interrupts.641. Addressing Modes. Microprocessor registers.528.519. 504-505.637.347.218. 277-283. 2 13. See Memory Management Unit. MOS switch input. 326. 508-5 1 1. 121. Microcomputer Development Systems. 458. Timing Diagrams. 529-532.817 Index Light Emitting Diodes. Motorola MC68010. Stack. Maskable interrupts. 3.510. Motorola MC68012. Motorola MC6821. 514-517.284286. Reset. 71.6 19-620. 209. Microcomputer Bus. Exceptions. E2PROM.205.204-205. EEPROM.428429. 15-16. 458.477478. 641. Microcomputer programming languages. 427.75.456. 201-204. 166. 457-542. Clock Generation. 305-306. 641. 3. 123. 513. Minterms. Microprocessor. Little-endian.641. 53 1-532. 514-521. 72. Programming examples. Mealy circuit.65 1. MC68230. 185.637. 202. Memory Types.504.206. 18. Locality of reference. 521-526. Instruction Set. MMX. Microinstruction. Memory Management Unit.641. 127. MC68012. 6800-68230 Interface. 306. 68000-6821 Interface. SRAM. 201-204. DTACK timing diagram. Memory Organization. Macroassembler. Memory fragmentation. See LED.433. 270-283.20-21.438440.127. 458.299. 148. Microprocessor system development flowchart. 187.73.497. 515-517. 520-52 1.14-16. 573-574. Interfacing with Memories. 189. Main memory. 51 1-514. 467487. 2.696-699.384-385.652457. .209. Microprogrammed CPU Design. 3.641.548. 123. MC68010. Merced.347. 3. 528. 529.20.576580. 460.696-699.205. 304-307. Motorola’s stat-of-the art microprocessors. Literal. 13-15. Modulo-n Counters. 205-209. 46 1. 516517. System Design. 458. 232-23 3. 123. 545. 2 10. 5 14-52 1. Microcomputer. 123. 528-532. 461466.74. MC6116. 227-228. 148. 198. 140-141. Registers.640.206. 228-23 1. MC6821.640.607410. Modulo-4 Counter.

318.516521. Nonvolatile memory. 237-239.67. 583-587. Pipelining. 29.644. Primary memory. 46. Prime Implicants.399. 16. 610. 207-209. . 189-193. See RAM.644. 189. 12-13. Q Quine-McCluskey Method.644. 342-344. 610.6. Binary. See Multiplexer.643. See PAL. Parallel processing. NOT. Open-collector outputs. 123. 610-61 1.383.53-54. 198-199. Optical memories. Octal Number. Motorola MC68030. Product-of-sums. PAL16L8. 9-10. 63.428432.311-315.58-59.642. 105. 576410. Nibble. PLD Programming Languages. 73-74. Nanomemory. 196197. Nonmaskable interrupts. READY. ORG. 61 1 4 2 0 .88-91. 127. Program. PLDs. 63.305.644.487489. 88-91. Arithmetic pipeline. PEEL. 581-583. 33-34.643. PMOS. 215. 10-1 I . Pentium 111. 286286. 24. 127. Propagation delay.642.93-94. Pentium 11.2628. 1 6 6 168. 604405. Paging. 695499. 70. 127-129.643. 354-359. Priority Encoder. 299. Program Counter. ORIGIN. Hexadecimal.258.25. Dynamic Bus Sizing. See PowerPC. See PGA. 544. 642. Nanoprogram. 29-32. NAND gate implementation.643. NOR.641. 347-359. 601404.642.300. 102. Instruction pipeline. 643. READ and WRITE Operations.644. Pentium 4. Interfacing with Memories. Octal. 196197. Pins and Signals.642. 572-573. 23-52. 258.642.205-209.7. 341. 573-575. 124126. Motorola MC68040 / MC68060. See PLD. Addressing Modes. 126-128.63. 2. 607410. See PLA. 21. NOR gate implementation.399. 121. Signed. 3.379. 114-1 16. Read-only Memory.576. Ones complement arithmetic. Unsigned. Parity. 2 1 1.487489. 16. 3940. Nine’s complement.642.300.818 Fundamentals of Digital Logic and Microcomputer Design Motorola MC68020.59. See ROM. Programmed I/O. P Packed BCD.546545. 336. I/O. System Design.. 336340. Pentium Pro. 3.642. 199. 521..596597. 15. 91-93. Programmable array logic. 39-40. R E A D W T E .307-309. Overflow. 4. 93.642. OR. 4346.639.91-93.568-572.222.643. Random Access Memory. NMOS. PAL. 587401. N NAND. 1.458. MSI. Programmable Logic Devices. 644. Number Systems. Programmable logic array. 576. 351-359. See Main Memory. POP.642. 141-143. Polled interrupt. 15. 353-354. PROM. 25.37. Comparison with 68HC000. Multiplexer. 25.250-254. 10. 188-191. 213. PUSH. See ORG. Instruction Set. Multiplication of two unsigned and signed binary numbers. 4. 24. See Nanomemory.474.54. 13. 335-346. Positive logic. Negative logic. Pentium. Operating systems.27-28. 307. 0 Object codes. Op-code encoding. 13. Motorola PowerPC. RAM. Paged-segmentation method. Ones complement. 18. MUX. 123-124. Odd Function.643. 516-520. 116-1 18. Multiple-Output Combinational Circuits.5456.642. 81-83. 607-610.644. Processor memory. 643.644.545. 86-87. 58. 24. 124. 305. PGA. Pin Grid Array.437. 226.250. Preset and Clear Inputs of Flip-Flops. Noise margin. Race Condition. 16. 18.644. 39.222.381.644. 49-50. PowerPC. 28-3 1. Motorola MC68230. 127. 132. One-Pass Assembler. Port.482483. PLA. Registers.

25 1. 121.205. Signed division. 136-138. 719.634. 221.507.383. Unsigned binary numbers. 646. USB Flash Memory. 88. 349-351.644. Description. 185. Design. Open-collector output. 32. 253-254.460. case. 6. 8. 337-338. 147-154. 72. 195-197.Index 819 READ Timing Diagram. Excitation table. Superscalar Processor. 251. 144.388-391. Sign-magnitude Numbers. Totem-pole outputs. 76-77. 299-300. 213. Blocking assignment. Status Register. 619. T U Unicode. 743-745. Self-correcting counter. SRAM cell. Three-Variable K-map. Register transfer.647. 138-139. 250-25 1.646.476. Two-Pass Assembler. Sequential logic circuit. 165. 150-1 56. 144. Common anode. Totem-pole output. Unified cache. V Vector machine. Sixty-Four Bit Microprocessors. 138. 8. 109.715. 336.719-721. 545. Shift Operations. 6. Scalar Processor. 162-164. 372-373. 419420. 197-198. Sign-magnitude arithmetic. Ten’s complement. Set-associative cache mapping. 9-1 I . 38. 158-159.305-306. 645. 576. Tristate. 46. 754. 23 1.405 Unsigned addition. S T Flip-Flop.612. 300. Full-subtractor. 129. 142. SRAM. 15-16. 142. SIMD. 305-308. 127-129. Stack. 10. 11. 128. 36-37. 10. 1 1. 730.123. Segmented memory.419420. Signed multiplication. always.611-612. 204-205. Description. 6. 108. 11. Minimization. SDRAM. Schmitt Trigger. 1. 348-349. Relocatable. assign.545. 328. RISC. 1 I . 28-29.383. Stack Pointer. Thirty-two Bit Microprocessors. 714.505-509. . 259-260. 135. 172. Spooling.381. Signed binary numbers. Twos complement. SSI.646. 1.369. ALU.258. Saturation mode. Secondary memory. 38. 3946. 10-1 1. 46. 147. Active mode.713-755.487489. 221. 204-205.428. 3 11-3 15. 39-40. 74. State machines. 647. 10. 188-189.311-314. State diagram. Seven Segment Displays. Tristate.645. Static RAM. Subroutine.479482. Unsigned multiplication. Segments. 39. Ring Counter. Ripple Counter. 146.460.645.437. 570. begin. 145-1 76.See SRAM. 18. 185. 372. 10. Sign extension. Segmentation.646. 194-195. 386386. Verilog. 543. Cut-off mode.316.565. 729. 143. 17. RS Flip-Flop. Common cathode. 148-150. 140. 29-32. Single-chip microcomputer. 167. 254. 399. 242-244. 207. 231. ROM-based multiplier. 162-164. 8. Signed subtraction. One’s complement. 197. 720. 140. 570. ROM.647. Subtractor. Excitation table. 10. Unsigned division. Ripple Cany Adder. 714. 142.460. Analysis. 159. 145-147. 166.576-61 1.304-326.34. 170.373. 142. 109-1 10. 142. Behavioral. Single-step. 16.646.645. State machine design using ASM chart. TTL.645. Characteristic table. 221-222. Signed addition. Software. 645.575. Characteristic table. Transistor. Unpacked BCD.228-233. RESET. Standard I/O. 195.485. Software breakpoint. Sum-of-Products. SR Latch. TTL outputs. 2. 11.3 13-3 14.644.239-242. 170-1 76. Half-subtractor. 206. 329-330. Two-Variable K-map. Register. State table.6-7.645.399. 188. 142.647.645.646. 76. 29. Single-Chip Microprocessor. Synchronous sequential circuit..

729. Hierarchical. Clock. 766-769. Procedural statement. User-Defined Primitive (UDP). 760. parameter. Concatenate operator. generic. entity. 743. 714. XOR. 128. wire. 781-785. 762. Write-back method. Combinational circuit design. if-else. Counter.757-806. $monitor. Behavioral. case. 758. 714. 7 15. 757. 761 process. 713. 195. Zip disk. 769. variable. Positional association. when-else.209. 76 1. architecture. 713. 714. 71 8. 636.648. Counter. 3. 714.634. if-else.764765. wait until. in. Miswiring. $display. 728. 760. Write-through method. 714. 758. Conditional operator. CPU. Dataflow. See Exclusive-OR. 725. 758. . 719. 762. 761. port.Fundamentals of Digital Logic and Microcomputer Design Clock. 716. Volatile memory. 778-781. 15-16. Numbers. Non-blocking assignment. 758. Net. Test bench. XOWXNOR Implementation. 714. 735-740. 127-129. IEEE 1164. 10. 714. VLSI. 778-781. signal. Sequential circuit design. Dataflow. end. $time. Combinational circuit design. 300.648. VHDL. constant. 716. 2. 715. 11.3. 129. endmodule. 714. Operators. 729. Virtual memory. 757. 715. 777-778. initial.760. WRITE Timing Diagram. 197-198.460. buffer. 758. inout. CPU. 718. Operators. Reduction operator.758. 762. 773-777. See Exclusive-NOR. 128. 769. 729. Structural. 373. Named association. 764. 719. generic map. 713. Structural. 720. Concatenate operator. Mixed. Hierarchical. 758. 758. 785-805. 758. 729. Positional association. 713. 769-805. 759. out. reg. 763. 777. Memory. Status Register. 760. 205. Z Zero flag. 765.648. 721-728. 763. 717-719. Named association. Register. 763-764. with-select. 761-763. 166. 778-78 1. 758. component. 330. 723. 208. 128. bit-vector. 719. 741-743. 330.719. 304326. 762. Status Register. Word. 714. 745-753. 7 16. X XNOR.763-765. W Wired-AND logic. generate. Synchronous sequential circuit design. 715 module. 91-94. 759-761.636. ALU. 729.

Sign up to vote on this title
UsefulNot useful