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Fast Methods to Estimate Clock Jitter due to Power Supply Noise

Koutaro HACHIYAa) , Takayuki OHSHIMA , Hidenari NAKASHIMA , Nonmembers, Masaaki SODA , Member, and Satoshi GOTO , Fellow

PAPER

Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa

SUMMARY In this paper, we propose two methods to estimate clock jitter caused by power supply noise in a LSI (Large-Scale Integrated circuit). One of the methods enables estimation of clock jitter at the initial design stage before oor-planning. The other method reduces simulation time of clock distribution network to analyze clock jitter at the design verication stage after place-and-route of the chip. For an example design, the relative dierence between clock jitter estimated at the initial design stage and that of the design verication stage is 23%. The example result also shows that the proposed method for the verication stage is about 24 times faster than the conventional one to analyze clock jitter. key words: clock jitter, power supply noise, clock distribution network, power distribution network

1.

Introduction

Considering power supply noise in LSI design becomes more and more important according as the technology trends of LSI are moving towards increasing clock frequency and decreasing power supply voltage [1]. The eects of the power supply noise are dierent depending on the types of the circuits such as logic circuits, analog circuits, and input/output buers. In synchronous logic circuits, two kinds of variation in signal delay are caused by the power supply noise: delay variation of data path between FFs (Flip-Flops) delay variation of clock path which is called clock jitter The clock path is dened as the path from the root of the clock distribution network to the input terminal of a FF. When the power supply noise is too large, some circuits may not be able to satisfy the timing constraints, such as setup time and hold time [18], due to the delay variations and the circuits will operate incorrectly. For the high speed interface such as DDR (Double Data Rate) and USB (Universal Serial Bus), the jitter of the clock signal supplied to the interface circuits must be small enough. The power supply noise in the clock distribution network of the clock signal will cause large clock jitter and high bit- error-rate in data transmission
Manuscript received June 26, 2006. Manuscript revised October 23, 2006. Final manuscript received December 22, 2006. The authors are with NEC Electronics Corp., Kawasaki-shi, 211-8668 Japan. The author is with the Graduate School of Information, Production and Systems, Waseda University, Kitakyushu-shi, 8080135 Japan. This paper was presented at Karuizawa Workshop. a) E-mail: k.hachiya@ieee.org DOI: 10.1093/ietfec/e90a.4.741

over the interface. This paper focuses on the estimation method of clock jitter caused by power supply noise in a clock distribution network. The method to estimate or analyze power supply noise is beyond the scope of the paper although its example and experimental results are shown. Such methods have already been proposed in many previous papers [1], [9], [11] [13]. We propose two methods to estimate the clock jitter for a given power supply noise. One of the methods is for the initial design stage and the other is for the design verication stage. The clock distribution network in this paper is assumed to have tree structure with same delay from the root buer to each FF. In the initial design stage, power supply noise is estimated by using a simple power distribution network model. The power supply noise is converted into the delay variation of clock paths. In the design verication stage, a detailed power network model is made from layout data of a chip, and the power supply noise is analyzed using the model. The eective static IR-drop [2] of each clock buer is calculated from the power supply noise. From the eective static IR-drop, the jitter of each clock path is estimated and the path having the biggest jitter is selected. Then, the clock jitter on the selected path is analyzed accurately by SPICE [15]. There has not been any available method to estimate the clock jitter at the initial design stage in the literature. In the clock jitter estimation at the design verication stage, the conventional method [3] is inappropriate for actual designs because the whole clock circuit has to be analyzed and it takes too much time. This paper is organized as follows. In Sect. 2, we present the method to estimate the clock jitter at the initial design stage. In Sect. 3, we present the method to estimate the clock jitter at the design verication stage. Section 4 shows the experimental results of the proposed methods. Finally, the paper concludes in Sect. 5. 2. Clock Jitter Estimation at Initial Design Stage

The proposed method of clock jitter estimation at the initial design stage is described in this section. The initial design stage means the design stage when chip size estimation and package type selection are done before the oor-plan design. In the method, the power supply noise is estimated rst, and then the clock jitter due to the power supply noise is estimated.

Copyright c 2007 The Institute of Electronics, Information and Communication Engineers

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Fig. 1

Power distribution network model for the initial design stage.

2.1 Estimation of Power Supply Noise at Initial Design Stage As mentioned above, method to estimate power supply noise is beyond the scope of this paper. It is assumed that there exists a method which can estimate power supply noise accurately enough. Therefore just a brief explanation of an example method is presented here. First, the following models are derived with possible accuracy at the initial design stage, and the circuit shown in Fig. 1 is formed. power distribution network of package: Z p on-chip power distribution network: Zc total supply current drawn within chip: i(t) As for the package model, LRC lumped model (e.g. shown in Fig. 5) of a VDD (power) and VSS (ground) pin of any type of package is preliminarily obtained by measurement or electromagnetic analysis, and then the model of the power distribution network in a package is derived by connecting the lumped models of all VDD and VSS pins according to the number of pins used for VDD and VSS. As for the on-chip model, Zc in Fig. 1 is modeled as a single capacitor between a and b. Nodes a and c are shorted, and nodes b and d are also shorted. Each pair of nodes above is sometimes connected by a resistor representing on-chip power grid resistance. The single capacitor is the sum of cell capacitance, well capacitance and wire capacitance [16]. Preliminarily calculating the capacitance between power pin and ground pin for each cell, the cell capacitance is obtained from the types and the number of cells used in a design. The well capacitance can be estimated from the chip size. The wire capacitance, capacitance between signal line and power/ground line, is estimated from the chip size, the interconnect structure and total signal length [4], [5]. The total signal length is estimated from Verilog netlist and the chip size [6], [7]. As for the current model i(t), it is derived from the power consumption of every clock domain. The current waveform for each clock domain is synthesized as periodical impulse so that its period is the same as the clock period of the clock domain [9]. Total current waveform i(t) is the sum of the current waveform of every clock domain. The power supply noise v(t) within the chip is calculated by transient analysis of the circuit in Fig. 1 using SPICE.

Fig. 2

Flowchart of clock jitter estimation at initial design stage.

2.2 Estimation of Clock Jitter from Power Supply Noise at Initial Design Stage In this section, a method to estimate clock jitter from power supply noise v(t) is presented. Hereafter, jitter means the peak-to-peak of period jitter [10]. The method uses the following two approximations of path delay variation known by experience [17]. Approximation 1: The delay of a path with power supply noise v(t) can be approximated by the delay of the path with the eective static IR-drop v, which is dened by v= 1 pd0
to to pd0

v(t)dt,

(1)

where pd0 is the path delay without power supply noise, and to is the time when the signal reaches the output of the path. The path delay is the delay from when the input signal of the path crosses 1/2 of the power supply voltage to when the output signal crosses 1/2 of the power supply voltage. Approximation 2: Delay increase Jd of a path with static IR-drop v can be approximated by Jd = p v pd0 , (2)

where p is a constant determined by linear approximation of the delay variation characteristics of the path. Figure 2 shows the owchart of the proposed method to estimate clock jitter. The detailed procedure is explained in the following. First, the clock path delay pd0 without the power supply noise is estimated. The delay is the signal propagation delay from the root of the clock distribution network to the input terminal of a FF. Here it is assumed that the clock distribution network has a tree structure and delays of all paths from the root to FFs are the same. pd0 can be estimated from the number of clock buers and their drivabilities. The number of buers and their drivabilities are estimated from the number of FFs and the chip size by experience. Next,(t), the eective static IR-drop when the clock v

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signal reaches to FFs at time t, is calculated by the following equation, v(t) = 1 pd0
t t pd0

v()d .

(3)

Jd(t), the delay variation when the clock signal reaches to FFs at time t, is approximated by Approximation 2: Jd (t) = p v(t) pd0 . (4)

p can be estimated from the clock path structure assumed in estimating pd0 and the delay variation characteristics of clock buers in the clock path. The period jitter J p (t) is dened by the following equation, J p (t) = Jd (t) Jd (t T 0 ) , (5)

Step 1. The eective static IR-drop v of each clock driver is calculated every when the output signal transition occurs. Then the delay variation of each driver is also calculated from v. Step 2. The delay variations of all drivers in the clock path are added. The sum of the delay variations is the delay variation of the clock path. Step 3. Steps 1 and 2 are repeated for some clock cycles. The peak-to-peak of period jitter of the clock path is estimated. Equation (1) is used to calculate eective static IR-drop in Step 1. The integral interval in Eq. (1) is determined by the timing windows of input and output pins of the driver which are derived by STA (Static Timing Analysis). The delay variation of a clock driver is calculated by the following equation like Eq. (2). Jd = c v pd0 , (7)

where T 0 is the clock period without power supply noise. J pp , peak-to-peak of period jitter J p (t), is the dierence between the maximum and the minimum of the period jitter. J pp = max J p (t) min J p (t)
t t

(6)

3.

Clock Jitter Estimation at Design Verication Stage

In this section, we present the method to estimate clock jitter at the design verication stage. The design verication stage means the verication stage to do timing verication, reliability verication and other design rule checks after a trial layout or the nal layout of the chip. Since the simultaneous analysis of combined power distribution network and clock distribution network takes long run-time, it is not practical for actual VLSI designs and the following two-step method is proposed in [3]. Step 1. Power supply noise is analyzed using the power distribution network model derived from the layout data by using LPE (Layout Parasitic Extraction) tool. Step 2. Clock jitter is analyzed using the clock distribution network model derived from the layout data with power supply waveforms of all the clock drivers given from Step 1. The proposed method in this paper is also based on the twostep method. Many methods have been proposed to analyze power supply noise in Step 1 [1], [9], [11][13]. In this paper, analysis method in Step 2 is only discussed. In the conventional clock jitter analysis [3], transistor-level circuit model (SPICE netlist) containing a whole clock distribution network is analyzed by SPICE. However, in most of actual designs, only the worst value of jitter of all the inputs to FFs is needed. The paper proposes to select and analyze the single clock path having the worst jitter instead of the whole clock distribution network. The method to select the clock path with worst jitter is shown below. First, peak-to-peak of period jitter of each clock path is estimated by the following steps.

where pd0 is the cell delay of the driver which is calculated by STA. c is a constant depending on the driver. After nishing Steps 1-3 for all clock paths, the path having the largest jitter is selected. Then The transistor-level SPICE netlist including only the path is created. The other paths connected to the selected path are replaced by eective capacitances in the SPICE netlist. Finally, the peak-to-peak of period jitter is calculated by SPICE simulation for several clock cycles. 4. Experimental Results

In this section, we present experimental results of the estimation method of clock jitter proposed in Sect. 23. First, a jitter analysis result and the measurement result of the LSI using CMOS 90 nm technology shown in Table 1 are compared to show the accuracy of the conventional two-step method [3] which the proposed methods relies on. Next, speedup and accuracy of the proposed method when applied to the example LSI design using CMOS 0.15 m technology shown in Table 2. 4.1 Accuracy Validation of Method to Estimate Clock Jitter at Design Verication Stage In order to show the correlation between analysis and measurement, we compare analysis result and measurement reTable 1 Information of LSI used for measurement. Number of gates 5.88 M gates Chip size 6.29 mm square Maximum clock frequency 264 MHz Frequency of the measured clock 132 MHz Power supply voltage Vdd 1.2 V Number of VDD pins 71 Number of VSS pins 75 PKG L per pin 8.358 nH PKG R per pin 495.6 m PKG C per pin 14.71 pF

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744 Table 2 Design information of example LSI. 1,847 3.996 mm square 500 MHz 1.5 V 162 620 psec 8 8 1.0 nH 25 m 0.5 pF

Number of instances Chip size Clock frequency Power supply voltage Vdd Number of clock paths Clock path delay pd0 Number of VDD pins Number of VSS pins PKG L per pin PKG R per pin PKG C per pin

Fig. 3

The evaluation circuit (clock circuit for DDR memory interface).

sult of clock jitter of a clock path in LSI, which brief information is shown in Table 1. Figure 3 shows the evaluation circuit. It is a clock circuit of DDR interface, which has the clock path from PLL to Slave-DLL (bold line in Fig. 3). When the other circuits in the LSI are operated, power supply noise and clock jitter occur at the clock path. The clock path has probe-pads at the output pin of the PLL and the input pin of the Slave-DLL so that clock jitter can be measured by an oscilloscope at these pads. The power supply noise is analyzed by a commercial dynamic power supply noise analysis tool [11] with the detailed power network model extracted from the layout data and with the package model shown in Fig. 5 for each VDD/VSS pin where the L, R and C of the model are shown in Table 1. Then, the clock jitter is analyzed by SPICE with the detailed clock network model and the power supply noise. The measurement and SPICE simulation results are shown in Fig. 4. The dierence of the jitter between them is less than 1.0%. 4.2 Speedup of Clock Jitter Analysis at Design Verication Stage In order to show the speedup eect of the proposed method to estimate clock jitter at the design verication stage, runtime of the proposed method and that of the conventional one are compared. Power supply noise is analyzed by the commercial analysis tool [11]. In the analysis, the package model shown in Fig. 5 is connected to each VDD/VSS pin where the L, R and C of the model are shown in Table 2. Figure 6 shows the VDD-VSS voltage waveform of a clock buer. The peak-to-peak of the voltage of the buer
Fig. 6 stage.

Fig. 4

The measurement and simulation results.

Fig. 5

Package model of a VDD/VSS pin.

Power supply voltage waveform analyzed at design verication

is the biggest one of all clock buers. Figure 7 shows the delay variation characteristics of the clock buer when the power supply noise v is varied in DC. The load capacitance of the buer is set so that the cell delay and the interconnect delay are the same. c in Eq. (7) is derived as the slope at v = 0 in Fig. 7, and is equal to 1.02 V1 for the buer. The peak-to-peak of period jitter of each clock path is calculated by the following two dierent procedures. In the calculation, VDD and VSS waveforms of each clock buer

HACHIYA et al.: FAST METHODS TO ESTIMATE CLOCK JITTER DUE TO POWER SUPPLY NOISE

745 Table 3 Run time of SPICE. Analysis Method Run time [sec] Ratio Conventional Proposed 4,230 175 24.2 1

Fig. 7 Delay variation characteristics of a clock buer for DC power supply noise.

Fig. 9

Power supply noise v(t) and its eective static IR-drop v(t).

ventional one. The run time for the clock path selection is 3.94 sec, and it can be neglected. 4.3 Accuracy of Clock Jitter Estimation at Initial Design Stage In the clock jitter estimation at the initial design stage, power network model of package, that of chip and power current model may be inaccurate. This paper assumes that there exists a method which can create those models accurately. Therefore, here the clock jitter at the initial design stage is estimated from the power supply noise obtained by analysis at the design verication stage, and it is compared with the jitter of analysis result at the design verication stage. In addition, to make the experiment more realistic, the power supply noise and clock jitter are estimated using the power network model derived only by the information available at the initial design stage. 4.3.1 With No Error in Supply Voltage In the jitter estimation here, the power supply noise v(t) analyzed at the design verication stage shown in Fig. 6 is used. Figure 9 shows the eective static IR-drop v(t) derived from the power supply noise. In the derivation, Eq. (3) is used. Figure 10 shows the delay variation Jd (t) and the period jitter J p (t) of the clock path. They are derived from v(t) in Fig. 9 using Eqs. (4) and (5). In Eq. (4), the constant p = 0.581 [V1 ] is used, which is derived from the delay variation characteristics of a clock path like shown in Fig. 7. The peak-to-peak of the period jitter is derived as J pp = 159 [psec] using Eq. (6). J pp at the initial design stage is 23% bigger than that of SPICE analysis result by the proposed method at the design verication stage (i.e. jitter by SPICE of the right- and up-most dot in Fig. 8). It is also 17% bigger than that estimated by the path selection in the proposed method (i.e. jitter by the path selection of

Fig. 8

Comparison of jitter by SPICE and that by the path selection.

from the power supply noise analysis result are used. The VDD/VSS waveforms are dierent from buer to buer. 1. The SPICE netlist including the clock path is created from the layout data and VDD/VSS voltage waveforms of the power supply noise analysis result. The clock jitter is analyzed by SPICE with the netlist. 2. The jitter estimation method for the path selection in the proposed method described in Sect. 3 is done. Figure 8 shows the relationship between the clock jitter analyzed by SPICE and that of estimated for the path selection in the proposed method. Each dot corresponds to a clock path. The dierence between the estimated results and the SPICE results ranged from 4 ps to 21 ps, and their relationship is roughly linear. In the experimental result, the clock path with the maximum jitter by the path selection accidentally has the maximum jitter by SPICE. However, for the design, it is considered that the estimation error in the path selection can reach 25 ps, the width of the two dashed lines in Fig. 8. Table 3 shows the run time of SPICE in the two methods: One is analyzing the whole clock distribution network, the other is analyzing the selected single clock path. Here, SPICE program is the in-house tool [14], and the platform is a Linux PC with AMD Opteron 2.4 GHz.The result shows that the proposed method is 24.2 times faster than the con-

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5.

Conclusion and Future Work

Fig. 10

The delay variation Jd and the period jitter J p .

In this paper, the methods to estimate clock jitter at initial design stage and design verication stage are proposed. An experimental example shows that relative dierence between period jitter (peak-to-peak) values estimated at initial design stage and design verication stage is 23% when there is no error in the power voltage waveform used at the initial design stage. The experimental result also shows that SPICE execution speed of the proposed method is 24.2 times faster than that of full-chip clock analysis with all clock-paths. The remaining issues include validating the proposed methods with various LSI designs. To enhance the accuracy of jitter estimation at the initial design stage, we need to develop method to derive models of package and chip with necessary accuracy. Reducing estimation error of period jitter (peak-to-peak) in the clock-path selection will also be a future work. Acknowledgments Mr. Muta in Kyoto University contributed the experimental results. The measurement data in Fig. 4 are contributed by Mr. Takeuchi, Mr. Ohno, Mr. Uenishi, Mr. Ibe, Mr. Makino and Ms. Hokoiwa of NEC Micro System Corp. The authors would like to thank Mr. Akimoto and Mr. Uchida of NEC Electronics Corp. for having fruitful discussions on the topic. The authors also acknowledge Mr. Sakuma and Mr. Kawarabayashi of NEC Electronics Corp. for their giving chance to present the paper.
References [1] S.S. Sapatnekar and H. Su, Analysis and optimization of power grids, IEEE Des. Test Comput., vol.20, no.3, pp.715, May-June 2003. [2] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, Timing analysis considering temporal supply voltage uctuation, Proc. ASP-DAC 2005, pp.10981101, Jan. 2005. [3] R. Saleh, S.Z. Hussain, S. Rochel, and D. Overhauser, Clock skew verication in the presence of IR-Drop in the power distribution network, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.19, no.6, pp.635644, June 2000. [4] J.H. Chern, J. Huang, L. Arledge, P.C. Li, and P. Yang, Multilevel metal capacitance models for CAD design synthesis systems, IEEE Electron Device Lett., vol.13, no.1, pp.3234, 1992. [5] S. Takahashi, M. Edahiro, and Y. Hayashi, Interconnect design strategy: Structures, repeaters and materials with strategic system performance analysis (S2PAL) model, IEEE Trans. Electron Devices, vol.48, no.2, pp.239251, 2001. [6] J.A. Davis, V.K. De, and J.D. Meindl, A stochastic wire length distribution for gigascale integration (GSI): Part I: Derivation and validation, IEEE Trans. Electron Devices, vol.45, no.3, pp.580589, 1998. [7] H. Nakashima, J. Inoue, K. Okada, and K. Masu, ULSI Interconnect length distribution model considering core utilization, Proc. Design Automation and Test in Europe 2004, no.2, pp.12101215, Feb. 2004. [8] X. Wu, X. Hong, Y. Cai, Z. Luo, C.K. Cheng, J. Gu, and W. Dai, Area minimization of power distribution network using ecient

Fig. 11

Power supply noise estimated at initial design stage (solid line).

the right- and up-most dot in Fig. 8). The main reason of the error is considered to be the following. J pp at the design verication stage is calculated from the delay variation of clock buers at the time when the buers actually make their output transitions, while the J pp at the initial design stage does not consider the actual transition time. 4.3.2 With No Error in Supply Current In the experiment here, the power supply voltage at the initial design stage is estimated using the model in Fig. 1 with the power current i(t) of total supply current in the analysis result at the design verication stage. The package model used in the estimation is the same model used for the design verication stage. All terminals connected to VDD pads are connected to the node a in Fig. 1. All terminals connected to VSS pads are connected to the node b in Fig. 1. The chip model is expressed by a single capacitor which connects between VDD and VSS nets within the chip. The capacitance is the sum of cell capacitances, well capacitance and wire capacitance. The power supply voltage waveform estimated by SPICE using the circuit in Fig. 1 is the solid line in Fig. 11. The dotted line is the same waveform in Fig. 6. These two waveforms in Fig. 11 are nearly the same. Using the estimated voltage waveform (the solid line), the peak-to-peak of period jitter of the clock is derived as J pp = 151 [psec] using Eqs. (3)(6).

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Hidenari Nakashima received the B.E. degree in department of applied physics from Tokyo University of Science, Tokyo, Japan, in 2002, and the M.E. degree in Department of Advanced Applied Electronics, Tokyo Institute of Technology, Yokohama, Japan in 2004. Since 2004 he has been with NEC Electronics Corp., Kanagawa, Japan, where he has been developing dynamic IR-drop analysis environment.

Masaaki Soda was born in Fukuoka, Japan in 1964. He received the B.S. and M.S. degrees in electronics engineering from the Kyusyu University, Fukuoka, Japan, in 1988 and 1990, respectively. He joined NEC Corporation in 1990. He is now working on analog circuits design at Core Development Division in NEC Electronics. Mr. Soda is a member of the Institute of Electronics, Information and Communication Engineers of Japan.

Satoshi Goto was born in Hiroshima, Japan, 1945. He received the B.E. and the M.E. degrees in Electronics and Communication Engineering from Waseda University in 1968 and 1970 respectively. He also received the Dr. of Engineering from the same University in 1981. He joined NEC Laboratories in 1970 where he worked for LSI design, Multimedia system and Software. Since 2003, he has been Professor of Waseda University at Kitakyushu whose interests include LSI design and multimedia applications. He is IEEE Fellow and Member of Academy Engineering Society of Japan.

Koutaro Hachiya was born in Miyagi, Japan on March 31, 1968. He received the B.E. and M.E. degrees in computer science from Tohoku University in 1990 and 1992, respectively. From 1992 to 2002 he was with NEC Corp., Kanagawa, Japan, where he developed in-house circuit simulation tools. From 1998 to 1999 he was a visiting scholar at Kiel University, Germany. Since 2002 he has been with NEC Electronics Corp., Kanagawa, Japan, where he has been developing Chip-Package-Board co-design environment. His research interest include computational electronics, especially circuit simulation and interconnect modeling. He is a member of IPSJ, IEEE, ACM, and SIAM.

Takayuki Ohshima received the B.E. and M.E. degrees, both in computer science, from Gunma University, Kiryu, Japan, in 1995 and 1997, respectively. He is currently in the Design Engineering Division at NEC Electronics Corporation, Kawasaki, Japan. His research interests are power grid analysis and timing analysis in digital integrated systems.