Aurasemi’ AU5508 (IEEE1588 Network Synchronizer) +

“AuraSync” (High Performance Servo)

Solution Introduction and Test Results
July 2022

AURASEMI CONFIDENTIAL 1
 Aurasemi IEEE1588 Network Synchronizer + “AuraSync”Servo Solution

• Aurasemi’s Network Synchronizer + “AuraSync” Servo offer the best-in-class

total solution for PDV mitigation in real-life network scenarios Network Synchronizer + “AuraSync” Servo
• Customer has freedom in which IEEE1588 stack to use
– Aurasemi solution can be customized to fit with the Customer’s choice
of IEEE-1588 stack requiring very little modification IEEE1588 Stack “AuraSync” PDV Mitigation Servo
– Customer can choose to use an open-source PTP stack like ptp4l (e.g.,
PTP Stack
with Linux PTP v3.1.1) Full Timing Support Partial Timing Support
• Aurasemi’s device driver makes the adoption simple
– Aurasemi devices have special features that may not be exercised by
conventional (e.g., ptp4l) servo and associated clock control
mechanisms. These can be utilized by the Aurasemi servo/PLL driver
and can be customized for the customer’s architecture. TCP/IP/UDP
– Aurasemi Network Synchronizer can be used with other PTP solutions
such as those from open-source or customer’s proprietary development.
Ethernet Driver Device Drivers (kernel)
• Currently supporting T-BC and Slave modes in the following networks
– Full Timing Support with/without SyncE
– Partial Timing Support (most prevalent to PDV) Peripheral Interface
• Available compliance results Software
– ITU-T G.8261 (frequency and phase) Hardware
– ITU-T G.8273.2 PHY/MAC with Aura AU550x
• PLL
Future planned features Timestamp and TOD Clock Synthesizer and SyncE
– ITU-T G.8273.4 Assisted Partial Timing Support/GNSS-PTP Switching
– T-GM

AURASEMI CONFIDENTIAL 2
 Top Level View of Aurasemi’s IEEE1588 Demo System
General Computing
1588 Stack on Host Processor:
OS, Applications, etc.
1. Demo system uses ptp4l in LinuxPTP Version 3.1.1

1588 Servo that works with Aurasemi Au55xx PLLs:

Aurasemi 1. Can be configured for Full On-Path support or for
Partial On-Path Support.
PTP Servo 2. Leverages properties of IEEE-1588-2019
PTP Stack 3. Architected so that User can choose to use a
(S/W)
proprietary stack or an open-source stack
(customization is simple and straightforward)

PLL Driver translates DCO commands to appropriate low-

PLL Driver
Time-Stamping level hardware commands (e.g., SPI or I2C)
(S/W)
1. Driver agnostic to the specific choice of stack

PLL Key parameters of Demo System:

PHY MAC 1. Ethernet link rate: 1Gbit/s
(H/W)
2. Time-stamping granularity: 8ns
3. Oscillator: OCXO
Other OSC
GNSS Key Performance Characteristics:
Ref.
1. Full On-Path Support case achieves near-Class C
(G.8273.2) with time-stamping granularity of 8ns.
2. Time-stamping granularity of 4ns (or better) will
Demo System based on NXP LS1021A DevKit achieve Class D and improve margin for Class C
1588 stack based on ptp4l in LinuxPTP v3.1.1

AURASEMI CONFIDENTIAL 3
 Test Set Up

House Reference (GPS-based) • House Reference with GPS as Master

Timing Reference
10MHz Reference
• Calnex Paragon as PTP Master and
Calnex Paragon SyncE Master
Meas
PTM-M • PDV added using Anue 3500 for network
emulation (G.8261 tests)
1GE

• Primary measurement based on 1pps

Anue
3500
output of the Demo System
1GE 1pps
• Secondary measurement of output clocks
Demo System (10MHz) from PLL possible using the
(NXP LS1021A Motherboard + capability of the Anue 3500
AU5508 DPLL “Add-On” card)

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 TEST CASES SUMMARY
Test Name Parameters Standard Option Status

G.8262 1&2

Wander Generation G.8262.1 -

G.8273.2 -

G.8262 1&2

Wander Tolerance MTIE, TDEV G.8262.1 1&2

G.8273.2 -

G.8262 1&2

Wander Transfer G.8262.1 1

G.8273.2 -
Pass
Wander Transfer TDEV stratum 3 TDEV G.8262 2

G.8262 1&2
Short Term Phase Transient TIE
G.8262.1 -

G.8262 1&2
Long Term Phase Transient TIE, MTIE
G.8262.1 -

Short Term Phase Transient (Input gapped clock) G.8262 1

MTIE, TDEV G.8262 1&2

Phase Discontinuity *Board configurations :
G.8262.1 - XO 54M LFF 8pF Crystal - Doubler enabled
OCXO 12.8M SMA100(R&S) RF source
Transient Response TIE G.8273.2 - FIN 10M From Calnex Paragon
FOUT 10M 5508 output
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 G.8273.2 Test Results Zoom In
TEST Class C Limit Measured Comments
Noise Generation. Max|TE| 30ns <20ns Meets Class C
Noise Generation. Max(TEL| 5ns (Class D) 6.1ns (mean value nonzero!)* Borderline Class D (see Note 1)
Noise Generation. LF MTIE <10ns (τ ≤ 1 000) 10.06ns (τ ≤ 1 000) Borderline Class C
Noise Generation. TDEV <2ns (τ ≤ 1 000) ~2ns (τ ≤ 1 000) Borderline Class C
Noise Tolerance PASS
Wander Tolerance PASS
Noise Transfer PASS
Wander Transfer PASS
Transient Response PASS
Holdover PASS (LF MTIE < 10ns (τ ≤ 1 000))
Notes:
1. Lowpass filtered TE had mean value of 1.7ns. Perfect asymmetry calibration would change max|TEL| to 5.03ns (borderline Class D) (see asterisk).
2. Demo system used 8ns time-stamping granularity. Finer granularity (e.g., 4ns) would achieve Class C and specified Class D performance (Class D has multiple
requirements that as “for further study”).
3. Demo system time-stamping is at the MAC layer. Better performance achievable with PHY layer time-stamping.

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 Recommended Customer Hardware Architecture

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 Aurasemi IEEE1588/SyncE Reference Design
with LS1021A Tower System Module
• AU5508 IEEE 1588 Network Synchronizer generates ultra-low jitter reference clocks
for various critical components in the system as well as precision timing signals for
Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE)

• PTP time synchronization is achieved by adjusting Digitally Controlled Oscillators

(DCOs) available in AU5508 by a companion “AuraSync” 1588 servo software
running on LS1021A processor

• “AuraSync” 1588 servo algorithm supports statistical packet selection specially

designed to mitigate Path Delay Variation (PDV) effects

• ITU-T G.8262, G.8261 and G.8273.2 compliant

• 1588 Class-C compliant solution (cTE < +/- 10nS)

• LS1021A Tower System Module is available for purchase from: Layerscape LS1021A
Tower® System Module | NXP Semiconductors

• AU5508 Add-on Card and “AuraSync” software demo version is available from
Aurasemi by contacting our sales representatives

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 Summary
• “AuraSync” Servo is a proprietary control software specially designed to mitigate Path Delay
Variation (PDV) in open wireless front-haul networks as well as next generation data centers
requiring precise time synchronization

• “AuraSync” Servo can be plug-and-play with Linux PTP open-sourced stack or other custom stack

• “AuraSync” Servo is available in binary form through a royalty-free license as long as it’s used
together with Aurasemi’s 1588 Network Synchronizer device such as AU5508 or other devices
supporting “AuraSync”

• Other license and commercial arrangements are available upon mutual agreement with Aurasemi

• Demo system (NXP LS1021A Motherboard + AU5508 PLL “Add-On” card) is available upon request

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