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AN INVERTER – SCHEMATIC DESIGN

Table of components for building the schematic Library name gpdk180 gpdk180 Cell Name pmos nmos Properties W=2u, L=180n W=2u, L=180n

INVERTER TEST CIRCUIT USING INVERTER SYMBOL

Table of components for building the Test schematic Library name analogLib analogLib Cell Name vpulse vdc, gnd Properties V1=0, V2=1.8, Period=20n, Pulsewidth=10n Vdc=1.8

ANALOG SIMULATION WITH SPECTRE FOR INVERTER

Table of values to setup for different analysis Analysis name Transient Settings tran DC Analysis Sweep Variable Component Parameter Sweep Rage Start-Stop Sweep 1 Range Type Step Control Properties Stop time = 200n , moderate Save DC Operating Point Component Name=Select input signal component (Name of Vpulse) Parameter Name =dc Start = 0, Stop = 1.8 Variable Name = wp From=1u, To=10u Total Steps=10

DC

Parametric

AN INVERTER – LAYOUT DESIGN

Table of components for building the Layout Connection Metal1 Poly Metal 1 Psubstrate Metal1 Nwell Contact Type Metal1 - Poly Metal1 – Psub Metal1 – Nwell

COMMON SOURCE AMPLIFIER – SCHEMATIC DESIGN

Table of components for building the schematic Library name gpdk180 gpdk180 Cell Name pmos nmos Properties W=50u, L=1u W=10u, L=1u

CS AMPLIFIER TEST CIRCUIT USING CS AMPLIFIER SYMBOL

Table of components for building the Test schematic Library name analogLib analogLib Cell Name vsin vdc, gnd Properties AC Magnitude = 1; DC Voltage=0; Offset Voltage=0; Amplitude=5m or 5u; Frequency=1K VDD : vdc = 2.5; VSS : vdc = -2.5

Stop = 5 Start = 100.ANALOG SIMULATION WITH SPECTRE FOR CS AMPLIFIER Table of values to setup for different analysis Analysis name Transient Settings tran DC Analysis Sweep Variable Component Parameter Sweep Range Start-Stop Sweep Range Start-Stop Sweep Type Properties Stop time = 5m . moderate Save DC Operating Point Component Name=Select input signal component (Name of VSIN) Parameter Name =dc Start = -5. Stop = 100M Automatic DC AC .

COMMON SOURCE AMPLIFIER – LAYOUT DESIGN .

L=1u .COMMON DRAIN AMPLIFIER – SCHEMATIC DESIGN Table of components for building the schematic Library name gpdk180 gpdk180 Cell Name nmos nmos Properties W=50u. L=1u W=10u.

Offset Voltage=0. Amplitude=5m or 5u. Frequency=1K VDD : vdc = 2. DC Voltage=0. gnd Properties AC Magnitude = 1.5. VSS : vdc = -2.CD AMPLIFIER TEST CIRCUIT USING CD AMPLIFIER SYMBOL Table of components for building the Test schematic Library name analogLib analogLib Cell Name vsin vdc.5 .

moderate Save DC Operating Point Component Name=Select input signal component (Name of VSIN) Parameter Name =dc Start = -5.ANALOG SIMULATION WITH SPECTRE FOR CD AMPLIFIER Table of values to setup for different analysis Analysis name Transient Settings tran DC Analysis Sweep Variable Component Parameter Sweep Rage Start-Stop Sweep Rage Start-Stop Sweep Type Properties Stop time = 5m . Stop=100M Automatic DC AC . Stop = 5 Start=100.

COMMON DRAIN AMPLIFIER – LAYOUT DESIGN .

L=1u (PM0.5u. L=1u (NM2. NM3) . L=1u (NM0. NM1) W=4.DIFFERENTIAL AMPLIFIER – SCHEMATIC DESIGN Table of components for building the schematic Library name gpdk180 gpdk180 gpdk180 Cell Name pmos nmos nmos Properties W=15u. PM1) W=3u.

gnd Idc Properties AC Magnitude = 1. Offset Voltage=0. Amplitude=5m.DIFFERENTIAL AMPLIFIER TEST CIRCUIT USING DIFFERENTIAL AMPLIFIER SYMBOL Table of components for building the Test schematic Library name analogLib analogLib analogLib Cell Name vsin vdc. VSS : vdc = -2.5. Frequency=1K VDD : vdc = 2.5 DC current = 30u . DC Voltage=0.

moderate Save DC Operating Point Component Name=Select input signal component (Name of VSIN) Parameter Name =dc Start = -5. Stop = 5 Start=100.ANALOG SIMULATION WITH SPECTRE FOR DIFFERENTIAL AMPLIFIER Table of values to setup for different analysis Analysis name Transient Settings tran DC Analysis Sweep Variable Component Parameter Sweep Rage Start-Stop Sweep Range Start-Stop Sweep Type Properties Stop time = 5m . Stop=100M Automatic DC AC .

DIFFERENTIAL AMPLIFIER – LAYOUT DESIGN .

L=1u (PM0. L=1u (PM2) W=3u. L=1u (NM0. L=1u (NM4) . PM1) W=50u.5u.OPERATIONAL AMPLIFIER – SCHEMATIC DESIGN Table of components for building the schematic Library name gpdk180 gpdk180 gpdk180 gpdk180 gpdk180 Cell Name pmos pmos nmos nmos nmos Properties W=15u. NM1) W=4. L=1u (NM2. NM3) W=15u.

Amplitude=5u. Offset Voltage=0. DC Voltage=0.5. VSS : vdc = -2. Frequency=1K VDD : vdc = 2. gnd Idc Properties AC Magnitude = 1.OPERATIONAL AMPLIFIER TEST CIRCUIT USING OPERATIONAL AMPLIFIER SYMBOL Table of components for building the Test schematic Library name analogLib analogLib analogLib Cell Name vsin vdc.5 DC current = 30u .

moderate Save DC Operating Point Component Name=Select input signal component (Name of VSIN) Parameter Name =dc Start = -5.ANALOG SIMULATION WITH SPECTRE FOR OPERATIONAL AMPLIFIER Table of values to setup for different analysis Analysis name Transient Settings tran DC Analysis Sweep Variable Component Parameter Sweep Range Start-Stop Sweep Range Start-Stop Sweep Type Logarithemic Properties Stop time = 5m . Stop = 5 Start=100. Stop=100M Points per decade = 20 DC AC .

OPERATIONAL AMPLIFIER – LAYOUT DESIGN .

R-2R DAC – SCHEMATIC DESIGN Table of components for building the schematic Library name gpdk180 gpdk180 analogLib Cell Name polyres Polyres Idc. gnd Properties R = 2k R = 1k Idc = 30u .

Pulsewidth=20u D2: V1=0.5. Period=40u.5 DC current = 30u analogLib analogLib vdc.R-2R DAC TEST CIRCUIT USING R-2R DAC SYMBOL Table of components for building the Test schematic Library name analogLib Cell Name vpulse Properties D0: V1=0. Period=80u.8. gnd Idc . Period=160u. V2=1. Period=20u. Pulsewidth=80u VDD : vdc = 2.8. V2=1.8. VSS : vdc = -2. V2=1. Pulsewidth=40u D3: V1=0. V2=1.8. Pulsewidth=10u D1: V1=0.

moderate .ANALOG SIMULATION WITH SPECTRE FOR R-2R DAC Table of values to setup for different analysis Analysis name Transient Settings tran Properties Stop time = 5m .

R-2R DAC – LAYOUT DESIGN .

in2).Power and Ground Lines output out.in1).DIGITAL SIMULATION AND SYNTHESIS //Define our own And Gate. // Declarations of I/O . in1 .nout). // Declaration of Wires wire contact. wire nout.nout). // Instantiate pmos and nmos switches to form Inv pmos (out.pwr. (nout.pwr.in2).pwr. (contact. supply1 pwr.in1).gnd. nmos (out. (nout. endmodule . in2 ). supply0 gnd. // Instantiate pmos and nmos switches to form Nand gate pmos pmos nmos nmos (nout.gnd. input in1. module andgate ( out .contact.in2.

. in2.// Testbench for And Module module and_test. in1. . out ) . . $time . wire out . . . begin $display ( "time=%0d" " Input1=" " Input2=" " Output=" end endtask // Apply Stimulus initial begin in1 in1 in1 in1 end endmodule . " ns" . . . . = = = = 1'b0 1'b0 1'b1 1'b1 . . . . // Display task display . reg in1. . // Instantiate And Gate Module andgate a1 ( out. . . in1.in2 . . . #10 #10 #10 #10 . in2 ) . display display display display . in2 in2 in2 in2 = = = = 1'b0 1'b1 1'b0 1'b1 .

in1).contact. in1 .Power and Ground Lines output out. input in1. supply0 gnd. // Declaration of Wire wire contact.pwr.//Define our own Nand Gate. // Declarations of I/O . (contact.in2. in2 ). // Instantiate pmos and nmos switches pmos pmos nmos nmos (out. (out.gnd. (out. module nandgate ( out .in2). endmodule .in1). supply1 pwr.pwr.in2).

. . begin $display ( "time=%0d" . #10 #10 #10 #10 . in2 in2 in2 in2 = = = = 1'b0 1'b1 1'b0 1'b1 .in2 . in1. in2 ) . . $time . . " ns" in1 in2 out = = = = 1'b0 1'b0 1'b1 1'b1 . . . " Input1=" . . " Output=" ) . wire out . . . display display display display . .// Testbench for Nand Gate Module module nand_test. . end endtask // Apply Stimulus initial begin in1 in1 in1 in1 end endmodule . // Display task display . . . // Instantiate Nand Gate Module nandgate n1 ( out. . " Input2=" . . reg in1. .

in2. // Declaration of Wire wire contact. in1 . (out.in2). // Declarations of I/O .pwr.gnd.contact.in2).in1). // Instantiate pmos and nmos switches pmos pmos nmos nmos (contact.//Define our own Nor Gate.gnd. module norgate ( out . (out. endmodule .Power and Ground Lines output out. input in1. supply0 gnd. (out. supply1 pwr. in2 ).in1).

. begin $display ( "time=%0d" . " Input1=" . . . . . . . . .// Testbench for Nor Gate Module module nor_test. in2 ) . // Display task display . " Output=" ) . . $time . . in1. #10 #10 #10 #10 . wire out . . display display display display . " ns" in1 in2 out = = = = 1'b0 1'b0 1'b1 1'b1 . . " Input2=" . reg in1. // Instantiate Nor Gate Module norgate n1 ( out. end endtask // Apply Stimulus initial begin in1 in1 in1 in1 end endmodule . .in2 . . in2 in2 in2 in2 = = = = 1'b0 1'b1 1'b0 1'b1 . .

(nout. (nout. wire nout.gnd. in1 .nout).gnd.nout). endmodule . // Instantiate pmos and nmos switches for Nor gate pmos pmos nmos nmos (contact. in2 ).in1).in2). // Declarations of I/O .contact. input in1.gnd.pwr.in1). nmos (out. supply1 pwr. supply0 gnd. // Instantiate pmos and nmos switches for Not gate pmos (out. (nout.in2).pwr.Power and Ground Lines output out.in2. module orgate ( out . // Declaration of Wires wire contact.//Define our own Or Gate.

end endtask // Apply Stimulus initial begin in1 in1 in1 in1 end endmodule . display display display display . . begin $display ( "time=%0d" . in2 ) .in2 . . $time . . in2 in2 in2 in2 = = = = 1'b0 1'b1 1'b0 1'b1 . . . . . wire out . " Input1=" . #10 #10 #10 #10 . reg in1. in1. . " ns" in1 in2 out = = = = 1'b0 1'b0 1'b1 1'b1 . " Input2=" . . . // Instantiate Orgate Module orgate n1 ( out. . . " Output=" ) . // Display task display . . . .// Testbench for Or Gate Module module or_test. .

in1 . input in1.in1).in2bar. in2 ).in2. endmodule .in2. wire in2bar.in2bar). (out.in1.//Define our own XNOR Gate.in2). // Declarations of I/O ports output out.in1. module xnorgate ( out .in1). // Instantiate pmos and nmos switches : pmos nmos pmos nmos (out. (out. (out. assign in2bar = ~in2.

wire out . " Input2=" . $time .in2 . . . begin $display ( "time=%0d" . end endtask // Apply Stimulus initial begin in1 in1 in1 in1 end endmodule . . . . // Display task display . . . in1. . " Input1=" . . . display display display display . in2 in2 in2 in2 = = = = 1'b0 1'b1 1'b0 1'b1 . . . .// Testbench for Xnor Module module xnor_test. // Instantiate Xnor gate Module xnorgate x1 ( out. . " Output=" ) . " ns" in1 in2 out = = = = 1'b0 1'b0 1'b1 1'b1 . #10 #10 #10 #10 . . in2 ) . reg in1. .

in2).in1.in1.in2. (out. // Declarations of I/O ports output out.in2. in1 .in1). module xorgate ( out .in2bar). endmodule . (out. (out. wire in2bar.in1). in2 ). assign in2bar = ~in2.//Define our own XOR Gate. input in1. // Instantiate pmos and nmos switches : pmos nmos pmos nmos (out.in2bar.

begin $display ( "time=%0d" . // Display task display . . . . . #10 #10 #10 #10 . . . in1. . in2 ) . . . $time . . display display display display . . . end endtask // Apply Stimulus initial begin in1 in1 in1 in1 end endmodule . . in2 in2 in2 in2 = = = = 1'b0 1'b1 1'b0 1'b1 .in2 . reg in1. . . " Input2=" . wire out . " Output=" ) . " ns" in1 in2 out = = = = 1'b0 1'b0 1'b1 1'b1 .// Testbench for Xor Module module xor_test. // Instantiate Xorgate Module xorgate x1 ( out. . " Input1=" .

nmos (out.in). input in.in).pwr.gnd. // Declarations of I/O . endmodule . in ). module inverter ( out .Power and Ground Lines output out. // Instantiate pmos and nmos switches pmos (out. supply1 pwr. supply0 gnd.//Define our own Inverter.

in . . . end endtask // Apply Stimulus initial begin in = in = in = in = end endmodule 1'b0 1'b1 1'bx 1'bz . " Output=". wire out . . . . #10 #10 #10 #10 . " ns" .// Testbench for Inverter Module module inv_test. . . reg in . in ) . . out ) . . $time . . // Display task display . begin $display ( "time=%0d" . " Input=" . display display display display . // Instantiate inverter Module inverter i1 ( out.

inverter i2 (out. // Wire Declaration wire a. input in.a).Power and Ground Lines output Y. supply0 gnd.pwr. (BUFFER) module inverter ( Y. endmodule . // Instantiate Inverter module inverter i1 (a. in ).in).gnd. // Declarations of I/O . A ). supply1 pwr.A). // Declarations of I/O Lines output out. endmodule // Define our own Buffer module buffer ( out.//Define our own Inverter. nmos (Y. // Instantiate pmos and nmos switches pmos (Y.A). input A.

begin $display ( "time=%0d" . display display display display . . " Input=" . out ) . // Display task display . . reg in . . #10 #10 #10 #10 . . . // Instantiate Buffer Module buffer b1 ( out.// Testbench for Buffer Module module buf_test. . " Output=". $time . end endtask // Apply Stimulus initial begin in = in = in = in = end endmodule 1'b0 1'b1 1'bx 1'bz . in . " ns" . . in ) . . . . wire out .

// Declarations of I/O and Control Lines output out. endmodule .cntrl2).//Define our own Transmission Gate.in. nmos (out. // Instantiate pmos and nmos switches pmos (out. module trangate ( out . cntrl1.cntrl2. input in. cntrl2 ).cntrl1).in. in . input cntrl1.

// Display task display . . in. . . . . " Control2=". . $time . " Output=". out . .cntrl1 . cntrl1. " ns" . . cntrl2 ) .// Testbench for trangate Module module trangate_test. #10 #10 #10 #10 . . wire out . // Instantiate trangate Module trangate t1 ( out. in . .cntrl2. begin $display ( "time=%0d" . cntrl2 cntrl2 cntrl2 cntrl2 = = = = 1'b1 1'b0 1'b1 1'b0 . " Control1=". " Input=" . . . cntrl1 cntrl1 cntrl1 cntrl1 = = = = 1'b0 1'b1 1'b0 1'b1 .cntrl2 ) . . end endtask // Apply Stimulus initial begin in = in = in = in = end endmodule 1'b0 1'b0 1'b1 1'b1 . reg in . . . . display display display display . reg cntrl1.

else q <= din. n_rst=1'b1. end endmodule // Testbench for D-Flip Flop Module module dff_test.#10. din=1'b0.q).din. task display. wire q. always @(posedge clk or negedge n_rst) begin if(!n_rst) q <= 1'b0.din. input clk.din=1'b1.#10.clk.din=1'b1.#10. end initial #70 $finish.din)." din=".display. reg clk.clk. begin $display("time=%0d".//Define our own D-Flip Flop Module module d_ff(q.n_rst.din). initial begin n_rst=1'b0.n_rst. reg q. " n_rst=".$time. end endtask initial clk = 1'b0.n_rst.din=1'b1. output q.display.din. n_rst=1'b1. endmodule .#10.din=1'b1. n_rst=1'b0. display.display.display.display. always #5 clk = ~clk. din=1'b1. d_ff inst(q."ns"." q=".#10.n_rst.n_rst.#10.

rst. end else begin if (j == 1'b1 && k == 1'b0) begin q <=1'b1.k). end else if (j == 1'b1 && k == 1'b1) begin q <=~q. always @(posedge clk or negedge rst) begin if (!rst) begin q <= 1'b0. end else if (j == 1'b0 && k == 1'b1) begin q <=1'b0 .//Define our own JK-Flip Flop Module module jk_ff(q.j.j.rst.qbar.k. reg q. input clk.qbar. output q.clk. end end end assign qbar=~q. endmodule .

#10.j." k=". j=0. begin $display("time=%0d".display.#10.k.#10.qbar)." q=".display. task display.k=0. end initial #70 $finish. endmodule .#10.display.rst. jk_ff inst(q.k). j=1.$time.display." qbar="."ns".k=0. initial begin rst=0.k=1.clk.display.j=1. rst=1.j=1. wire q. end endtask initial clk = 1'b0. #10. " rst=".j.#10." j=".k=1.// Testbench for JK-Flip Flop Module module jk_ff_test.qbar.j.rst. reg clk.rst.k=0.q.k=1. j=1. always #5 clk = ~clk.k.#10.qbar. j=0.display.

q1.//Define our own MS D-Flip Flop Module module ms_dff(q2.clk. input clk. reg q1.d).q1. output q2.d.q2bar.q2bar. endmodule . end else if(!clk) begin q2 <= q1. end end assign q2bar=~q2.q2. always @(clk) begin if (clk) begin q1<=d.

" q2=". reg clk.q2bar.clk.display.display.q1.q1.display."ns". #5." time=%0d"." q2bar=". " clk=".d).display. initial d=1'b0. end initial #70 $finish." q1=". #5. #10 .q2. task display.$time. wire q2. always #18 d=~d.// Testbench for MS D-Flip Flop Module module msdff_test. #5. #5. #5. ms_dff inst(q2. begin $display(" d=". always #5 clk = ~clk.display.d.display. initial begin #5.display. end endtask initial clk = 1'b1.q2bar. #5. #5. #5.clk. #5.display.display.q2bar).display.display. #5.q1.d. endmodule .

rst). else if q else if q else if q else if q (s <= (s <= (s <= (s <= == 1'b0 q.s. && r == 1'b0) && r == 1'b1) && r == 1'b0) && r == 1'b1) end //assign q = tq.r. input clk. output q. endmodule .rst. == 1'b1 1'b1. assign qbar = ~q. always @(posedge clk or negedge rst) begin if (!rst) q <= 1'b0.r.qbar.qbar. == 1'b1 1'bx.//Define our own SR-Flip Flop Module module sr_ff(q. reg q. == 1'b0 1'b0.clk.s.

end endtask initial clk = 1'b0. rst=1.display. s=1.s=1.r=1.r=1.s.#10. " rst=". wire q.r.#10." q=".$time.#10.s. end initial #70 $finish. always #5 clk = ~clk.display. s=0.qbar.qbar. endmodule .rst.#10.display. begin $display("time=%0d". sr_ff sr1(q.q.qbar)."ns".r=0.r.display.clk." qbar=". s=0.s=1." r=".r=0.r=0." s=".r.// Testbench for SR-Flip Flop Module module sr_ff_test.rst).#10. task display.rst. reg clk.display.s. initial begin rst=0.

rst). endmodule ." tin=". input clk. end end assign q = tq.qbar.tin. tin = 1'b1. task display. begin $display("time=%0d".display. end endtask initial clk = 1'b0.display.qbar. rst=1'b0.#10. always @(posedge clk or negedge rst) begin if(!rst) tq <= 1'b0. t_ff t1(q.rst. else begin if (tin) tq <= ~tq.#10.display.#10.display. reg tq. end initial #100 $finish.$time.//Define our own T-Flip Flop Module module t_ff(q. output q.rst.qbar.tin=1'b1.#10.display. assign qbar = ~q.tin. wire q. initial begin rst = 1'b0.tin. rst=1'b1. " rst=".qbar.rst.#10.tin. endmodule // Testbench for T-Flip Flop Module module tff_test.rst).tin=1'b1. tin = 1'b0.tin. rst = 1'b1.display.tin=1'b1. tin = 1'b1.q. always #5 clk = ~clk. #10 .#10.clk." qbar=".qbar).#10.clk. reg clk.display."ns"." q=".tin=1'b0.

rst.cnt). tff T2(cnt[2].rst. tff T1(cnt[1]. input clk. endmodule module tff(q."output q=%h". output [3:0]cnt. end initial $monitor($time. tff T3(cnt[3].rst. always@(negedge clk or posedge rst) begin if(rst) tq<=1'b0. initial begin rst=1'b1. reg clk.rst. endmodule // Testbench for Ripple Counter Module module ripcount_test.rst. endmodule .clk. else tq<=~tq.cnt). #10 rst=1'b0.cnt[0]. reg tq.rst).rst). input clk. always #5 clk =~clk. wire [3:0]cnt. ripcount r1(clk. initial clk=1'b0. #200 $finish. tff T0(cnt[0]. end assign q=tq.rst).rst).clk.cnt[1].//Define our own Ripple counter Module //RIPPLE COUNTER module ripcount(clk.cnt). output q.cnt[2].rst).

//Define our own Synchronous Counter Module module counter_behav ( count. output reg [3:0] count. endmodule // Testbench for Synchronous Counter Module module sycounter_t . . endmodule "Output count = %d ". else count <= count + 4'b0001. wire [3:0] count. end initial $monitor ($time.reset. always @(posedge clk) if (reset) count <= 4'b0000. counter_behav m1 ( count.reset.clk). initial clk = 1'b0. #30 reset =1'b0. #200 $finish.clk). initial begin reset = 1'b0 . reg reset. input wire reset. clk. #15 reset =1'b1.count ). always #5 clk = ~clk.clk.

c. wire a. c1). wire c1. #20 x =4'b1111. wire [3:0] sum. c_out. fulladder fa1(sum[1]. c1. y). c_in). y[1]. FourBitAdder a1 ( sum. x[1]. c_in). a. c_in). c_out. c_in).c_out. c2. . y= #20 x =4'b1111. c_out. reg [3:0] x. c_out. y = 4'b1010. and (c. output c_out. xor (a.y. y[3]. fulladder fa3(sum[3]. y =4'b0110. b). fulladder fa0(sum[0]. y). x. c_in). c2. #20 x =4'b1011. x. x[3]. and (b. y. input c_in. y. c3. fulladder fa2(sum[2]. c_in. input x.c_in = 1'b0. c3. endmodule //********* 4-Bit Adder ********************** module FourBitAdder(sum. y[0]. b. or (c_out. x. xor (sum. wire c_out. c2). initial begin x = 4'b0000. x[2]. endmodule // Testbench for Parallel Adder Module module adder_t . x. c. input [3:0] x.//Define our own Parallel Adder Module //** ******Full Adder ****************** module fulladder(sum.x. end endmodule 4'b0000. x[0]. output [3:0] sum.c_in). y[2]. y. y=4'b1111. reg c_in. #80 $finish. y. output sum. a. c3).y.

parallel [7:1]}. start. end else begin // adding {carry_out. reg [7:0] parallel.//Define our own Serial Adder Module module serial_adder2 (a. reg serial_sum. reg [3:0] count. clock. //shifting if(counting) parallel = {serial_sum. always @(negedge clock) begin if(start) begin count = 3'b0.serial_sum} = a + b + carry_in . output [7:0] result. counting = 1'b1. input a. parallel = 8'b0. b. // counting if (count==limit-1) counting = 0. carry_in. ready. output ready. carry_in = carry_out. start. else . clock. carry_out. counting. carry_in = 1'b0. parameter limit = 8. b. result).

b. clock. #05 start = 1'b1. a = 1'b0.1 b = ~ b. end always #2 clock = ~ clock. b. start.counting = 1. initial begin clock = 1'b1. endmodule . if (count < limit-1) count = count + 1. assign result = parallel . endmodule // Testbench for Serial Adder Module module test_serial_adder2. #54 $finish. b = 1'b1. always #5. clock. #11 start = 1'b0. end end assign ready = ~ counting. start.1 a = ~ a. always #3. result). wire [7:0] result. ready. serial_adder2 u1(a. wire ready. reg a.

indata.start. end else begin if(convert) begin outdata[limit-i]=1'b1. reg [7:0]outdata.j. res=0. convert=1'b1. end if(res>indata) outdata[limit-i]=1'b0. input clk. assign bindata=outdata.//Define our own Successive Approximation Register Module module sar(clk. else convert=1. reg convert. if(i>limit+1) convert=0. always@(negedge clk) begin if(start) begin outdata=8'b0.j=j+1) begin if(outdata[j]==1) res=res+2**j. integer i. integer res.ready. end i=i+1. i=1.bindata).j<=7. endmodule . output ready. output [7:0]bindata.start. input [31:0]indata. parameter limit=8. for(j=0. end end assign ready=~convert.

sar s(clk. endmodule .ready. reg clk. #11 start=1'b0. reg [31:0]indata. reg start.indata. wire [7:0]binout.// Testbench for Successive Approximation Register Module module sar_t. #50 $finish. indata=170.start.binout). end always #2 clk=~clk. #05 start=1'b1. initial begin clk=1'b1.