A MINI PROJECT REPORT ON

IMPLEMENTATION OF MEMORY BUILT-IN SELF TEST USING VERILOG

Submitted by ERASANI CHAMIKAR (ROLL NO: 097B1A0417)

In partial fulfillment for the award of the degree of BACHELOR OF TECHNOLOGY IN ELECTRONICS & COMMUNICATION ENGINEERING

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SAGAR INSTITUTE OF TECHNOLOGY (SITECH) SAGAR GROUP OF EDUCATIONAL INSTITUTIONS

A PROJECT REPORT ON

IMPLEMENTATION OF MEMORY BUILT-IN SELF TEST USING VERILOG

Submitted in partial fulfillment of the requirement for the award of the degree of BACHELOR OF TECHNOLOGY IN ELECTRONICS & COMMUNICATION ENGINEERING BY ERASANI CHAMIKAR (ROLL NO: 097B1A0417) (2009-2013) Under The Esteemed Guidance Of Mr. SRI SHAILAM .K Asst.Professor

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SAGAR INSTITUTE OF TECHNOLOGY (SITECH)

S V V R EDUCATIONAL SOCIETY GROUP OF INSTITUTIONS
Flame of Forest, Chevella- Urella Road, Urella(V), Chevella (M), RR Dist-501504, A.P.

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DECLARATION
We submit this project work entitled " IMPLEMENTATION OF MEMORY BUILT-IN SELF TEST USING VERILOG" to SAGAR INSTITUTE OF TECHNOLOGY, Chevella, Hyderabad in partial fulfillment of the requirements for the award of the degree of "Bachelor of Technology' in "Electronics and Communication Engineering". We declare that it was carried out independently by us under the guidance of sri ashailam, Asst.Professor Sagar Institute Of Technology (Sitech), Hyderabad, India.

ERASANI CHAMIKAR (ROLL NO: 097B1A0417)

Date : Place: Hyderabad

signature:

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SAGAR INSTITUTE OF TECHNOLOGY (SITECH)

SAGAR GROUP OF EDUCATIONAL INSTITUTIONS
Flame of Forest, Chevella- Urella Road, Urella(V), Chevella (M), RR Dist-501504, A.P.

Certificate

This is to certify that the project report entitled IMPLEMENTATION OF MEMORY BUILT-IN SELF TEST USING VERILOG being submitted by Mr ERASANI CHAMIKAR in partial fulfilment for the award of the Degree of Bachelor of Technology in
ELECTRONICS AND COMMUNICATION ENGINEERING to the Jawaharalal Nehru

Technological University is a record of bonafied work carried out by him under my guidance and supervision. The results embodied in this project report have not been submitted to any other University or Institute for the award of any Degree or Diploma.

Internal Guide
Mr. SRI SHAILAM .K Asst.Professor

HOD
Mr. B. PRABHAKAR RA

Professor

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ACKNOWLEDGEMENT
With great pleasure we want to take this opportunity to express our heartfelt gratitude to all the people who helped in making this mini project work a grand success We express my deep sense of gratitude to Mr. Vamshi for his constant guidance throughout our mini project work. W e g r a t e f u l t o Mr. K. Sri Shailam for his valuable suggestions and guidance given by him during the execution of this mini project work. We would like to thank Prof. B. PRABHAKAR RAO , Head of the Department of Electronics and Communication Engineering, for being moral support throughout the period of the study in SITECH.

First of all I am highly indebted to Principal Dr.V.V.Satyanarayana, for giving me the permission to carry out this mini project.

WewouldliketothanktheTeaching&NonTeachingstaffofECE Department for sharing their knowledge with us.

Last but not the least I express my sincere thanks to Sri S. Veera Reddy Chairman and Dr.W.R Reddy Secretary , SAGAR Group of Institutions for their continuous care towards my achievements.

ERASANI CHAMIKAR (ROLL NO: 097B1A0417)

ABSTARCT
To test and the semiconductor memories for Faults. In this project we test RAM for finding out faulty locations. Memories are one of the most universal cores. On average embedded RAMs occupy 90% area in system-on-chip (SOC), so embedded memory test design has become an essential part of the SOC development infrastructure. In this project we implement memory built in self test (MBIST) engine for memory test. A simple architecture for built in self test is implemented which works independent of any MBIST algorithm. Todays deep submicron technologies allow the implementation of multiple memories on a single chip Due to their high density memories is more prone to faults. These faults impact the total chip Yield.
The memory is tested by external test hardware or by on chip dedicated hardware (memory BIST). The second testing strategy is the preferred method for embedded memories.

SOC consists of many memory models. Like, SRAM, FLASH, ROM etc, we consider here only SRAM type of memory core. In this section we will see what the functional model of SRAM is and what types of Functional Faults, Fault Models and Defects exist in SRAM cores due to process variation and manufacturing. SRAM consists of Many sub functional models, fault can be anywhere in the sub modules. Faults can be existing in address decoder logic, cell array, write driver etc.

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LIST OF FIGURES

Fig. No _____________________ Name of the Figure___________________________ Page No. 2.1(a) 2.1(b) 2.2.2(a) 2.2.2(b) 2.2.3 3.1 3.2(a) 3.2(b) 6.2 6.3 6.6 8(a) 8(b) 8(c) 8(d) 8(e) 9.1(a) 9.3(a) 9.3(b) 9.3(c) 9.3(d) A simple digital figure Sequence of steps in conventional electric circuit design Design domain and levels of abstraction Major actives in ASIC design ASIC design and development flow Basic functional model of RAM Stuck at fault Transition fault Memory cores on SOC Block diagram of Memory BIST Architecture of MBIST Device properties window of Xilinx ISE Verilog source tile window Source file containing counter module window Simulation waveforms Programming file generation Simulation result RTL schematic view RTL schematic view Technology schematic view Technology schematic view 3 4 7 7 8 12 13 13 20 21 22 27 28 28 31 32 37 47 47 48 48

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NOTATIONS/ABBREVATIONS
a<b a>b a<=b a>=b a === b a !== b a == b a != b ! && || ~ & | ^ ^~ or ~^ ~& ~| ^ ^~ or ~^ << >> + ?: a less than b a greater than b a less than or equal to b a greater than or equal to b a equal to b, including x and z
a not equal to b, including x and z a equal to b, resulting may be unknown a not equal to b, result may be unknown

logic negation logical and logical or negation and inclusive or exclusive or exclusive nor (equivalence nand nor xor
xnor

left shift right shift Add Subtract Conditional

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* / % VLSI ASIC HDL RTL VHDL

Multiply Divide Modulus very large scale integration application specified integrated circuit hardware description language Register Transfer Level
Very high-speed integrated circuit hardware description language

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CONTENTS Title
Abstract
LIST OF TABLE

Page.no
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LIST OF FIGURES 1.Introduction 1.1.1 VLSI 1.1.2 Conventional approach to digital design 2. VLSI Desig 2.1 Abstraction Model 2.2 ASIC design flow 2.3 Design description 2.4 Optimization 2.5 Synthesis 2.6 Physical design 2.7 Post layout simulation 2.8 Role of HDL 3.Memories and memory fault analysis 3.1 Basic function model of RAM core 3.2 Fault analysis 3.3 RAM test algorithm
4.Design for testability 5.Built In Self Test (BIST) 5.1 Why BIST.? 5.2 BIST techniques 5.3 Advantages in implementing BIST

5.4 Disadvantages in implementing BIST 6.Memory Built In Self Test (MBIST) 6.1 Why MBIST.? 6.2 Various MBIST algorithm 6.3 Ideal implementation of MBIST 6.4 Block diagram 6.5 Architecture 7.HDL
7.1 Verilog 8.XILINX ISE 9.Coading and Results 9.1 Simulation Results 9.2 Synthesis Report 9.3 Synthesis Results
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Conclusion & Future scope Bibliography

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