UNIVERSITY college OF engineeringariyalur

An Embedded Communication Network System Based on Quantum Cryptography Communication SUBMITTED BY

R.ARIVAZHAGAN, EEE-THIRD YEAR,

A.KUMARAVEL, EEE-THIRD YEAR, velurx@gmail.com , 8870080097.

arivu.mvl@gmail.com, 8098522707.

Abstract
A set of embedded communication network system is constructed according to the reality requirement of quantum cryptography communication to achieve dynamic data transmission. The software and hardware synergy design method is adopted to construct network communications system based on MicroBlaze with EDK and FPGA board as embedded Web server. Furthermore, Gauss random number IP core is designed to generate random number. Such system could be used for high speed and long-distance data transmission on two PC machines and FPGA board to achieve data coordination in quantum cryptography communication.

Introduction
It is increasingly urgent to establish real and safe information confidentiality system along with continuous advancement of society informatization. The quantum cryptography communication is a kind of new communication technology developed in recent thirty years and the only communication way recognized in the science field to achieve

absolute security. Therefore, it is hoped to establish quantum cryptography information system in the globe. In order to change the quantum cryptography to be practical cryptosystem for encrypting data in the communication, there are higher requirement for key length and quantity as well as accuracy of transmission data. Thus, it is important to deal with after communication with bidirectional classic channels in order to obtain safe key. The data post-processing is including data screening, error rate estimate, data coordination error correction and confidentiality intensifying, etc. EDK is used to construct a network communication system based on MicroBlaze to generate random number in the cryptography communication with FPGA hardware and transfer random number through internet. In the communication process, two PC machines are installed as sender and receiving side of network communication client side respectively in client/server mode and FPGA board as embedded Web server to connect two PC machines and FPGA board to Internet. The quantum cryptography data

coordination is conducted on the established embedded communication network to greatly improve data coordination efficiency.

that, (2)~(4) is data processing in classic channel. The Communication system is designed to complete that data processing.

Quantum Cryptography Communication Process

Quantum cryptography communication includes four steps: (1) quantum information transmission is achieved through quantum channel; (2) both communication parties must screen required results and calculate error rate after obtaining quantum transmission result. If the established error rate is exceeded, telephone tapping is considered that both parties could give up all data and start again. If the established error rate is not exceeded, both parties store the screened data. The obtained data is called screened data; (3) error correction for the original data is required on the condition that both communication parties still could not guarantee the whole data stored respectively has no error after screening. This process is also called as data coordination; (4) confidentiality intensifying. It is a necessary measure to further improve safety and confidentiality of the obtained key book. Among

Embedded Communication Network Construction

A set of embedded network communication system is designed to satisfy for data post processing requirement in quantum cryptography communication. It is an embedded communication network composed of hardware system based on MicroBlaze soft core processor and a software system based on Xilkernel. The check code is received by sender (Alice)s PC by coding the sent data and sent to receiving party (Bob) while received by receiving partys PC through embedded communication network and operate decoding procedure for decoding at the same time to complete data coordination. FPGA plays the role of Web server to be mainly responsible for data communication with two computers. Two PC machines and FPGA development board are connected to internet through concentrator to constitute the required network communication website, which could realize longdistance

dynamic communication.
Fig. 1 MicroBlaze System Structure
Gauss random number IP

interrupt controller

timer MicroBlaze
10/100M Ethernet controller
OPB BUS

Ethernet chip BCM522l

DDR SDRAM controller

RS232
DDR SDRAM

UART controller

As shown in Fig. 1 of the hardware system structure, several major modules are including: MicroBlaze soft core processor, 10/100M Ethernet controller, UART controller, Gauss random number IP, interrupt controller, DDR SDRAM controller, timer and interrupter, etc. OPB bus is the systems communication bus and MicroBlaze soft core processor is control core of the whole network communication system. 10/100M Ethernet controller is an IP core provided by Xilinx. A trail version is offered on Xilinx official website, with which to control Ethernet chip BCM522l on Spartan3s

1500MB board. UART controller is EDK self-taken IP core and is communication interface of RS232 on MicroBlaze and FPGA board. RS232 interface on the board is communicated with that on PC machine as debugging port of system hardware to display debugging information on the super terminal.

MicroBlaze Soft Core Processor

MicroBlaze is 32 bps soft core processor developed by Xilinx company that it uses RISC framework with

independent 32 bps data bus and order bus to be able to execute the procedures stored on ESRAM and external memory at full speed and visit the data. MicroBlaze could flexibly use Spartan or Virtex series FPGA for construction, easy for extension. In MicroBlaze, the order and data are stored separately that the processor firstly reads order content in instruction memory, gets data address after decoding and then reads data in the relevant data storage. Thus, the next order could be read in advance in executing the procedure to improve execution efficiency. In order to increase MicroBlaze processing speed, 8 Kbyte DRAM is designed in this system to be data and order buffer memory.

Gauss Random Number IP Core

EDK users could customize their own IP core that EDK provides IPIF to enable users to ignore system interface logic but concentrate to work out users logic. In order to test data transmission effect, a Gauss random number IP core is designed in ISE to generate the random number fit for Gauss distribution as data for network communication. IP core is hung on MicroBlaze embedded system through OPB bus, which is connected between peripheral and RAM with different bus width and sequence requirement to minimize their influence on PLB performance. In this system, MicroBlaze is not directly connected to OPB bus but bridged upon PLB to OPB Bridgeto visit Gauss random number IP core with OPB bus while Gauss random number IP core is bridged upon OPB to PLB Bridge to visit storage with PLB bus.

Software Design
All software designs are realized on Xilkernel for software

system adopts Xilinxs Xilkernel embedded real-time operation system. All application programs are developed by invoking API function provided by Xilkernel core, which conducts task invoking and management.

A. Xilkernel Operating System

Xilkernel is small and modularized embedded operation system core used in EDK system to support Microblaze soft core and Power PC hard core. Xilkernel is close integration with hardware system formed by EDK with highly customized feature and supporting transplantable operation system interface POSIX open structure. Xilkernel supports POSIX thread operation that it is allowed to build a multiple thread operation network program. LwIP requires more thread operations for running because it lies in internal mailbox function to process buffer data package. In order to realize EDKs reading and writing operation for HTML webpage, HTML webpage is firstly required to transfer into proper EDK operation document. LibXiL MFS

function library is added in Xilkerne1. LibXiL MFS function library is a library function provided by EDK to conduct document operation for documents in storage, mainly targeted for document system on storage media of RAM/ROM/Flash, etc. The order of mfsgen provided by LibXil MFS library is firstly used: mfsgen_cvbfs image mfs 600 index html to change HTML webpage into image.mfs document which is recognized by MFS system; then the order of dow is used to download this image document through JTAG line to DDR DRAM for storage.

B. LwIP and HTTP Protocol

TCP/IP connection is firstly established to realize network communication between PC machine and FPGA board. Here LwIP is chosen to realize this process. LwIP is simplified TCP/IP protocol and reduces RAM occupancy based on maintaining major function of TCP/IP protocol, making it more suitable for embedded system. EDK provides LwIP function library, by invoking the function of which to use BSD SocketAPI to conduct network programming and achieve server function, design embedded SOPC system as server and

PC as client side. After establishing TCP connection between PC machine and FPGA board, IE browser could be used on PC machine to visit FPGA board, which returns to storage webpage after receiving visit order and displays result on IE browser and then PC machine conducts data transmission through webpage operation and FPGA board. Thus, HTTP protocol must be realized in the procedure to achieve smooth communication between IE browser and FPGA board. HTTP protocol is used to send and receive information on the internet. HTTP is a stateless protocol. Stateless means not necessarily establishing lasting connection between Web browser and Web server that the connection is closed when a client side sends request to server, then Web server returns response. The relevant connection information is not kept in server side.

Experiment Step and Result

The quantum cryptography processing software CV QKD is used to allocate PC machine A (Alice side)s IP address to operate CVQKD simulation software Alice side's

program and allocate PC machine B (Bob side)s IP address to operate Bod sides program on it; and then allocate IP address and gateway of FPGA development board to make three at the same segment. Click browser window on the interface of Alice side's program and enter IP address of FPGA development board in address column, the webpage of EDK network transmission system will pop up; then enter 500, the number of random numbers in setcolumn on the webpage and click generate Gauss random number that FPGA begins to generate Gauss random number; which is delivered to PC machine through internet and displayed in the output column. Enter sent data in sent data column and click send, the data is transmitted to DDR SDRAM through Ethernet for storage. Next, enter IP address of FPGA board in IE browser on PC machine of the receiving side, data stored on DDR SDRAM is sent to the receiving party through internet. Data encryption, transmission and decoding process are realized through CVQKD simulation software, demonstrating that this embedded communication network has strong practical utility.

Conclusion
A set of embedded network communication system is constructed according to data processing requirement of quantum cryptography communication to realize continuous data coordination and improve data processing speed. The software and hardware realization principle of this communication system is analyzed in this paper. It is proved by the experiment result that SOPC system using embedded soft core MicroBlaze not only makes FPGA design more flexible but also better plays hardware function. The designed network communication system is able to conduct network data communication on many longdistance PC machines and FPGA board as well as have important utility value in other fields.