62

TRANSA2TIONS IEEE

ON ELECTRON DEVICES,

VOL. ED-31, NO. 1, JANUARY 1984

[ 171 K. Lehovec, C-V analysis of a partially depleted semiconductj.1g

channel, A p p l . Phys. Lett., vol. 26, pp. 82-84, Feb. 1,1975. [ 181 W. Ford and J. Barrera, Limitations of electrical Profiling Techniques in GaAs, in GaAs IC Symp. Tech. Dig., pp. 62-65, N[w. 1982. [19] W. Walukiewicz, L. Lagowski,L.Jastrzebski, M. Lichtensteigx, and H.C. Gatos, Electron mobility and free-carrier absorptim in GaAs: Determinationofthecompensationratio, J. Ap,??. Phys., vol. 50, pp. 899-908, Feb. 1979. [20] G. M. Martin, A. Mitonneau, and A. Mircea, Electron traps in bulk and epitaxial GaAs, Electron. Lett, vol. 13, pp. 191-1!12, Mar. 1977. [21] G. N. Maracas, J. G. Tenedorio,A. 0. Tenedorio,andL. F. Eastman, Investigation of deep levels in GaAs MESFEXS introduced bydeviceprocessing, in Proc. 8thBienn. CornzM Elec. Eng. Con&,pp. 149-158,1981. [22] S. G. Liu, S. Y. Narayan, C. W. Magee, and C. P. Wu, 2Sli implantation into 40Ar implant-pretreated semi-insulating Ga.is substrates-mobility and activation efficiency enhancement $ Appl. Phys. Lett., vol. 41, pp. 12-75, July 1982. [23] A. M. White,Whitherchromium in gallium arsenide?, in Eroceedings of the Conference on Semi-Insulating 111-V Materic!!s, Nottingham, G. J. Rees, Ed. United Kingdom: Shiva PublicatioIIr;, Limited, 1980, pp. 3-12. I241 G. M. Martin, Key electrical parameters insemi-insulating I : ZLterials: the methods to determine them in GaAs, in Proceedirigs of the Conference on Semi-Insulating 111-V Materials, NottipgUnited Kingdon: Shiva Publicatiorla,, ham, G. J. Rees, Ed. Limited, 1980, pp. 13-28. [25] A. Ashby, G. G. Roberts, D. J. Ashen, and J. B. Mullin, Ncnextrinsic conduction in semi-insulating gallium arsenide, SolidState Commun., vol. 20, pp. 61-63, Oct. 1976. [26] G. M. Martin, J. P. Farges, G. Jacob, J. P. Hallais, andG. Poiblau1,

Compensationmechanisms in GaAs, J. A p p l . Phys., vol. 51, pp. 2840-2852, May 1980. [27] J. Lagowski, H. C. Gatos, J. M. Parsey, K. Wada, M. Kaminska, and W. Walukiewicz, Origin of the0.82eV electrontrapin GaAs and its annihilation by shallow donors, Appl. Phys. Lett., vol. 40, pp. 342-344, Feb. 1982. [28] G. P. Li and K. L. Wang, Defect formation chemistry of EL2 centeratEc-0.83 eVinion-implantedgalliumarsenide, J. A p p l , Phys., vol. 53, pp. 8653-8662, Dec. 1982. [29] P. N. Favennec and H. LHaridon, Implantation of shallow impurities in Crdoped semi-insulating GaAs, A p p l . Phys. Lett., VOI. 35, pp. 699-701, NOV. 1979. [30] J. Kasaharaand N. Watanabe, Redistribution of Cr in caplessannealedGaAsunderarsenicpressure, Japan J. Appl. Phys., vol. 19, pp. L151-L154, Mar. 1980. [31] P. K. Vasudev, R.G. Wilson, andC.A. Evans, Jr., Damage getteringofCrduring the annealingof Cr and S implants i n semi-insulating GaAs, A p p l . Phys. Lett., vol. 37, pp. 308-310, Aug. 1980. [ 321 E. J. Johnson, J. A. Kafala, and R. W. Davies, The role of deeplevel centers and compensation in producing semi-insulating GaAs,J. Appl. Phys., vol. 54, pp. 204-207, Jan. 1983. [33] Z. Yuanxi, On the probable nature of certain electron traps in GaAs, Inst. Phys. Con& Ser., vol. 63, pp. 185-190, 1981. [ 341 B. T. Debney and P. R. Jay, The influence of Cr on the mobility of electronsinGaAsFets, Solid-state Electron., vol.23,pp. 773-781, July 1980. [35] J. K. Rhee, P. K. Bhattacharya, and R. Y. Koyama, Deep levels in Si-implanted and thermally annealed semi-insulating GaAs :Cr, J. Appl. Phys., vol. 53, pp. 3311-3313, Apr. 1982. [ 361 D. E. Theodorou and J. J. Queisser, Profiling of deep impurities by persistent photocurrent measurements, Appl. Phys., voL 23, pp. 121-126, Oct. 1980.

A Better Understanding of CMOS Latch-Up

GENDA J.

i[u,MEMBER, IEEE

Abstract-Both lumped-element two-transistor circuit model andtvmdimensional finite-element analyses are used to studythelatch.ap phenomena in CMOS structures. The equivalent circuit model offels a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up. A generalized criterion ?or p-n-p-n latch-up is derived based on theequivalent circuit. 2-D modell ulg confirms the latch-up triggering condition described by the criterion. inclutl.,ng Furthermore, 2-D simulationmodelsthe entire latch-upprocess, the dynamic triggering stage, and determines the intrinsic steady-state I- V characteristics of p-n-p-n devices.

[ 2 ]-[4]. Fig. 1 shows the cross section of a CMOS invertor. Fig. 2 shows its basic equivalent circuit, whereR , and R , represent the well and the substrate parasitic resistances, respectively. Due to the distributed nature and the nonlinear behavior of both transistors andresistors, such a lumped-element model generally does not give accuratepredictions. However, this model does provide a simple picture of the latch-up. Recently, atwo-dimensional finite-elementtransient analysis hasbeen used to simulate the entire latch-up process from a high-impedance off state through a dynamic triggering stage to a lowI. INTRODUCTION impedance onstate [ 5 ] . Thispaper combines the simple direct two-dimensional ARASITIC semiconductor-controlled-rectifier [l] (SC:R) lumped-element representation with the simulation to obtain a better understanding of thelatch-up action, also known as latch-up in CMOS structures is phenomena. traditionally represented using a two-bipolar-transistor mollel For simplicity, all the 2-D simulations performed in this Manuscript received March 28, 1983;revised August 31, 1983. work were carried out without considering carrier recombinaThe author was with the IBM Thomas J. WatsonResearch Cewer, tion. Thissimplificationshould not, in any way, affect the Yorktown Heights, NY 10598. He is nowwith the Xerox Palo Alto essence of this work. Research Center,Palo Alto, CA 94304. 0018-9383/84/010C-0062$01 .OO 0 1984 IEEE

HU: A BETTER UNDERSTANDING O F CMOS LATCH-UP

63

p-SI

-=4s
n

Fig. 1. Crosssection of a CMOS invertor. R , and R , representthe resistance associated with the well and the substrate,respectively.
VDD

Equation (3) is a generalized latch-up criterion fora fourterminal device. It expresses the relationship of as and 8s ina low-impedancesteadystate. 8 represents thecontribution of the resistors R , and R , in preventing thelatch-up. Undernormalconditions, 8 ranges between :I and 0. 8 = 1 means all the emitter current is bypassed through the resistor ( R , or/and R , = 0), and (3) can never be satisfied; thus no latch-up can occur. On the other hand, in the case of a twoterminal p-n-p-n structure (Shockley diode) [:6] , 81 = 8 11 = 0 and (3) reduces to the conventional expression for the latch-up criterion

a1 + a 1 1=1
or
PlPll =

(44

1.

(4b)

It is clear that this well-known criterion is only a special case of (3). Several points may be worth mentioning here. The relation4 ship shown by (3) has been used to define the center junction Fig. 2. Basic equivalent c h i t of a CMOS inverster for latch-up study. of a one-dimensional p-n-p-n structure gaing from reverse bias to forward bias [7] , [8] . It also has been suggested that, based 11. A GENERAL CRITERION FOR LATCH-UP on a power supply constraint, an expression similar to (3) can Before the actual 2-D simulation is performed, theequivalent be used as a necessary conditionforlatch-upto occur [4], circuit is used to derive a generalized latch-up criterion. This [9]. Furthermore, (3) was used to described the latch-up latch-up criterion which is a more general condition than holding current [9]. However, one should understand that (3) al+ all > 1 or Plpil > 1, canbe obtained from Fig. 2 . As- has a much wider application than any of the previous suggessuming that the p-n-p-n structure is in a low-impedance state, tions; (3) is a sufficient condition for a p-n-p-n device being in one finds a steadystate.Although (3) is derived fromthe equivalent circuit shown in Fig. 2, thefinal mathematical expression does not contain either R , or R,; thus the resistance values are of noimportance.Infact, (3) is valid whetherornotother resistancessuch as those associated with the base, collector, or emitter of the parasitic transistors are included. Therefore, the uncertainty of determining the resistance value for a completetwo-transistor equivalentcircuit is eliminated,and where al and all are the common-base dc current gain of the instead a well-defined parameter 8 is used. vertical p-n-p and lateral n-p-n transistors, respectively, and I,, is If carrier generation in the center junction of a p-n-p-ndevice the collector saturation current. By rearranging (l), one has takes place (for instance, by light or radiation), an additional term IGENERATIONIZ~,which is similar to Ic,/It should be added totheleft-hand side of (3). However, under normal FET operatingconditions,themagnitude of the generation current is not significant. Thus this term may also be ignored. where I,, = ICol+ I,, 11. In a low-impedance state, the term Z,,/It is negligible, and 111. DETERMINATION OF THE LATCH-UP THRESHOLD for a nontrivial solution I , # 0, it is found Both as and the 8s are functions of current. Itwill be shown al t all = 1 + elal + ellall (3a) that once as and 0s are determined as functions of current, the or latch-up threshold can be predicted. The structure shownin Fig. 3 will be used for demonstration in this study. It hasbeen PlPII = 1 + elPl(Pll + 1) + e IlPll (PI+ 1) (3b) suggested that the conventional way of measuring a in CMOS structures does not give true values [ 101 . This is because the where base current of the measured transistor is supplied by the external base-emitter bias during the. medsurement, while ina real situation, the base current is supplied bythe complementary transistor. The pattern of the current flow within the structure and is totally different between the two cases. In order to model thecurrent flowina more realistic fashion,twodifferent structure configurations depicted in Figs. 4 and 5 were used

64
VDD

IEEETRANS/.CTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 1 , JANUARY 1984

o+"DD=30"olls

T
I T

O L IpA

-I

IOmA

IOpA

100pA

ImA

22pm

ITOTAL (pm?

Fig. 3. A p-n-p-n structure used for the 2-D simulation of latch-up.

Fig. 6 . Simulated all and 0 11 as functions of the total current obtained using the structure in Fig. 4.

L--

~~

1 -

._~

~~

O L IpAI O O p A

--J

IOpA

ImA

lOmP

ITOTAL (~m-l)

Fig. 4. Part of the structure shown in Fig. 3 used to determine a11;md 0 11. Zcl is a current source replacing the vertical p-n-p transistor.

Fig. 7 . Simulated a1 and 01 as functions of the total current obtained using the structure in Fig. 5.
7 "

01 10pA

LATCH-UP !/THRESHOLD Y lOOpA 1mA

~

lTOTAL

b-')

lOmA

VI
1A

lOOmA

Fig. 5. Part of the structure shown in Fig. 3 used to determine a i nd 01. 1,ll is a current source replacing the lateral n-p-n transistor.
I :

Fig. 8. al+ all - 0101 - e llall plotted as a function of total current. a's and e's are from Figs. 6 and 7. At ITHRESHOLD and1, (3) is satisfied.

- al)at node B in Fig. 2 . These results indicate the base potential of the n-p-n transistor will drop and that of the p-n-p transistor will rise; consequently,thetotalcurrent will decrease. Ontheother hand, inequality (6) represents a self-sustaining increase in the total current. This suggests that latch-up will be triggered once the total current is greater than the threshold current, andIL is thesteady-statecurrentatlatch-up. It is foundthatthe threshold current is afunction of V D ~ Fig. . 9 shows the threshold current calculated from a's and 8's at different V,, . As long as the disturbance in this p-n-p-n structure does not cause thetotalcurrent t o exceedthethresholdcurrent,no a1 t all < I t elaL t ellall 5) latch-up will be initiated. is satisfied for I , <ZTHRESHOLD and Since the threshold current of latch-up is an intrinsic quantity of a p-n-p-n structure, one should not expect this quantity to al t all > 1 t elal t ell all 11 6 ) change with respect to different triggering mechanisms. Howis true for I t >ITHRESHOLD. Since the a's will continue! to ever, it has been known that the measured current (triggering decrease after 0 saturates as current increases, (3) will be current) required to trigger a latch-up does vary depending on satisfied again at a current level , Z (latch current) higher than the measuringscheme. For example CMOS fabricatedwith ZTHRE~HOLD. For current even higher than I,, al t all < 'I t epitaxial layer on a heavily doped substrate is very difficulty 8lal t 0 1 1 a11is always valid. This situation is illustrated.in to latch byinjecting current through the vertical transistor, Fig. 8 where a's and 8's are obtained from Figs. 6 and 7, a Id but easy tolatchby stimilating the lateral transistor. This the latch-up current I, is determined by a separate simulatic'n. puzzle can be comprehended with the knowledge of a and 8 So, (3) is satisfied at two current levels, i.e., at I , = ZTHRESFI- describedby (3). Inexperiment, besides the power supply OLD and[, = Z , . Whereas, inequality ( 5 ) or (6) holds, elsewhae. V,, , an additional externalbias is commonly used t o stimulate It can readily be shown that inequality( 5 ) leads to Zcl<1,: t one of the parasitic bipolar transistors. This additional external
to determine a's and 0's. In Fig. 4, current source Icl is used to replace the vertical transistor so thatnolatch-up can be initiatedandthecurrent flow resembles the real situaticln. Accurate a 1 1 and 8 11 as functions of current can thus be obtained from electron and hole current components computed at ;:he terminals. Similarily, al(I) and O1(Z) are determined from 1:h.e configuration shown in Fig. 5 . The results acquired for VDL = 3 V areshownin Figs. 6 and 7. If one defines the smalloat total current at which (3) is satisfied to be the threshold vurent ITHRESHOLD, then in this case, ZTHKESHOLD = 5 1 yA//.m of width. It is interesting to note that
I[

Z ~ l l ( 1- all) at node A and I,ll < I , t IEl(l

HU: A BETTER UNDERSTANDING OF CMOS LATCH-UP

65

i
loot

STEADY STATE

3 VD0 (volts/

Fig. 9. Predicted latch-up triggering threshold current versus the power supply voltage. This is obtained from the as and the 0s following (3).

Fig. 11. A steady-statepotentialdistributionatthe off state.

high-impedance

AFTER 1.6 ns VDD3V

Fig. 10. Equivalent circuit for latch-up triggering experiment. Besides the power supply VDD,an additional bias VBIAS is applied to stimulate n-p-n transistor.

bias changes the equivalent circuitfrom Fig. 2 to Fig. 10 (assuming current injection through n-p-n). Under this circumstance, the current I , becomes negative and consequently 0 i s negative too. This change in 0 value causes the (3) to be satisfied at a lower current level. Since the intrinsic 0 11 for the CMOS with epitaxial layer approach is much bigger than 01, the value and sign change in 011results in a greater impact on the measurement of latch-up triggering current than does 01; this means lateral triggering is easier than vertical triggering in the experiment. Because the additional external bias (in addition to the biases for the proper CMOS operation) changes the latch-up equivalent circuit, the measured triggering current is not the intrinsic latch-up threshold for the circuit without this additional bias. Therefore, the triggering current measured in this case may be considered as an extrinsic latch-up threshold, and an extrinsic latch-up threshold may vary with different triggering methods.

Fig. 12. An instantaneouspotentialdistribution triggering process.

during thelatch-up

The FIELDAY [l 11 program is used, for this simulation, and the simulated structure is the one shown in Fig. 3. Fig. I 1 shows the initial potential distribution at the highrimpedance offstate, where the well bias V , = Voo. Insuchplots, zero potential corresponds to the Fermi level in intrinsic silicon at zero bias. Thus at zero bias, the potential of n-type silicon is positive and p-type is negative. Notethat well-tosubstrate junction is reversely biased. The latch-up is triggered by forward biasing the p+-well junction. By lowering down IV. DYNAMICTRIGGERING OF LATCH-UP IN 2-D V , to 2.2 V, the p-n-p transistor is turned on hard enough to In a p-n-p-n structure, the switching from a high-impedance initiate apositive feedbackfromthen-p-n transistorwhich off state to a low-impedance on state is a transient phe- causes the total current to increase. Fig. 12 shows the potential nomenon. This fast transition makes the study of this phenom- distributionafter V , = 2.2 V for 1.6 ns. EIoth the p+-well enon extremely difficult. Now with the advancement in junction and the n+-junctionare forward biased. This is due to numerical analysis, transient simulation provides a feasibleway a large number of holes injected from the emitter of the p-n-p to study this dynamic behavior. In the following a demonstra- transistor into the collector (the substrate) which causes the tion of dynamic triggering of a p-n-p-n latch-up is presented. potential of the substrate to rise, in turn forward biasing the

66

IEEE TRANS8P,CTIONSON ELECTRON DEVICES, VOL. ED-31, NO. 1, JANUARY 1984

AFTER 2.6
VDD
h

ns

7 7

3v

Fig. 13. An instantaneouspotentialdistributionduringthe triggering process.

AFTER 1.1 ns

latc11-up
I 2 3 I 4

i 1
I
5 I 6 7 VDD (Volts)

v , = 3v vw = 3 v

Fig. 16. Simulatedlow-impedancesteady-state I-V characteristics for the structure in Fig. 3.

to 3 V. Fig. 13 shows the state after V , is kept at 2.2 V for 2.6 ns. There, the total current has increased to an even higher level. After totalof 3.1 ns at 2.2 V, the bias at thewell terminal is returnedto3 V. Because thetotalcurrentat this stage exceeds ITHRESHOLD, latch-up can be triggered. Fig. 1 4 depicts thepotentialafter V w returns to 3 V for 1.1 ns. Thefinal latch-upcondition is shownin Fig. 15.There,the n-well is indistinguishable, and the entire region is flooded with electrons and holes ~m-~) The . total current is close to 1 A/pm of width.
Fig. 14. An instantaneouspotentialdistribution triggering process. during thelatck-up

V. STEADY -STATE I- V CHARACTERISTICS O F LATCH -UP

Starting from a latch-up state one can determine the steadystate I- V characteristics by either varying the voltage and comSTEADY STATE puting the current or varying the current and computing the VDD = 3 v voltage. With this method, thelow-impedance steady-statel-V / vw 3 v characteristic is obtainedandplottedin Fig. 16.Notethe portion of the curve for I , <IHOLD~NG (holding point is defined by dV/dI= 0) can only be tracedusinga currentsource. This part of the curve matches reasonably well with the curve in Fig. 9, which is the latch-up triggering threshold predicted by as and 6s. The potential of the state at latch-upthreshold for V,, = 3 V is depicted in Fig. 17. Note that in the first steady state, the off state in Fig. 11, both transistors are in thecut-offmode, whereas in thesecond steady state,the latch-up on state in Fig. 15, both transistors are in the saturationmode. Now here, in thethirdsteadystatewiththe same V,o, both transistors are in the active mode. This confirms the previous analysis that this state is not stable; any slight noise causing the current to deviate from ZTHRESHOLD will throw the state off balance. So this part of the curve is generally unstable. However, if the measuring system is Fig. 15. The potential distribution of the latch-up on state. stable,portions of this curve are obtainable. Fig. 18 shows nmbstratejunction. Nevertheless, it is foundthat becaI.s,e a dc measurement obtained on a curve tracer where the part the total current at this stage is still smaller than the threshcid of the curve below the holding point is clearly visible. Also, current, the positive feedback cannot sustain after V , returns one finds that the minimum current required to sustain the
i

HU: A BETTER UNDERSTANDING OF CMOSLATCH-UP

61

STEADY STATE

solution. Above this voltage, therearetwo low-impedanck solutions corresponding to each voltage; the lower-current solution, which has a negative impedance, is the latch-up threshold and the higher-current solution, which hasa positive impedance, is thelatch-uponstate.The as and 0s corresponding to the curve of Fig. 16 are recordedin Fig. 19. As predicted, the entire steady-state I-V curve, both the positive-impedance part as well as the negative-impedance part, satisfy the relationship of (3).

Fig. 17.

VI. SUMMARY The two-transistor equivalent circuit and the direct simulation using finite-element analysis are shown to be useful in understanding the latch-up phenomena. It also has been shown that all the low-impedance steady states of p-n-p-n structure satisfy the relationship state by (3). This latch-up criterion is good 2 for 2-, 3-, and 4-terminal p-n-p-n devices. Even with the fact that the resistances associated with a real CMOS structure are of distributed nature, (3) is always valid because the mathematicalexpressiondoes not contain any resistance value. It The potential distribution at I, = lTHRESHOLD. This steady stateis an is found that besides the high-impedance off state, there are unstable state. two low-impedance steady states corresponding to every voltage greater than the holding voltage. The state ,at lower current level is the latch-up triggering threshold and the one at higher current level is the latch-up on state. The latch-up triggering threshold of a p-n-p-n structurecan be predicted if the 0s and as can be determined as functions of current. Since there is no minimum current associated with the latch-up I-V characteristic, thus physically, the holding voltage is a more meaningful term than the holding current. ACKNOWLEDGMENT The author wouldlike to acknowledge the valuable assistance of M . Pinto, S. Kordic, and S. Laux. The author is also grateful to L. Terman, R. Dennard, and H. Yu for their encouragement during the course of this work.

Fig. 18. Measured low-impedance steady-state Z-V characteristics. This curve is traced from high current to low current. Due to the unstable nature of the lower part of the curve, further trace toward even lower current is not obtained.

REFERENCES
[Ij F. E. Gentry, F. W. Gutzwiller, N. Holonyak, Jr., and E. E. Von
Zastrow, Semiconductor Controlled Rectifies. Englewood Cliffs, NJ: Prentice-Hall, 1964. [2] J. J. Ebers, Four-terminal pnpn transistors, Proc. IRE, vol. 40, p. 1361, 1952. [3] E. L. Gregory and E. D. Shafer, Latch-up in CMOS integrated circuits, ZEEE Trans. Nucl. Sci., vol. NS-20, p. 293, Dec. 1973. [ 4 ] D. E. Estreich, The physics and modeling of latch-up and CMOS integrated circuits, Dep. of Electrical Engineering, Stanford Univ., Tech. Rep. G-201-9, Nov. 1980. [5] G. J. Hu, M. R. Pinto, and S. Kordic, Two-dimensional simulation of latch-up in CMOS structures, presentedat the 40th Device Research Conf. (Fort Collins, CO), paper VA-5, June 1982. [6] Sze, Physics of semiconductor Devices. New York: Wiley-Interscience, 1969. [7] J. F.Gibbons, A critiqueofthetheory ofp-n-p-n devices, ZEEE Trans. Electron Devices, vol. ED-11, p. 406, 1964. [8] W. D. Raburn, A model for the parasitic SCR in bulk CMOS, inZEDM Tech. Dig., p. 252, Dec. 1980. [9] A . Ochoa, W. Dawes, and D. Esteich, Latch,.up control in integratedcircuits, ZEEE Trans. Nucl. Sci., vol.NS-26,p.5065, 1979. [ l o ] A. Ochoa and P. V. Dressendorfer, A discussion of the role of distributed effects in latch-up, ZEEE Trans, Nucl. Sci., vol. NS28, p. 4292, 1981. [ 111 E. M. Butula, P. E. Cottrell, E. E. Grossman, and K. A. Salsburg, ZBMJ. Res. Develop., vol. 25, p. 218, 1981.

lorn

IOopA

ImA
IT~TAL (

IOmA

IOOmA

~m-)

Fig. 19. Simulated as and 0s which are determined at different current levels corresponding to the curve shown in Fig. 16. Atall current levels, (3) is satisfied.

low-impedance state does not correspond to the holding current. Actually, at least in principle, the minimum low-impedance currentwhichcorrespondstolatch-upthreshold will continue to decrease as voltage increases until junction breaks down. Thus there is no well-defined minimum current. On the other hand, there is a local minimum in voltage, namely the holding voltage. Below this voltage, there is no low-impedance