B.E/B.TECH.

Degree EXAMINATION, MAY/JUNE 2012 Sixth Semester Electronics and Communication Engineering 080290038- VLSI DESIGN (Regulation 2008) Answer ALL Questions PART A (10*2=20 marks) 1. What is latch up? How it is prevented? 2. What are the four types of design rules? 3. Define body effect. 4. Draw the stick diagram of a CMOS Inverter. 5. Design a 2:1 Mux using transmission gates. 6. Define Logical effort. 7. What is charge leakage? 8. Define retention time. 9. Name the primary design units in VHDL. 10. State the difference between <= and => operators in VHDL. PART B-(5*16=80 marks) 11. (a) (i) List the sequence of steps to create the pattern.(6) (ii) Explain the electrical characteristics that will affect the design of an integrated circuit. (10) (Or) (b) Discuss in detail about the SCMOS design rule set. (16) 12. (a) (i) How the n FET channel is created? Explain(6) (ii) Derive the square law model of a MOSFET.(10) (Or) (b) Discuss in detail about the parasitic resistance and capacitance that affects the MOSFET circuit operation. (16) 13. (a) (i) Explain the operation of a series connected and parallel-connected FETs. (6) (ii)With neat schematic explain the operation of a NOR2 logic circuit. (10) (Or) (b) (i) With neat schematic explain the operation of a NAND2 logic circuit. (10) (ii) Briefly explain Wienberger Array. (6) 14. (a) (i) With circuit schematic, explain the operation of a Dynamic D Flip Flop. (8) (ii) With neat sketch explain the layout of a SR Latch using NOR2 primitives. (8) (Or) (b) (i)With circuit diagram and layout, explain the domino AND2 gate. (10) (ii) With circuit schematic, explain the DRAM array. (6) 15. (a) Write the VHDL code to realize a full adder using (i) Data flow modeling (4) (ii) Behavioral modeling (6) (iii) Structural modeling (6) (b) Design a serial adder (sequential) using Moore model and mealy model. Write the VHDL code to realize them using structural modeling. (16)