- Thit k 1 h thng nh s 1 gm cc khi nh sau: khi thanh ghi 16b, khi multiplexer, 1 khi add/sub unit, khi control

l unit. D liu u vo h thng s thng qua Port DIN 16bit, d liu s c load bi Mux 16 bit vo trong cc thanh ghi khc nhau t r0->r7,v b Mux s cho php d lu c lun chuyn t thanh ghi i cc khi khc( ni khc). ng ra ca MUX c ni vi cc bus nh trong hnh bi n thng xuyn c s dng ghi da liu hay gi da liu t 1 kt ni trong h thng n cc khi khc . - Cc php Cng tr c hin thc bi MUX khi s dng ng a ch u tin ca bus v load s 16 bit vo thanh ghi A.Nu thnh cng, s th 2 s c a tip vo bus. khi Cng tr lc ny s thc hin php ton,v tr v kt qu c a vo thanh ghi G.D liu trong thanh ghi G s c y sang 1 trong cc thanh ghi yu cu

-H thng s hin thc tng php ton da vo chu k xung, v n c iu phi bi khi control Unit.Ci Khi ny s nh r khi no tng phn d liu s c a vo v tr no trn bus v n c iu khin bi thanh ghi no trong qu trnh

load.1 vd nh sau, Nu khi control yu cu 1 tn hiu t ng ra R0out vo Ain , Khi MUx s a ni dng ca thanh ghi R0 vo trong bus v d liu s c load ti chu k xung tip theo v vo thanh ghi A. -Mt h thng tt s thng xuyn gi 1 processor. nu n thc hin tt cc php tnh c xc lp trong kin trc tp lnh. 1 ci danh sch tp lnh ca processor s h tr tt cho vic thc thi lnh. Ct bn tri s cho chng ta thy tn ca cc lnh v cc cc ton t.Nn nh rng c php RX<-[Ry] l ni dung ca thanh ghi RY c a vo thanh ghi RX. ln mv s cho php data s c coppy t 1 thanh ghi ny sang 1 thanh ghi khc.i vi lnh mvi th mt ci hng s D s c y vo trong Rx.

V 1 s lnh khc s c m ha v ly ra t thanh ghi IR s dng dng 9 bit IIIXXXXYYY, III s biu din lnh, XXX gn bi thanh ghi Rx, v YYY gn bi thanh ghi Ry. ngoi ra cn c 2 bit n u bn mun m ha cho 4 tp lnh, chng ta s dng 3 bit bi v 1 s lnh cn li c th chng s c thm vo con processor trong nhng phn cui cng ca bi tp,Do thang ghi IR s kt ni ti 9 bit t 16 bit u vo Din,Nh trong s 1 .Trong lnh mvi 1 word s c ly t thanh ghi IR. - mt s cu lnh, ta c th thm hoc bt , v lm nhiu hn th trong 1 chu k clock , bi v c nhiu lung c thc hin ngang qua bus.Control Unit chuyn sang trng thi ng khi 1 cu lnh hon thnh, v 1 ci tn hiu iu khin cn hon tt trong chu k lnh sau khi lnh hon thnh. con processor bt u thc hin cc lnh trong DIn khi tn hiu Run c xc nhn v processor xc nhn l hon thnh (Done) u ra khi 1 cu lnh kt thc. Ci bng 2 di y cho ta bit tn hiu iu khin u vo c xc nhn trong tng khong thi gian khi n c ci t cc lnh bng 1. cn ghi nh l c 1 s tn hiu c xc nhn thi im 0 trong IRin , khi thi gian tng bc s khng show ra trong tabe.,

Part I Thit k v hin thc Mt processor trong hnh 1 s dng Verilog nh sau: 1. To mt Quartus II project mi cho bi tp ny. 2. To ra Verilog file nh yu cu nh km trong project, v bin dch mch. Mt yu cu ct li ca Verilog code c a ra trong phn a v b ca Hnh 2, v mt vi subcircuit modules trong Hnh 2c c th c s dng trong phn ny. 3. S dng m phng chc nng kim tra code c ng khng. Mt v d ca output cung cp bi mt m phng chc nng cho mt mch c thit k ng c cho trong hnh 3. N cho thy gi tr (2000)16 dc load ln IR t DIN ti thi im 30ns. Trong s ny ( cc bit bn tri nht ca DIN ni n IR) trnh by lnh mvi R0,#D, gi tr D = 5 c a n R0 trn cnh xung clock ti thi im 50ns. Vic m phng sau th hin lnh mv R1, R0 ti thi im 90ns, add R0, R1 ti 110ns, v sub R0, R0 ti 190ns. Lu vic m phng ng ra biu din DIN nh l mt s hexa 4 ch s, v n th hin d liu trong IR nh l mt s bt phn 3 ch s.

moduleproc (DIN, Resetn, Clock, Run, Done, BusWires); input [15:0] DIN; input Resetn, Clock, Run; outputDone;

output[15:0] BusWires; parameter T0 = 2b00, T1 = 2b01, T2 = 2b10, T3 = 2b11; : :: declare variables assignI = IR[1:3]; dec3to8 decX (IR[4:6], 1b1, Xreg); dec3to8 decY (IR[7:9], 1b1, Yreg); // Control FSM state table always@(Tstep_Q, Run, Done) begin case(Tstep_Q) T0: // data is loaded into IR in this time step if(!Run) Tstep_D = T0; elseTstep_D = T1; T1:: :: endcase end // Control FSM outputs always@(Tstep_Q or I or Xreg or Yreg) begin : :: specify initial values case(Tstep_Q) T0: // store DIN in IR in time step 0 begin IRin = 1b1; end T1: //define signals in time step 1 case(I) : :: endcase T2: //define signals in time step 2 case(I) : :: endcase T3: //define signals in time step 3 case(I) : :: endcase endcase end // Control FSM flip-flops always@(posedgeClock,negedgeResetn)

if(!Resetn) : :: regn reg_0 (BusWires, Rin[0], Clock, R0); : :: instantiate other registers and the adder/subtracter unit : :: define the bus Endmodule moduledec3to8(W, En, Y); input [2:0] W; input En; output[0:7] Y; reg[0:7] Y; always@(WorEn) begin if(En == 1) case(W) 3b000: Y = 8b10000000; 3b001: Y = 8b01000000; 3b010: Y = 8b00100000; 3b011: Y = 8b00010000; 3b100: Y = 8b00001000; 3b101: Y = 8b00000100; 3b110: Y = 8b00000010; 3b111: Y = 8b00000001; endcase else Y = 8b00000000; end endmodule moduleregn(R, Rin, Clock, Q); parametern = 16; input [n-1:0] R; input Rin, Clock; output[n-1:0] Q; reg[n-1:0] Q; always@(posedgeClock) if(Rin) Q<= R; endmodule

4. To mt Quartus II project s dng cho vic hin thc mch thit k ln trn DE2-serial board. Project nn bao gm mt top-level module c cc cng input output tng ng trn Altera board. Khai bo mt thc th l mt module processor trong module ny. S dng cc switches SW[15:0] gn n ng vo DIN ca processor v dng SW[17] gn cho Run input. ng thi dng KEY[0] cho v KEY[1] cho Clock ni ng data-bus n cc LEDR[15:0] v kt ni tn hiu Done n LEDR[17]. 5. Thm vo project cc pin assignment cn thit cho board DE2-series. Bin dch mch ln chip FPGA. 6. Kim tra chc nng ca thit k bt cc switches v quan satscacs LEDs. V clock input ca processor c iu khin bi mt nt nhn, n d dng thc hin qua cc bc x l lnh v quan st hnh vi ca mch. Part II : Trong phn ny s hng dn bn thit k mch c m t trong Hnh 4, , memory v counter module s c kt ni n processor thit k trong part I. B m (counter) c dng c d liu trong memory cc t nh c cc a ch lin tip nhau a vo processor (as a stream of instructions). n gin ha thit k v kim tra mch, ta s dng cc tn hiu clock ring bit, PClock cho procesor v MClock cho memory.

1. To mt project mi, dng test mch. 2. To mt file top-level veilog, khi to cc module processor, memory v counter. S dng cng c the Quartus II MegaWizard Plus_In Manager to module memory trong th vin Altera library of parameterized modules (LPMs). Tm n mc ROM:1-PORT trong danh mc Memory Complier ca LPMs, lm theo hng dn to mt b nh c mt data port 16 bits v c 32 words (ROM 32*16) . Trong Hnh 5, V memory ch c mt read port khng c write port nn n cn c gi l synchronous read-only memory (synchronous ROM). Lu memorry cn c mt thanh ghi load a ch mt cch ng b. Vic phi dng thanh ghi ny l do thit k ca cc khi nh trong chip Cyclone FPGA; Trong bn thit k bn phi tnh ton cho clock ca thanh ghi a ch (address register) .

 a lnh vo trong b nh, bn cn ghi r cc gi tr ban u cn a vo trong b nh, v s a vo mt ln khi mch ca bn c lp trnh trn chip FPGA. iu ny c th c thc hin bi trnh vit vo b nh (wizzard) dng file memorry initialization file (mif). Vic ny c minh ha c th trong Hnh 6. Ta t tn file inst_mem.mif, sau file ny s c to ra trong th mc cha project. Vo Quartus II on-line Help bit thm v nh dng mif file v to mt file m c cc lnh ca processor kim tra mch ca bn.

3. Dng m phng chc nng (functional simulation) kim tra mch. Chc chn rng d liu phi c c ra mt cch chnh xc t ROM v dc x l bi processor. Project phi c cc tn port cn thit v gn pin cho n hin thc mch ln DE2series board. Dng SW17 lm Run input ca processor. KEY0 lm Resetn, KEY1 cho Mcock v dng KEY2 cho Pclock. Kt ni processor bus n LEDR[15:0] v kt ni tn hiu Done n LEDR17. Ci tin processor: C th ci thin hiu sut cho processor cho counter (Hnh 4) khng ln hn mc cn thit, v cho processor c kh nng thc thi cc lnh read v write ln b nh hay cc thit b khc. Vic ci tin ny bo gm c vic thm lnh mi vo

processor v chng trnh c processsor x l v vy m cng phc tp hn; vic ny s c m t chi tit hn trong bi lab sp ti ca Altera.