N CU TRC MY TNH LAB 4

N CU TRC MY TNH
LAB4:

Design a MIPS Pipelined

CPU
I.
STT

NHM 37

BNG PHN CNG CNG VIC:

TN THNH VIN

NHIM V

+ Tm hiu li LAB 1: Thit

k RegisterFile 32 by 32
+ Tm hiu Structural
Hazards v cch khc
NGUYN THNH I phc.
+ Data Hazards:
Forwarding and stalling.
+ Bo co
+ Slide: phn I.
+ Tm hiu li LAB2: Thit
k
b tnh ton ALU.
+ Control Hazards v cch
khc phc.
NGUYN CNG LINH
+ Vit on code ASM
v chuyn sang m
my kim tra CPU
+ Slide: phn II
+ Tm hiu li LAB 3: MIPS
32 bit SINGLE-CYCLE CPU
v
so snh vi PIPELINE-CPU
L HU V
+ Datapath PIPELINE-CPU
+ M phng lnh trn
Quartus
+ Slide: phn III.

NG GP

33%

33%

33%

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 N CU TRC MY TNH LAB 4

I.

YU CU THIT K:

1.

Yu cu chung:

Thit k b x l trung tm MIPS PIPELINED thc hin cc lnh:

ADD, SUB, SLT, JR, LW, SW, BNE, XORI, J

Cc cng logic khng c qu 4 ng vo, vi delay 50ps.

Cc khi iu khin logic c th dng cu trc lnh behavioral.

2.

Tp lnh:

ADD rd, rs, rt: Reg[rd] = Reg[rs] + Reg[rt].

BNE rs, rt, imm16:

if (Reg[rs] != Reg[rt]) PC = PC + 4 + Sign_ext(Imm16)<<2 else PC = PC +
4.

J target: PC = { PC[31:28], target, 00 }.

JR rs:

PC = Reg[rs].

LW rt, imm16(rs): Reg[rt] = Mem[Reg[rs] + Sign_ext(Imm16)].

SLT rd, rs, rt:

If (Reg[rs] < Reg[rt]) Reg[rd] = 00000001 else Reg[rd] = 00000000

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SUB rd, rs, rt:

Reg[rd] = Reg[rs] Reg[rt].

SW rt, imm16(rs):

Mem[Reg[rs] + Sign_ext(Imm16)] = Reg[rt].

XORI rt, rs, imm16:

Reg[rt] = Reg[rs] XOR Zero_ext(Imm16).

II.

THIT K :

1. Gii thiu v mips-pipelined-cpu:

Gm c 5 tng:
IF:
Instruction Fetch
ID:

Register Decode/ Register file

read EX:

ALU Execute/ Address

caculation MEM: Memory access

WB:

Write Back

2. Datapath ca mt MIPS-PIPELINED-CPU 32bit bao gm :

Khi PC 32-bit
B nh lnh 32 bit
B thanh ghi MIPS Register 32 bit
B tnh ton ALU
B nh d liu 32 bit
B iu khin trung tm
B iu khin ALU
B cng
B dch tri
B m rng du
Mt s MUX 5 bit v 32 bit.
Khi Hazards Detection.
Khi Forwarding.
Khi Discard Instruction.
Cc thanh ghi pipelined gm IF/ID, ID/EX, EX/MEM,
MEM/WB.
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 N CU TRC MY TNH LAB 4

3. Cc thay i so vi single-cycle-cpu:
Cc tn hiu iu khin c chia thnh cc nhm:
Nhm EX: Jump, AluOp[1:0], AluSrc,
RegDst. Nhm M: Branch, Memread,
MemWrite.
Nhm WB: MemtoReg v RegWrite.
V Signzero dng m rng zero i vi lnh XORI.
cc lnh thc hin ng chu k lnh th cc tnh hiu iu khin
trn phi c lu vo cc thanh ghi pipeline. Sau mi chu k cc tn hiu
n vi tng khi v iu khin cc khi hot ng ng.
Bng tr v cc tnh hiu iu khin:

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 N CU TRC MY TNH LAB 4

Gii quyt lnh BNE
Khi c lnh BNE th s xy ra mt trong hai trng hp l: Nu
khng tha mn iu kin th cu lnh k tip thc hin bnh thng. Nu
iu kin tha mn lnh s nhy ti mt nhn mi ty thuc vo gi tr
trong trng Immed. Nhn nhy ti c tnh ton bng cch ly gi tr
thanh ghi hin ti cng vi 4 cng tip vi gi tr trong trng Immed sau
khi c m rng du v shiftleft2. Khi taken xy ra th cc cu lnh ID,
EX cn phi xa i (ghi 0 vo thanh ghi IF/ID v ID/EX) v thc hin 2
lnh NOP vo khi lnh iu khin (STALL_BNE_ID_EX)
Gii quyt lnh Jump
Khi c lnh Jump th sau mt chu k s nhy ti cu lnh cha
trong trng Immed. V ch sau 1 chu k lnh mi thc hin lnh nn khi
cu lnh ang giai on ID th phi pht hin c lnh Jump ri. Do
tn hiu iu khin cn phi xut hin thm tng ID pht hin
lnh Jump. Khi thc hin lnh Jump, tn hiu iu khin iu khin khng
cho php ghi vo thanh ghi ID_EX. Khng bubble v cc lnh thc hin trn
thanh ghi $0 nn khng nh hng chi c.

Lnh JR
Lnh JR s c thc hin sau 2 chu k lnh. Tng t, khi c lnh
JR th 2 cu lnh sau lnh JR s b xa, v tn hiu iu khin s khng
cn to ra lnh NOP v cu lnh b xa.

Lnh load
Lnh load c Stall lm cho khng ghi d liu vo PC, IF_ID v cc
lnh iu khin b xa. Vi cch lm trn th cu lnh k tip sau lnh
load s xut hin 2 chu k tng EX nn xut hin ForwardB, nhng iu
ny khng nh hng ti kt qu cc thanh ghi v cc lnh iu khin
b xa.

Lnh Sw
i vi lnh storewords: CPU hot ng bnh thng. Khi lnh sw
n tng
MEM th phi mt chu k d liu mi c ghi.(ch l ghi d liu ch
xy ra ti
chu k cui).
Cc lnh R
Lnh R thc hin nh lab3, khi cu lnh qua tng EX th CPU thc
hin lnh
v ch n 2 chu k sau khi qua tng MEM, WB th d liu ghi vo thanh ghi
ch.

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 N CU TRC MY TNH LAB 4

4. DATAPATH:

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 N CU TRC MY TNH LAB 4

5. CC KHI THAY I SO VI SINGLE CYCLE CPU
Khi Forwarding unit :
i vi CPU Pipeline, khi thanh ghi ngun(Rs or Rt) ca cu lnh
k tip l thanh ghi ch Rd ca cu lnh ang thc hin th d liu
s khng c sn v cha kp ghi vo cc thanh ghi. Do d cn c
khi Forwarding chuyn d liu t tng MEM hoc WB v li ng vo
ALU tng EX.
Gii quyt

vn

Forward:

iu kin: Thanh ghi ch khng c l thanh ghi $0.

Bit cho php ghi RegWrite=1
Forward s xy ra khi a ch thanh ghi EX/MEM Register Rd trng
vi a ch
thanh ghi ID/EX Rs(forwardA), hoc a ch thanh ghi ID/EX Rt(forwardB).
Forward s xy ra khi a ch thanh ghi MEM/WB Register Rd trng vi
a ch thanh ghi ID/EX Rs(forwardA), hoc a ch thanh ghi ID/EX
Rt(forwardB).
thc hin Forward th ta thm mch chn 3 knh thnh 1 knh
(mux 3 to
1) 32 bit trc ng vo Bus_A v Bus_B.
Bng forward
ForwardA=0
0
ForwardA=0
1

ID/EX
EX/MEM

ForwardA=1
0

MEM/WB

ForwardB=0
0
ForwardB=0
1

ID/EX

ForwardB=1
0

EX/MEM
MEM/WB

BusA ca ALU ly gi tr t Register File

BusA ca ALU ly gi tr t kt qu ca chu k
trc
BusA ca ALU ly gi tr t kt qu ca t
DataMem
hoc gi tr c tnh ton ca 2 chu k trc
BusB ca ALU ly gi tr t Register File
BusB ca ALU ly gi tr t kt qu ca chu k
trc
BusB ca ALU ly gi tr t kt qu ca t
DataMem
hoc gi tr c tnh ton ca 2 chu k trc

CODE KHOI FORWARDING:

`timescale 1 ps / 100 fs module

ForwardingUnit(ForwardA,ForwardB,MEM_RegWrite,WB_RegWrite,MEM_WriteRe
gister,WB_WriteRegister,EX_rs,EX_rt);
output [1:0] ForwardA,ForwardB;
wire [1:0] ForwardA,ForwardB;
input MEM_RegWrite,WB_RegWrite;

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input [4:0] MEM_WriteRegister,WB_WriteRegister,EX_rs,EX_rt;
always @(MEM_RegWrite or WB_RegWrite or MEM_WriteRegister or
WB_WriteRegister or EX_rs or EX_rt)
Begin
if ((MEM_RegWrite==1)&&(MEM_WriteRegister !=
0)&&(MEM_WriteRegister==EX_rs))
ForwardA = 2'b10;
else if ((WB_RegWrite==1)&&(WB_WriteRegister !=
0)&&(WB_WriteRegister==EX_rs))
ForwardA = 2'b01;
else
ForwardA = 2'b00;
if ((MEM_RegWrite==1)&&(MEM_WriteRegister !=
0)&&(MEM_WriteRegister==EX_rt))
ForwardB = 2'b10;
else if ((WB_RegWrite==1)&&(WB_WriteRegister !=
0)&&(WB_WriteRegister==EX_rt))
ForwardB = 2'b01;
else
ForwardB = 2'b00;
end
endmodule

Khi Hazard detection unit:

i vi lnh load: d liu s c ly ra giai on MEM nn vic
bit iu
khin c ni dung t b nh d liu MemRead=1. Data Hazard xy ra khi
thanh ghi ngun (Rs or Rt) ca cu lnh lin sau trng vi thanh ghi ch
(Rt) ca cu lnh Lw hin ti. Do cn c khi Hazard detection unit
giai on ID pht hin Hazard. Khi pht hin c Hazard s to tr
(STALL) 1 chu k ng thi khng cho php ghi vo cc thanh ghi PC v IF.
CODE KHOI HAZARD DETECTION:
`timescale 1 ps / 100 fs
module
StallControl(PC_WriteEn,IFID_WriteEn,Stall_flush,EX_MemRead,EX_rt,ID_rs,ID_rt);
output PC_WriteEn,IFID_WriteEn,Stall_flush;
wire PC_WriteEn,IFID_WriteEn,Stall_flush;
input EX_MemRead,EX_rt,ID_rs,ID_rt;
wire [4:0] EX_rt,ID_rs,ID_rt,xorRsRt,xorRtRt;
wire EX_MemRead;

always @(EX_MemRead or EX_rt or ID_rs or ID_rt)

begin
if ((EX_MemRead==1)&&((EX_rt==ID_rs)||(EX_rt==ID_rt)))
begin
PC_WriteEn=1'b0;

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IFID_WriteEn=1'b0;
else
begin
PC_WriteEn=1'b1;
IFID_WriteEn=1'b1;
Stall_flush =1'b0;
end
end
endmodule

KHI WRITE-BACK:
Khi ny nhm mc nh c ngay d liu ang c ghi ng thi
khc phc khng cho xy ra Hazard tng Writeback.
CODE KHOI WRITEBACK:
`timescale 1 ps / 100 fs
module
WB_forward(ReadData1Out,ReadData2Out,ReadData1,ReadData2,rs,rt,WriteRe
gister,WriteData,RegWrite);
//module nay nham muc dich co the doc ngay du lieu dang duoc ghi dong thoi
// khac phuc khong cho Hazard xay ra o WriteBack Stage
output [31:0] ReadData1Out,ReadData2Out;
input [31:0] ReadData1,ReadData2,WriteData;
input [4:0] rs,rt,WriteRegister;
input RegWrite;
wire ReadSourceRs,ReadSourceRt;
// neu viet theo behavior thi phai khai bao reg thay vi wire
wire compOut1,compOut2;
always @(rs or rt or WriteRegister or WriteData or RegWrite)
begin
if ((RegWrite==1)&&(WriteRegister != 0)&&(WriteRegister==rs))
ReadSourceRs = 1'b1; //Forwarding WriteData to ReadData1
else
ReadSourceRs = 1'b0;
if ((RegWrite==1)&&(WriteRegister != 0)&&(WriteRegister==rt))
ReadSourceRt = 1'b1; //Forwarding WriteData to ReadData2

else
ReadSourceRt = 1'b0;
end
endmodule

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KHI DISCARD INSTRUCTION:
Khi ny x l Control Hazard, pht hin cc lnh nhy v hy cc
lnh ngay sau lnh nhy . Nu lnh nhy l J th xa thanh ghi IF/ID.
Nu lnh nhy l Jr hoc lnh r nhnh Brand th xa thanh ghi IF/ID v
ID/EX
CODE KHOI DISCARD INSTRUCTION:
`timescale 1 ps / 100 fs
module Discard_Instr(ID_flush,IF_flush,jump,bne,jr);
output ID_flush,IF_flush;
input jump,bne,jr;
or #50 OR1(IF_flush,jump,bne,jr);
or #50 OR2(ID_flush,bne,jr);
endmodule

6. CODE VERYLOG CHO MIPS-PIPELINED-CPU:

`timescale 1 ps / 100 fs
`include "regfile.v"
module
MIPSpipeline(clk, reset);
inputclk, reset;
wire [31:0] PC, PCin;
wire [31:0] PC4,ID_PC4,EX_PC4;
wire [31:0] PCbne,PC4bne,PCj,PC4bnej,PCjr; // cac tin hieu PC o cac bo MUX
wire [31:0] Instruction,ID_Instruction,EX_Instruction; // dau ra bo nho lenh
wire [5:0] Opcode,Function; // truong Opcode, Function
// Extend
wire [15:0] imm16; // gia tri immediate trong cau lenh loai I
wire [31:0] Im16_Ext,EX_Im16_Ext;
wire [31:0] sign_ext_out,zero_ext_out;
// regfile
wire [4:0]
rs,rt,rd,EX_rs,EX_rt,EX_rd,EX_WriteRegister,MEM_WriteRegister,WB_WriteRegister;
wire [31:0] WB_WriteData, ReadData1, ReadData2,ReadData1Out,ReadData2Out,
EX_ReadData1, EX_ReadData2;
// ALU
wire [31:0] Bus_A_ALU,Bus_B_ALU,Bus_B_forwarded;
wire [31:0] EX_ALUResult,MEM_ALUResult,WB_ALUResult;
wire ZeroFlag, OverflowFlag, CarryFlag, NegativeFlag,notZeroFlag;
wire [31:0] WriteDataOfMem,MEM_ReadDataOfMem,WB_ReadDataOfMem;
//Cac tin hieu Control
wire
RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Jump,SignZero,J
RControl;
wire
ID_RegDst,ID_ALUSrc,ID_MemtoReg,ID_RegWrite,ID_MemRead,ID_MemWrite,ID_Br
anch,ID_JRControl;
wire
EX_RegDst,EX_ALUSrc,EX_MemtoReg,EX_RegWrite,EX_MemRead,EX_MemWrite,E
X_Branch,EX_JRControl;
wire MEM_MemtoReg,MEM_RegWrite,MEM_MemRead,MEM_MemWrite;
wire WB_MemtoReg,WB_RegWrite;

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wire [1:0] ALUOp,ID_ALUOp,EX_ALUOp;
wire [1:0] ALUControl;
wire bneControl,notbneControl;
wire JumpControl,JumpFlush;
wire [1:0] ForwardA,ForwardB;
//flush
wire IF_flush,IFID_flush,notIFID_flush,Stall_flush,flush;
//shift left
wire [31:0] shiftleft2_bne_out,shiftleft2_jump_out; // dau ra 2 bo shift left
// PC Write Enable, IF/ID Write Enable
wire PC_WriteEn,IFID_WriteEn;
//======Tao thanh ghi PC======
register PC_Reg(PC,PCin,PC_WriteEn,reset,clk);
Add Add1(PC4,PC,{29'b0,3'b100}); // PC4 = PC + 4
InstructionMem InstructionMem1(Instruction, PC);
// thanh ghi IF/ID
register IFID_PC4(ID_PC4,PC4,IFID_WriteEn,reset,clk);
register IFID_Instruction(ID_Instruction,Instruction,IFID_WriteEn,reset,clk);
RegBit IF_flush_bit(IFID_flush,IF_flush, IFID_WriteEn,reset, clk);
//========= ID STAGE===========
assign Opcode = ID_Instruction[31:26];
assign Function = ID_Instruction[5:0];
assign rs = ID_Instruction[25:21];
assign rt = ID_Instruction[20:16];
assign rd = ID_Instruction[15:11];
assign imm16= ID_Instruction[15:0];
// Main Control
Control MainControl(
RegDst,
ALUSrc,
MemtoReg,
RegWrite,
MemRead,
MemWrite,
Branch,
ALUOp,
Jump,
SignZero,
Opcode
);
// Regfile
regfile Register_File(
ReadData1,
ReadData2,
WB_WriteData,
rs,
rt,

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WB_WriteRegister,
WB_RegWrite,
reset,
clk);
// forward Read Data if Write and Read at the same time
WB_forward
WB_forward_block(ReadData1Out,ReadData2Out,ReadData1,ReadData2,rs,rt,WB_
WriteRegister,WB_WriteData,WB_RegWrite);
// Sign-extend
sign_extend sign_extend1(sign_ext_out,imm16);
// Zero-extend
zero_extend zero_extend1(zero_ext_out,imm16);
// immediate extend: sign or zero
mux2x32to32 muxSignZero( Im16_Ext,sign_ext_out,zero_ext_out, SignZero);
JRControl_Block JRControl_Block1( JRControl, ALUOp, Function);
Discard_Instr
Discard_Instr_Block(ID_flush,IF_flush,JumpControl,bneControl,EX_JRControl);
or #(50) OR_flush(flush,ID_flush,IFID_flush,Stall_flush);
flush_block flush_block1(
ID_RegDst,
ID_ALUSrc,
ID_MemtoReg,
ID_RegWrite,
ID_MemRead,
ID_MemWrite,
ID_Branch,
ID_ALUOp,
ID_JRControl,
flush,
RegDst,
ALUSrc,
MemtoReg,
RegWrite,
MemRead,
MemWrite,
Branch,
ALUOp,
JRControl);
//==========EX STAGE=========================
// thanh ghi ID/EX
register IDEX_PC4(EX_PC4,ID_PC4,1'b1,reset,clk);
register IDEX_ReadData1(EX_ReadData1,ReadData1Out,1'b1,reset,clk);
register IDEX_ReadData2(EX_ReadData2,ReadData2Out,1'b1,reset,clk);
register IDEX_Im16_Ext(EX_Im16_Ext,Im16_Ext,1'b1,reset,clk);
register IDEX_rs_rt_rd(EX_Instruction[31:0],ID_Instruction,1'b1,reset,clk);
assign EX_rs = EX_Instruction[25:21];
assign EX_rt = EX_Instruction[20:16];
assign EX_rd = EX_Instruction[15:11];

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// 9 tin hieu control qua ID/EX
RegBit IDEX_RegDst(EX_RegDst, ID_RegDst, 1'b1,reset, clk);
RegBit IDEX_ALUSrc(EX_ALUSrc, ID_ALUSrc, 1'b1,reset, clk);
RegBit IDEX_MemtoReg(EX_MemtoReg, ID_MemtoReg, 1'b1,reset, clk);
RegBit IDEX_RegWrite(EX_RegWrite, ID_RegWrite, 1'b1,reset, clk);
RegBit IDEX_MemRead(EX_MemRead, ID_MemRead, 1'b1,reset, clk);
RegBit IDEX_MemWrite(EX_MemWrite, ID_MemWrite, 1'b1,reset, clk);
RegBit IDEX_Branch(EX_Branch, ID_Branch, 1'b1,reset, clk);
RegBit IDEX_JRControl(EX_JRControl, ID_JRControl, 1'b1,reset, clk);
RegBit IDEX_ALUOp1(EX_ALUOp[1], ID_ALUOp[1], 1'b1,reset, clk);
RegBit IDEX_ALUOp0(EX_ALUOp[0], ID_ALUOp[0], 1'b1,reset, clk);
// khoi Forwarding
ForwardingUnit
Forwarding_Block(ForwardA,ForwardB,MEM_RegWrite,WB_RegWrite,MEM_WriteRe
gister,WB_WriteRegister,EX_rs,EX_rt);
// mux 3 x32 to 32 chon nguon cho ALU (forwarding)
mux3x32to32
mux3A(Bus_A_ALU,EX_ReadData1,MEM_ALUResult,WB_WriteData,ForwardA);
mux3x32to32
mux3B(Bus_B_forwarded,EX_ReadData2,MEM_ALUResult,WB_WriteData,ForwardB
);
// mux 2x32 to 32 chon nguon cho Bus B cua ALU
mux2x32to32 muxALUSrc( Bus_B_ALU,Bus_B_forwarded,EX_Im16_Ext,
EX_ALUSrc);
// ALU Control
ALUControl_Block ALUControl_Block1( ALUControl, EX_ALUOp, EX_Im16_Ext[5:0]);
// chu y EX_Im16_Ext[5:0] chinh la truong function
// ALU
alu alu_block(EX_ALUResult, CarryFlag, ZeroFlag, OverflowFlag, NegativeFlag,
Bus_A_ALU, Bus_B_ALU, ALUControl);
// mux 2x5 to 5 chon thanh ghi dich la Rd hay Rt
mux2x5to5 muxRegDst( EX_WriteRegister,EX_rt,EX_rd, EX_RegDst);
//==============MEM STAGE=================
// Thanh ghi EX/MEM
register EXMEM_ALUResult(MEM_ALUResult,EX_ALUResult,1'b1,reset,clk);
register EXMEM_WriteDataOfMem(WriteDataOfMem,
Bus_B_forwarded,1'b1,reset,clk);
RegBit EXMEM_MemtoReg(MEM_MemtoReg, EX_MemtoReg, 1'b1,reset, clk);
RegBit EXMEM_RegWrite(MEM_RegWrite, EX_RegWrite, 1'b1,reset, clk);
RegBit EXMEM_MemRead(MEM_MemRead, EX_MemRead, 1'b1,reset, clk);
RegBit EXMEM_MemWrite(MEM_MemWrite, EX_MemWrite, 1'b1,reset, clk);
RegBit EXMEM_WriteRegister4(MEM_WriteRegister[4], EX_WriteRegister[4],
1'b1,reset, clk);
RegBit EXMEM_WriteRegister3(MEM_WriteRegister[3], EX_WriteRegister[3],
1'b1,reset, clk);
RegBit EXMEM_WriteRegister2(MEM_WriteRegister[2], EX_WriteRegister[2],
1'b1,reset, clk);
RegBit EXMEM_WriteRegister1(MEM_WriteRegister[1], EX_WriteRegister[1],
1'b1,reset, clk);
RegBit EXMEM_WriteRegister0(MEM_WriteRegister[0], EX_WriteRegister[0],
1'b1,reset, clk);
// Data Memory

dataMem dataMem1(MEM_ReadDataOfMem, //data

MEM_ALUResult,
//address
WriteDataOfMem,
//writedata
MEM_MemWrite,
//writeenable
MEM_MemRead,
clk);
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//==========WB STAGE====================
// thanh ghi MEM/WB
register
MEMWB_ReadDataOfMem(WB_ReadDataOfMem,MEM_ReadDataOfMem,1'b1,reset
,clk);
register MEMWB_ALUResult(WB_ALUResult,MEM_ALUResult,1'b1,reset,clk);
RegBit MEMWB_WriteRegister4(WB_WriteRegister[4], MEM_WriteRegister[4],
1'b1,reset, clk);
RegBit MEMWB_WriteRegister3(WB_WriteRegister[3], MEM_WriteRegister[3],
1'b1,reset, clk);
RegBit MEMWB_WriteRegister2(WB_WriteRegister[2], MEM_WriteRegister[2],
1'b1,reset, clk);
RegBit MEMWB_WriteRegister1(WB_WriteRegister[1], MEM_WriteRegister[1],
1'b1,reset, clk);
RegBit MEMWB_WriteRegister0(WB_WriteRegister[0], MEM_WriteRegister[0],
1'b1,reset, clk);
RegBit MEMWB_MemtoReg(WB_MemtoReg, MEM_MemtoReg, 1'b1,reset, clk);
RegBit MEMWB_RegWrite(WB_RegWrite, MEM_RegWrite, 1'b1,reset, clk);
// Select Data to WriteData for regfile
mux2x32to32 muxMemtoReg( WB_WriteData, WB_ALUResult,
WB_ReadDataOfMem,WB_MemtoReg);
//Stalling
StallControl
StallControl_block(PC_WriteEn,IFID_WriteEn,Stall_flush,EX_MemRead,EX_rt,rs,rt);
// Cac lenh nhay Jump,bne, JRs
// lenh bne: Branch if not equal
shift_left_2 shiftleft2_bne(shiftleft2_bne_out, EX_Im16_Ext);
Add Add_bne(PCbne,EX_PC4,shiftleft2_bne_out);
not #(50) notZero(notZeroFlag,ZeroFlag);
and #(50) andbneControl(bneControl,EX_Branch,notZeroFlag);
mux2x32to32 muxbneControl( PC4bne,PC4, PCbne, bneControl);
// lenh jump
shift_left_2 shiftleft2_jump(shiftleft2_jump_out, {6'b0,ID_Instruction[25:0]});
assign PCj = {ID_PC4[31:28],shiftleft2_jump_out[27:0]};
not #(50) notIFIDFlush(notIFID_flush,IFID_flush);
and #(50) andJumpFlush(JumpFlush,Jump,notIFID_flush);
not #(50) notbne(notbneControl,bneControl);
and #(50) andJumpBNE(JumpControl,JumpFlush,notbneControl);
mux2x32to32 muxJump( PC4bnej,PC4bne, PCj, JumpControl);
// lenh JR: Jump Register
assign PCjr = Bus_A_ALU;
mux2x32to32 muxJR( PCin,PC4bnej, PCjr, EX_JRControl);

endmodule
module mux2_1(O,A,B,sel);
// sel = 0 thi O = A
// sel = 1 thi O =B
output O;
input A,B,sel;
not #(50) not1(nsel,sel);
and #(50) and1(O1,A,nsel);
and #(50) and2(O2,B,sel);
or #(50) or2(O,O1,O2);
endmodule

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 N CU TRC MY TNH LAB 4

ON CODE ASM:
a
ch (
thp
0 phn)

Xori $s1, $0, 0x0002

00111000000100010000000000000010

Xori $s2, $0, 0x0006

00111000000100100000000000000110

J lableB

00001000000000000000000000000101

12

Xori $s1 , $0, 0x0002

00111000000100010000000000000010

16

Xori $s2, $0, 0x0002

00111000000100100000000000000010

20

Sub $s3, $s2, $s1

00000010010100011001100000100010

24

Bne $s1, $s2, lableA

00010110001100101111111111111100

28

Add $s4, $s1, $s2

00000010001100101010000000100000

32

Sw $s4, 8($s3)

10101110011101000000000000001000

36

Lw $5, 8($3)

10001110011101010000000000001000

40

Slt $s6, $s2, $s5

00000010010101011011000000101010

44

Xori $s6, $s6, 0x0001

00111010110101100000000000000001

48

Jr $6

00000010110000000000000000001000

Lnh

M my

52
56

NHM 37

.............

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