You are on page 1of 127

R.

Lauwereins Imec 2001

Course contents
Digital design Combinatorial circuits: it!out status Sequential circuits: it! status FSMD design: !ard ired "rocessors Language based H# design: VHDL

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/$

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5//

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


&cron)m:
VHDL 1 VHS%C Hard are Descri"tion Language VHS%C 1 Ver) Hig! S"eed %ntegrated Circuit

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

#!at is VHDL2
& "rogramming language 'or describing t!e be!a*ior o' digital s)stems Design entr) language+ used 'or 3nambiguous s"eci'ication at be!a*ioral and 45L le*el Simulation 6e.ecutable s"eci'ication78 S)nt!esis Documentation

Standardisation: %999 1:;<


First *ersion: 1=>< Second *ersion: 1==/ ?e *ersion about to a""ear
5/0

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


#!en to use VHDL instead o' sc!ematics2
Dra bac(s:
VHDL is eas) to learn but !ard to master 6semantics are quite di''erent 'rom so't are languages8 VHDL !as a di''icult s)nta. 6Language sensiti*e editors it! tem"lates 'or all language constructs8 VHDL is *er) @ ord)A: lots o' code to t)"e 'or Bust a 'e sim"le t!ings & list o' instructions is less intuiti*e to understand t!an a bloc( diagram 'or a !uman being VHDL is designed to ma(e simulation e''icient: contains as"ects t!at !a*e !ardl) an)t!ing to do it! !ard are be!a*ior+ but is use'ul to s"eed-u" e*ent dri*en simulation

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/5

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


#!en to use VHDL instead o' sc!ematics2
9asier to ca"ture com"le. circuits: !ig!er le*el o' abstraction it! automated s)nt!esis

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

)ou s"eci') @addA instead o' Botting do n a s"eci'ic t)"e o' adder: t!e s)nt!esis tool ill instantiate t!e best t)"e o' adder under timing+ area C "o er constraints eas) to "arametrise 6e,g, ord lengt!+ queue de"t!8 eas) to s"eci') arra)s o' com"onents
Dortable across man) tools 'or simulation+ s)nt!esis+ anal)sis+ *eri'ication+ 7 o' di''erent *endors 6e,g, S)no"s)s+ Mentor Era"!ics+ 78

5/<

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


Limitations o' VHDL
5!e standard onl) describes s)nta. and semantics+ but not t!e coding st)le
)ou can s"eci') t!e same be!a*ior 6e,g, M3-8 in an almost unlimited number o' a)s eac! leading to a com"letel) di''erent im"lementation 6e,g, Multi"le.or or tri-state bus8 !ic! is s)nt!esis tool de"endent, Fou s!ould do lots o' e."erimentation it! st)letool combinations to be able to "redict !o t!e !ard are ill loo( li(e t!at ill be s)nt!esised, %s "rediction necessar)2 Fou also do not "redict t!e &SM generated b) CG C is less e''icient t!an &SM but 'aster to rite, Currentl)+ it is !ard to tolerate t!e ine''icienc) caused b) t!e !ig!er le*el s"eci'ication 'or !ard are, ?ote: 'or DSD "rocessors "rogrammed in C+ e do "redict &SM and !a*e to e."eriment it! st)lecom"iler combinations 'or e''icienc) reasonsHH

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/;

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


Limitations o' VHDL 6ctud8
Inl) a subset o' VHDL can be automaticall) s)nt!esisedG eac! *endor su""orts a di''erent subset Inl) digitalG s"ecial e.tension 6not )et idel) ado"ted8 'or analog: VHDL-&MS 6acron)m 'or VHDL &nalog and Mi.ed Signal8

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

%999 standard 1:;<,1-1=== is a su"er-set o' t!e 'ull %999 VHDL 1:;<-1==/ standard 'or digital design

5/>

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


&bstraction le*els
Je!a*ioral

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

%nterconnected 'unctions Inl) in'o on 'unctions or algorit!ms 6 !at8 Inl) timing needed to let t!e 'unction or( correctl) IK 'or VHDL Je!a*ioral s)nt!esisers immatureG used 'or !ig! le*el e.ecutable s"eci'ication in to"-do n design and manual s)nt!esis into 45L

5/=

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


&bstraction le*els
45L
%nterconnected registers and combinatorial units %n'o on 'unction 6 !at8 and arc!itecture 6!o 8 C)cle accurate ?o tec!nolog) de"endent timing in'o IK 'or VHDL Eood s)nt!esisers

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Eate le*el
%nterconnected gates and 'li"-'lo"s %n'o on 'unction and arc!itecture %n'o on tec!nolog) de"endent timing 6gate dela)s8

La)out
%n'o on la)out on silicon Continuous timing &nalog e''ects
5/1:

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


It!er !ard are descri"tion languages 6HDL8
Verilog

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

More ides"read in 3S& t!an in 9uro"e I'ten required 'or gate le*el or 45L le*el &S%C sign-o'' ?e*er ending discussion !ic! is better
DLD languages li(e &J9L+ D&L&SM+ 7

5!ese are more at t!e gate le*el+ ca"turing also tec!nolog) de"endent 'eatures 6e,g, detailed timing8
5/11

R.Lauwereins Imec 2001

VHDL "rimer: %ntroduction


Di''erence bet een HDLs and traditional so't are "rogramming languages
Concurrenc): all !ard are com"onents o"erate in "arallel Data t)"es: su""ort is needed 'or arbitrar) siLe integers+ bit *ectors+ 'i.ed "oint numbers Conce"t o' time

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1$

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1/

R.Lauwereins Imec 2001

& First loo( at VHDL: 9.am"le 1 tas( descri"tion


Design a circuit named @5estA it! / >-bit in"uts 6%n1+ %n$+ %n/8 and t o boolean out"uts 6Iut1+ Iut$8, 5!e 'irst out"ut equals @1A !en t!e 'irst and second in"ut are equalG t!e second out"ut equals @1A !en t!e 'irst and t!ird in"ut are equal, LetAs 'irst ma(e a sc!ematic design:

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/10

R.Lauwereins Imec 2001

& First loo( at VHDL: Sc!ematic s"eci'ication


5!e circuit ill be !ierarc!icall) decom"osed into a to" le*el com"onent @5estA containing $ instantiations o' a com"arator com"onent @Com"areA
5est %n1 Com"are & 9M %n$ J Com"are & %n/ J 9M Iut$ Iut1

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/15

R.Lauwereins Imec 2001

& First loo( at VHDL: Sc!ematic s"eci'ication


5!e com"arator is t!en !ierarc!icall) decom"osed into a gate le*el combinatorial circuit
Com"are & &N:O JN:O &N1O JN1O &?D 9M 9M -?I4

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

&N;O JN;O

5/1<

R.Lauwereins Imec 2001

& First loo( at VHDL: 9ntit) and &rc!itecture


Declaration o' t!e @Com"areA design entit): @9ntit)A s"eci'ies
-- 9ig!t bit com"arator -entit) Com"are is "ort6 &+J: in bitP*ector6: to ;8G 9M: out bit8G end entit) Com"areG t!e inter'ace to t!e circuit+ t!e blac( bo. o' a sc!ematic

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

arc!itecture Je!a*1 o' Com"are is begin @&rc!itectureA describes 9M Q1 @1A !en 6&1J8 else @:AG t!e be!a*ior and structure end arc!itecture Je!a*1G o' t!e entit)+ t!e internals o' t!e bo. ?otes: - Multi"le arc!itectures "er entit) are "ossible: di''erent a)s o' im"lementing same be!a*ior - 5!is arc!itecture s"eci'ies be!a*ior at 45L le*el and not t!e actual structure o' gatesG s)nt!esis tool ill automaticall) translate t!is 45L be!a*ioral descri"tion into gate le*el - Dorts !a*e an e."licit direction and are 6*ectors o'8 bits

%n"ut and out"ut signals are called @"ortsA

5/1;

R.Lauwereins Imec 2001

& First loo( at VHDL: Com"onent and %nstantiation


-- Dual com"arator 5est com"onent -entit) 5est is "ort6 %n1+%n$+%n/: in bitP*ector6: to ;8G Iut1+Iut$: out bit8G end entit) 5estG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

S"eci'ication o' t!e ne.t !ig!er le*el in t!e circuit !ierarc!): @5estA

arc!itecture Struct1 o' 5est is com"onent Com"arator is 5 o instantiations "ort6 -+F: in bitP*ector6: to ;8G o' t!e same com"onent R: out bit8G @Com"aratorA it! its end com"onent Com"aratorG signal binding begin Com"are1: com"onent Com"arator "ort ma" 6%n1+%n$+Iut18G Com"are$: com"onent Com"arator "ort ma" 6%n1+%n/+Iut$8G end arc!itecture Struct1G ?otes: - 5!e t o @com"aratorA com"onents or( concurrentl)HHH - 5!is arc!itecture describes structure+ i,e, !o t!is entit) consists o' an interconnection o' lo er le*el com"onents

Virtual de*ice: allo s 'or concurrent de*elo"ment o' bot! !ierarc!ical le*els+ b) di''erent "ersons, @Com"aratorA ill be bound to @Com"areA later

5/1>

R.Lauwereins Imec 2001

& First loo( at VHDL: Com"arison it! C


5!is is *er) similar to so't are "rogramming languages+ e,g, C
/S 9ig!t bit com"arator S/ int Com"are 6int &+ int J8 T return 6& 11 J8G U %nter'ace to t!e 'unction %n"uts and out"uts are called @argumentsA Je!a*ior o' t!e 'unction

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

?otes: - Inl) one be!a*ior "er 'unction "ossible - Je!a*ior is s"eci'ied at rat!er !ig! le*el and ill be automaticall) translated b) t!e com"iler into &SM instructions - Function arguments do not !a*e a direction and are o' t)"e int
5/1=

R.Lauwereins Imec 2001

& First loo( at VHDL: Com"arison it! C


5!is is !o t!e !ig!er !ierarc!ical le*el loo(s li(e in C
/S Dual com"arator 5est "rogram S/ main68 T int %n1+ %n$+ %n/G int Iut1+ Iut$G Iut1 1 Com"are6%n1+ %n$8G Iut$ 1 Com"are6%n1+ %n/8G U 5 o calls to t!e 'unction @Com"areA it! its argument binding

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

?otes: - 5!e t o @com"areA 'unction calls are e.ecuted sequentiall) - 5!is main "rogram is e.ecuted once and sto"s, %n VHDL+ all com"onents describe relations t!at are *alid continuousl) and 'ore*er

5/$:

R.Lauwereins Imec 2001

& First loo( at VHDL: Con'iguration


#!en an entit) !as multi"le arc!itectures+ !o !ic! one to use2 Ho do )ou bind @Com"onentsA to @9ntitiesA2 do )ou indicate

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

-- Con'iguration in'ormation: arc!itecture selection -- and com"onent-entit) binding Jot! @use entit)As could be combined in one: con'iguration Juild1 o' 5est is 'or &ll: Com"arator ,,, 'or Struct1 'or Com"are1: Com"arator use entit) Com"are6Je!a*18 "ort ma" 6& 1V -+ J 1V F+ 9M 1V R8G end 'orG 'or ot!ers: Com"arator use entit) Com"are6Je!a*18 "ort ma" 6& 1V -+ J 1V F+ 9M 1V R8G end 'orG end 'orG end con'iguration Juild1G ?ote: @con'igurationA corres"onds in S# to @lin(ingA

5/$1

R.Lauwereins Imec 2001

& First loo( at VHDL: S)nta.


9?5%5F: entit) 9ntit)Pname is "ort6 SignalPname: in SignalPt)"eG SignalPname: out SignalPt)"e8G end entit) 9ntit)PnameG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

&4CH%59C5349: arc!itecture &rc!itecturePname o' 9ntit)Pname is localPsignalPdeclarationsG com"onentPdeclarationsG begin statementsG end arc!itecture &rc!itecturePnameG

5/$$

R.Lauwereins Imec 2001

& First loo( at VHDL: S)nta.


CIMDI?9?5: com"onent Com"onentPname is "ort6 SignalPname: in SignalPt)"eG SignalPname: out SignalPt)"e8G end com"onent Com"onentPnameG CIMDI?9?5 %?S5&?5%&5%I?: -- com"onent instantiation %nstancePname: com"onent Com"onentPname "ort ma" 6SignalPlist8G or -- direct instantiation %nstancePname: entit) 9ntit)Pname6&rc!itecturePname8 "ort ma" 6SignalPlist8G S%E?&L L%S5: -- t o *ariants: -- *ariant 1: ordered list o' signals as in so't are languages -- e,g, 6%n1+%n$+Iut18 Locall) used name -- *ariant $: named list -- e,g, 6J 1V %n$+ 9M 1V Iut1+ & 1V %n18 ?ame used in com"onent declaration

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/$/

R.Lauwereins Imec 2001

& First loo( at VHDL: S)nta.


CI?F%E34&5%I?: con'iguration Con'igPname o' 9ntit)Pname is 'or &rc!itecturePname 'or %nstancePname: Com"onentPname use entit) 9ntit)Pname6&rc!itecturePname8 "ort ma" 6SignalPlist8G end 'orG end 'orG end con'iguration Con'igPnameG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/$0

R.Lauwereins Imec 2001

& First loo( at VHDL: 9.am"le $


Declare a /-in"ut &?D gate
& J C F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

-- /-in"ut &?D gate entit) &?D/ is "ort 6 &+J+C: in bitG F: out bit8G end entit) &?D/G arc!itecture 45L o' &?D/ is begin F Q1 @1A !en 66&1@1A8 and 6J1@1A8 and 6C1@1A88 else @:AG end arc!itecture 45LG

5/$5

R.Lauwereins Imec 2001

& First loo( at VHDL: 9.am"le $


Declare a /-in"ut I4 gate
& J C F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

-- /-in"ut I4 gate entit) I4/ is "ort 6 &+J+C: in bitG F: out bit8G end entit) I4/G arc!itecture 45L o' I4/ is begin F Q1 @:A !en 66&1@:A8 and 6J1@:A8 and 6C1@:A88 else @1AG end arc!itecture 45LG

5/$<

R.Lauwereins Imec 2001

& First loo( at VHDL: 9.am"le $


Declare an %?V gate
& -- %?V gate entit) %?V is "ort 6 &: in bitG F: out bit8G end entit) %?VG arc!itecture 45L o' %?V is begin F Q1 @1A !en 6&1@:A8 else @:AG end arc!itecture 45LG F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/$;

R.Lauwereins Imec 2001

& First loo( at VHDL: 9.am"le /


Juild a $-to-1 M3- using bot! a be!a*ioral as ell as a structural descri"tion
& J entit) M3-$1 is "ort 6 &+J+S: in bitG F: out bit8G end entit) M3-$1G 5!e blac( bo. inter'ace S F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

arc!itecture Je!a* o' M3-$1 is begin F Q1 & !en 6S1@1A8 else JG end arc!itecture Je!a*G

Je!a*ioral descri"tion

5/$>

R.Lauwereins Imec 2001

& First loo( at VHDL: 9.am"le /


Juild a $-to-1 M3- using bot! a be!a*, as ell as a structural descri"tion &
arc!itecture Struct o' M3-$1 is J signal 3+V+# : bitG com"onent &?D$ is S "ort 6 -+F: in bitG Structural descri"tion R: out bit8G end com"onent &?D$G com"onent I4$ is & # "ort 6 -+F: in bitG R: out bit8G S F end com"onent I4$G com"onent %?V is V 3 "ort 6 -: in bitG J R: out bit8G end com"onent %?VG begin Eate1: com"onent %?V "ort ma" 6-1VS+R1V38G Eate$: com"onent &?D$ "ort ma" 6-1V&+F1VS+R1V#8G Eate/: com"onent &?D$ "ort ma" 6-1V3+F1VJ+R1VV8G Eate0: com"onent I4$ "ort ma" 6-1V#+F1VV+R1VF8G end arc!itecture StructG F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/$=

R.Lauwereins Imec 2001

& First loo( at VHDL: 9.am"le /


&ssume t!at e ant to use t!e "re*iousl) declared &?D/+ I4/ and %?V 'or t!is structural descri"tion o' M3con'iguration 3se/%n"utEates o' M3-$1 is 'or Je!a* end 'orG 'or Struct 'or Eate1:%?V use entit) %?V645L8 "ort ma" 6&1V-+F1VR8G end 'orG 'or &ll:&?D$ use entit) &?D/645L8 "ort ma" 6&1V-+J1VF+C1VA1A+F1VR8G end 'orG 'or Eate0:I4$ use entit) I4/645L8 "ort ma" 6&1V-+J1VF+C1VA:A+F1VR8G end 'orG end 'orG end con'iguration 3se/%n"utEatesG 9ntities & J C & F F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Com"onents R F R

5//:

R.Lauwereins Imec 2001

& First loo( at VHDL: 5est benc!


Ho can made2 e *eri') t!e circuit t!at e
#e !a*e to a""l) re"resentati*e stimuli to t!e circuit and c!ec( !et!er t!e out"uts are correct

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& VHDL @test benc!A can be considered to be t!e to" le*el o' a design
%t instantiates t!e Design 3nder 5est 6D358 a""lies stimuli to it c!ec(s !et!er t!e stimuli are correct or ca"tures t!e out"uts 'or *isualisation in a a*e'orm *ie er

5//1

R.Lauwereins Imec 2001

& First loo( at VHDL: 5est benc!


Create a test benc! 'or t!e be!a*ioral *ersion o' t!e M3entit) 5estbenc! is end entit) 5estbenc!G 5estbenc! is sel'-contained: no "orts & J M3-$1 S arc!itecture Je!a*5est o' 5estbenc! is Signal %n1+%n$+Select+Iut : bitG begin D35: entit) M3-$16Je!a*8 "ort ma" 6%n1+ %n$+ Select+ Iut8G Stimulus: "rocess is begin %n1Q1@:AG%n$Q1@1AGSelectQ1@:AG ait 'or $: nsG SelectQ1@1AG ait 'or $: nsG %n1Q1@1AG%n$Q1@:AG ait 'or $: nsG ,,, end "rocess StimulusG end arc!itecture Je!a*5estG F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5//$

R.Lauwereins Imec 2001

& First loo( at VHDL: 4e-use


I'ten+ "arts o' a design can be re-used in anot!er design ?e "roducts in industr) o'ten contain =5W o' re-used "arts and 5W is ne l) designed: e*olutionar) design VHDL encourages t!is b) t!e conce"t o' @Dac(agesA & @Dac(ageA contains de'initions o' constant *alues+ com"onent declarations+ user data t)"es+ and sub-"rograms o' VHDL code Jut 'irst t!e conce"t @Librar)A: a librar) is name o' director) into !ic! t!e binar) code resulting 'rom anal)sis/com"ilation is stored, De'ault: #I4K

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5///

R.Lauwereins Imec 2001

& First loo( at VHDL: 4e-use


Dac(age inter'ace declaration: "ac(age Dac(agePname is -- constants -- user de'ined t)"es -- com"onent declarations -- sub "rograms end "ac(age Dac(agePnameG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Ho

to use a "ac(age2

use Librar)Pname,Dac(agePname,allG 7 31: entit) Dac(agePname,9ntit)Pname6&rc!itecturePname8G

5//0

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5//5

R.Lauwereins Imec 2001

Signals and Data 5)"es: Drede'ined signal t)"es


"ac(age Standard is t)"e Jit is 6@:A+A1A8G t)"e Joolean is 6False+ 5rue8G t)"e C!aracter is 6--&SC%% set8G t)"e %nteger is range im"lementationPde'inedG t)"e 4eal is range im"lementationPde'inedG t)"e JitP*ector is 6--arra) o' bits8G t)"e String is 6--arra) o' c!aracters8G t)"e 5ime is range im"lementationPde'inedG end "ac(age StandardG Jit+ Joolean and C!aracter are enumeration t)"es &ll standard t)"es are @unresol*edA 6see later 'or t!e meaning o' t!is8

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5//<

R.Lauwereins Imec 2001

Signals and Data 5)"es: Drede'ined signal t)"es


9.am"les o' integer declarations: t)"e Fear is range : to ==G t)"e Memor)Paddress is range <55/5 do nto :G 9.am"les o' real declarations: t)"e Drobabilit) is range :,: to 1,:G t)"e %n"utPle*el is range -5,: to 5,:G C!ec(ed b) simulator

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& JitP*ector is a collection o' bitsG a *alue is s"eci'ied bet een double quotes: constant State1: bitP*ector60 do nto :8 :1 X::1::YG MSJ+ bit 0 & String is a collection o' c!aractersG a *alue is s"eci'ied bet een double quotes: constant 9rrorPmessage: string :1 X3n(no n error: as( )our "oor s)so" 'or !el"YG LSJ

5//;

R.Lauwereins Imec 2001

Signals and Data 5)"es: Drede'ined signal t)"es


5ime is a "!)sical t)"e: t)"e 5ime is range im"lementationPde'ined units 'sG Drimar) unit: "s 1 1::: 'sG resolution limit ns 1 1::: "sG us 1 1::: nsG ms 1 1::: usG Secondar) units sec 1 1::: msG min 1 <: secG !r 1 <: minG end unitsG 9.am"les o' use: ait'or $: nsG constant Sam"leP"eriod: time :1 $ msG constant Cloc(P"eriod: time :1 5: nsG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5//>

R.Lauwereins Imec 2001

Signals and Data 5)"es: 3ser de'ined "!)sical t)"es


5!e user ma) de'ine !is/!er o n "!)sical t)"es: t)"e Lengt! is range : to 19= units Drimar) unit: umG resolution limit mm 1 1::: umG m 1 1::: mmG Metric secondar) units (m 1 1::: mG mil 1 $50 umG inc! 1 1::: milG 'oot 1 1$ inc!G %m"erial secondar) units )ard 1 / 'ootG end unitsG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5//=

R.Lauwereins Imec 2001

Signals and Data 5)"es: 3ser de'ined enumeration t)"es


5!e user ma) de'ine !is/!er o n enumeration t)"es: t)"e FSMPstates is 6reset+ ait+ in"ut+ calculate+ out"ut8G

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

?ot all s)nt!esis tools su""ort enumerated t)"es #!en t!e) do su""ort t!em+ t!e de'ault encoding is o'ten straig!t'or ard encoding using t!e minimum number o' bits I'ten+ t!e de'ault encoding ma) be o*er- ritten b) some !ere s"eci')ing somet!ing li(e XencodingPst)le is gra)PcodeY or b) e."licitl) s"eci')ing t!e encoding 'or eac! "ossible *alue: constant reset: bitP*ector :1 X1::::YG constant ait: bitP*ector :1 X:1:::YG constant in"ut: bitP*ector :1 X::1::YG constant calculate: bitP*ector :1 X:::1:YG constant out"ut: bitP*ector :1 X::::1YG

5/0:

R.Lauwereins Imec 2001

Signals and Data 5)"es: &rra) t)"es


5!e user ma) de'ine arra)s o' t)"es: t)"e 1DParra) is arra) 61 to 1:8 o' integerG t)"e $DParra) is arra) 65 do nto :+ 1 to 1:8 o' realG Kee" in mind t!at a *ector o' bits !as ?I numerical meaning and t!at !ence arit!metic o"erations on *ectors o' bits ma(e no sense: signal Jus+&ddress : bitP*ector 6: to /8G Jus Q1 &ddress Z 1G -- 5!is ma(es no senseHHH Solution: *ia o"erator o*erloading 6c', CZZ8: - t o 'unctions @ZA ill e.ist+ one or(ing on integers and one or(ing on *ectors o' bits - t!e latter is de'ined in a *endor s"eci'ic @*ector arit!metic "ac(ageA t!at s!ould be useAd at t!e beginning o' )our VHDL

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/01

R.Lauwereins Imec 2001

Signals and Data 5)"es: Standard logic


#e !a*e seen t!at e need more logic le*els t!an Bust @:A and @1A 6e,g, donAt care+ un(no n a'ter setu" *iolation+ 78 5!ere'ore t!e %999 de'ined in standard number 11<0 =-*alued logic signals and o"erations on t!em: use al a)s t!ose instead o' @bitAHH 9.ists in unresol*ed 'orm 6stdPulogic8 and resol*ed 'orm 6stdPlogic8 -- again: see later 'or meaning 9.ists in single bit and arra) 'orm:
constant constant constant constant &: J: C: D: stdPulogic :1 @3AG -- unitialiLed stdPlogic :1 @3AG stdPulogicP*ector 6: to 158G stdPlogicP*ector 615 do nto :8G

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/0$

R.Lauwereins Imec 2001

Signals and Data 5)"es: Standard logic


librar) %999G use %999,StdPlogicP11<0,&llG t)"e stdPlogic is 6 @3A+ -- uninitialiLed e,g, a'ter "o er-u" @-A+ -- strongl) dri*en un(no n e,g, a'ter setu" *iolation @:A+ -- strongl) dri*en logic Lero @1A+ -- strongl) dri*en logic one @RA+ -- !ig! im"edance e,g, not dri*en at all @#A+ -- ea(l) dri*en un(no n @LA+ -- ea(l) dri*en logic Lero @HA+ -- ea(l) dri*en logic one @-A8G -- donAt care

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/0/

R.Lauwereins Imec 2001

Signals and Data 5)"es: &ssignment to signals


%s t!e 'ollo ing code *alid2 signal R+&+J: stdPulogicG R Q1 &G R Q1 JG ?o+ because: - all statements are concurrentl) *alid and are not e.ecuted sequentiall) as in S# languages - !en &1@:A and J1@1A+ e !a*e a s!ort circuit & & 4esol*er circuit 4 J

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/00

R.Lauwereins Imec 2001

Signals and Data 5)"es: &ssignment to signals


VHDL is a single assignment language 'or unresol*ed data t)"es For resol*ed data t)"es 6stdPlogic C stdPlogicP*ector8+ t!e resol*er circuit is in'erred b) t!e s)nt!esis tool

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

signal R+&+J: stdPlogicG R Q1 &G R Q1 JG

&

4esol*er circuit 4

5/05

R.Lauwereins Imec 2001

Signals and Data 5)"es: &ssignment to signals


#!en an arra) is assigned to anot!er arra)+ bot! arra)s must !a*e same siLe &ssignment is b) "osition+ not b) inde.HHH
signal Do n: stdPlogicP*ector 6/ do nto :8G signal 3": stdPlogicP*ector 6: to /8G 3" Q1 Do nG #!ic! o' t!e t o 'ollo ing inter"retations is correct2

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

3"6:8 3"618 3"6$8 3"6/8


5/0<

Do n6/8 Do n6$8 Do n618 Do n6:8 I4

3"6:8 3"618 3"6$8 3"6/8

Do n6:8 Do n618 Do n6$8 Do n6/8

Corres"ondence b) "ositionH

R.Lauwereins Imec 2001

Signals and Data 5)"es: &ssignment to signals


&ssignment to a "art o' an arra) is "ossible Ma(e sure t!at t!e direction 6to or do nto8 is t!e same as in t!e declaration
signal Jus: stdPlogicP*ector 6; do nto :8G signal &: stdPlogicP*ector 6: to /8G #!ic! o' t!e 'ollo ing VHDL codes is correct2 Jus6: to /8 Q1 &G Jus Q1 &G Direction o' Jus di''ers 'rom declaration &rra) siLes do not matc! IKH Jus6/8 is dri*en b) &6:8 IKH Jus658 is dri*en b) &6:8 IKH Jus608 is dri*en b) &618 and b) &6$8: resol*ed data t)"e7 use it! careHH

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Jus6/ do nto :8 Q1 &G Jus65 do nto 08 Q1 &6: to 18G Jus65 do nto 08 Q1 &6: to 18G Jus60 do nto /8 Q1 &6$ to /8G
5/0;

R.Lauwereins Imec 2001

Signals and Data 5)"es: &ssignment to signals


@ConcatenationA: bring ire bundles toget!er to assign t!em to a bigger arra)
signal J)tePbus: stdPlogicP*ector6; do nto :8G signal ?ibblePbus&+ ?ibblePbusJ: stdPlogicP*ector6/ do nto :8G J)tePbus Q1 ?ibblePbus& C ?ibblePbusJG ?ibblePbus&6/8 ?ibblePbus&6$8 ?ibblePbus&618 ?ibblePbus&6:8

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

J)tePbus6;8 J)tePbus6<8 J)tePbus658 J)tePbus608 J)tePbus6/8 J)tePbus6$8 J)tePbus618 J)tePbus6:8

?ibblePbusJ6/8 ?ibblePbusJ6$8 ?ibblePbusJ618 ?ibblePbusJ6:8

5/0>

R.Lauwereins Imec 2001

Signals and Data 5)"es: &ssignment to signals


@&ggregationA: alternati*e met!od to assign multi"le small arra)s to a bigger arra) ?ot su""orted b) all s)nt!esis toolsHH
signal -+F+R+5: stdPlogicP*ector6/ do nto :8G signal &+J+C: stdPlogicG - Q1 6&+J+C+C8G -- corres"ondence b) "osition F Q1 6/ 1V &+ 1 do nto : 1V C+ $ 1V J8G R Q1 6/ 1V &+ $ 1V J+ ot!ers 1V C8G 5 Q1 6ot!ers 1V @:A8G -- initialiLation irres"ecti*e o' idt! o' 5

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/0=

R.Lauwereins Imec 2001

Signals and Data 5)"es: Eeneric constants


&llo s to "arameteriLe be!a*ior 9nables re-use o' entities in slig!tl) c!anging en*ironments Ma(es VHDL muc! more "o er'ul t!an sc!ematic entr) Eeneric constants need to !a*e a *alue at s)nt!esis timeH
entit) EeneralPmu. is generic 6 idt! : integer8G "ort 6 %n"ut : in stdPlogicP*ector 6 idt! - 1 do nto :8G Select : in integer range : to idt! - 1G Iut"ut : out stdPlogic8G end entit) EeneralPmu.G

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/5:

R.Lauwereins Imec 2001

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

entit) EeneralPmu. is generic 6 idt! : integer8G "ort 6 %n"ut : in stdPlogicP*ector 6 idt! - 1 do nto :8G Select : in integer range : to idt! - 1G Iut"ut : out stdPlogic8G end entit) EeneralPmu.G 5!is is not *alid VHDL: inde. is not (no n at arc!itecture Je!a* o' EeneralPmu. is design timeH #e ill begin re"lace t!is b) *alid Iut"ut Q1 %n"ut6Select8G code laterH end arc!itecture Je!a*G entit) 5estbenc! is end entit) 5estbenc!G arc!itecture Juild1 o' 5estbenc! is constant %n"utPsiLe : integer :1 >G signal & : stdPlogicP*ector 6%n"utPsiLe-1 do nto :8G signal S : integer range : to %n"utPsiLe - 1G signal J : stdPlogicG begin D35: entit) EeneralPmu.6Je!a*8 generic ma" 6 idt! 1V %n"utPsiLe8 "ort ma" 6%n"ut 1V &+ Select 1V S+ Iut"ut 1V J8G ,,, end arc!itecture Juild1G

Eeneric constants

5/51

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/5$

R.Lauwereins Imec 2001

Logical I"erators
List o' logical o"erators: not+ and+ or+ .or+ nand+ nor Drecedence:
@notA !as !ig!est "recedence all ot!ers !a*e equal "recedence+ lo er t!an @notA

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Logical o"erators are "rede'ined 'or 'ollo ing data t)"es: bit+ bitP*ector+ boolean+ stdPlogic+ stdPlogicP*ector+ stdPulogic+ stdPulogicP*ector & logical o"erator ma) or( on an arra):
arra)s s!ould !a*e same siLe elements are matc!ed b) "osition

5/5/

R.Lauwereins Imec 2001

Logical I"erators

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

librar) %999G use %999,StdPLogicP11<0,&llG entit) Eate is "ort6 &+J+C: in stdPlogicG R: out stdPlogic8G end entit) EateG arc!itecture Logical o' Eate is begin R Q1 & and not6J or C8G end arc!itecture LogicalG

5/50

R.Lauwereins Imec 2001

Logical I"erators
librar) %999G use %999,StdPLogicP11<0,&llG entit) Eate is generic6 idt! : integer range : to /18G "ort6 &+J+C: in stdPlogicP*ector6 idt!-1 do nto :8G R: out stdPlogicP*ector6 idt!-1 do nto :88G end entit) EateG arc!itecture Logical o' Eate is begin R Q1 & and not6J or C8G end arc!itecture LogicalG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/55

R.Lauwereins Imec 2001

4elational I"erators
List o' relational o"erators: Q+ Q1+ 1V+ V+ 1+ /1 4elational o"erators return a boolean Jot! o"erands need to be o' t!e same t)"e & relational o"erator ma) or( on an arra):
arra)s ma) !a*e di''erent siLeHH 5!e) are le't alligned and t!e number o' bits equal to t!e smallest arra) are com"aredG t!e com"arison is done bit b) bit+ 'rom le't to rig!t 4emember: *ectors o' bits do not !a*e a numerical meaningHH Ho e*er+ t!is com"arison or(s on *ectors o' bits it! t!e meaning o' an unsigned integer !en bot! *ectors !a*e equal lengt!

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/5<

R.Lauwereins Imec 2001

4elational I"erators
librar) %999 use %999,StdPLogicP11<0,&llG entit) Com"are is "ort6 &: in stdPlogicP*ector6/ do nto :8G J: in stdPlogicP*ector6: to 08G R: out boolean8G end entit) Com"areG arc!itecture 4elational o' Com"are is begin R Q1 5439 !en &QJ else F&LS9G end arc!itecture 4elationalG entit) 5estbenc! end entit) 5estbenc!G arc!itecture Juild1 o' 5estbenc! is signal &: stdPlogicP*ector6/ do nto :8 :1 X111:YG signal J: stdPlogicP*ector6: to 08 :1 X1:111YG signal R: booleanG begin D35: entit) Com"are64elational8 "ort ma" 6& 1V &+ J 1V J+ R 1V R8G end arc!itecture Juild1G #!at is t!e *alue o' R2 54392 F&LS92 111: is com"ared to 1:11 b) bit "osition 'rom le't to rig!tG in t!e $nd "osition &6$8 V J618 !ence 6&QJ8 is F&LS9

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/5;

R.Lauwereins Imec 2001

&rit!metic I"erators
List o' arit!metic o"erators: Z+ -+ S+ /+ SS 6e."onential8+ abs 6absolute *alue8+ mod 6modulus8+ rem 6remainder8 5!e) are de'ined on t)"es integer and real 6e.ce"t mod and rem8 and not on *ectors o' bitsG use o*erloading "ac(age 'or t!e latter 6*endor de"endent8 Jot! o"erands !a*e to be o' same t)"eG di''erent ranges are allo ed & *ariable o' "!)sical t)"e 6e,g, time8 ma) be multi"lied b) an integer or real and ill still return a *ariable o' t!e "!)sical t)"e

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/5>

R.Lauwereins Imec 2001

&rit!metic I"erators
entit) &dd is "ort 6 &+J: in integer range : to ;G R: out integer range : to 108G end entit) &ddG arc!itecture Je!a* o' &dd is begin R Q1 & Z JG end arc!itecture Je!a*G

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/5=

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/<:

R.Lauwereins Imec 2001

Concurrent Statements
&ll statements are concurrent and are continuousl) *alid: t!is mimics t!e be!a*ior o' !ard are+ !ere all gates o"erate concurrentl)
entit) Concurrent is "ort 6 &+J+C+D: in stdPlogicG F+R: out stdPlogic8G end entit) ConcurrentG arc!itecture Struct o' Concurrent is begin ?&?D1: entit) ?&?D$ "ort ma" 6&+J+F8G ?&?D$: entit) ?&?D$ "ort ma" 6C+D+R8G end arc!itecture StructG #!at is t!e di''erence in be!a*ior a'ter ?&?D$2

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Sc!ematic: & J C D

F R

!en ?&?D1 is s"eci'ied

5/<1

R.Lauwereins Imec 2001

Concurrent Statements
&ll statements are concurrent and are continuousl) *alid: t!is mimics t!e be!a*ior o' !ard are+ !ere all gates o"erate concurrentl)
entit) Concurrent is "ort 6 &+J+C+D: in stdPlogicG F+R: out stdPlogic8G end entit) ConcurrentG arc!itecture Struct o' Concurrent is begin ?&?D$: entit) ?&?D$ "ort ma" 6C+D+R8G ?&?D1: entit) ?&?D$ "ort ma" 6&+J+F8G end arc!itecture StructG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Sc!ematic: & J C D

F R

Je!a*ior is e.actl) t!e sameHHH


5/<$

R.Lauwereins Imec 2001

Concurrent Statements
Does t!is sc!ematic s"eci') sequential Je!a*ior2 Fes ?o entit) Concurrent is "ort 6 &+J+ D: in stdPlogicG R: out stdPlogic8G end entit) ConcurrentG arc!itecture Struct o' Concurrent is signal 51: stdPlogicG begin ?&?D$: entit) ?&?D$ "ort ma" 651+D+R8G ?&?D1: entit) ?&?D$ "ort ma" 6&+J+518G end arc!itecture StructG & J D 51 R Sc!ematic:

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Jot! gates continuousl) u"date t!eir out"uts

5/</

R.Lauwereins Imec 2001

Simulation
5!is continuousl) u"dating o' out"uts "oses "roblems to t!e simulator: e*en i' not!ing in t!e circuit c!anges+ t!e simulator !as to com"ute continuousl) t!e @ne A out"uts o' all gates Solution: e*ent-dri*en simulation
a statement is onl) re-e*aluated !en one or more o' its in"ut signals c!anges 6i,e, !en an e*ent occurs at one o' its in"uts8 e sa) t!at a statement is sensiti*e to all its in"ut signals+ because an e*ent at an) in"ut signals triggers a re-e*aluation (ee" in mind t!at t!is mec!anism is onl) 'or ma(ing simulation 'ast !ile maintaining t!e same be!a*ior as in realit)+ !ere all gates or( continuousl)HH

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/<0

R.Lauwereins Imec 2001

Simulation
Ho is an e*ent-dri*en simulator "racticall) im"lemented2
1, Dut all statements it! at least one c!anged in"ut in t!e @"rocess e.ecution queueA $, 9.ecute all statements in t!e "rocess e.ecution queue one b) one 6or concurrentl) i' t!e simulator is e.ecuted on a "arallel com"uter8 it!out u"dating t!e out"ut signals /, &'ter all statements in t!e "rocess e.ecution queue are "rocessed+ u"date t!e out"ut signals 0, &dd all statements to t!e "rocess e.ecution queue t!at !a*e an e*ent because o' t!e u"dated out"ut signals 5, 4e"eat until t!e "rocess e.ecution queue is em"t) <, &d*ance s)stem time to t!e ne.t time !ere a timed e*ent is "lanned 6e,g, testbenc!: ait'or $: ns8 Delta c)cle con*ergence Delta c)cle

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/<5

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 ?&?D1 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" 1: Dut statements e*ent in D9M

it! in"ut

5/<<

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" $: 9.ecute statements in D9M and remember out"ut

5/<;

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 ?&?D$ & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" /: 3"date out"uts

5/<>

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 ?&?D$ & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

5/<=

Ste" 0: &dd statements to D9M 9nd Delta c)cle 1 o' 51

it! e*ent

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 : Drocess 9.ecution Mueue 51 ?&?D$ & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" $: 9.ecute statements in D9M and remember out"ut

5/;:

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 : Drocess 9.ecution Mueue 51 ?&?D$ & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" /: 3"date out"uts

5/;1

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 ?&?D1 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

5/;$

Ste" 0: &dd statements to D9M 9nd Delta c)cle $ o' 51

it! e*ent

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" $: 9.ecute statements in D9M and remember out"ut

5/;/

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 Drocess 9.ecution Mueue 51 ?&?D1 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" /: 3"date out"uts Iut"ut does not c!ange

5/;0

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

5/;5

Ste" 0: &dd statements it! e*ent to D9M 9nd Delta c)cle / o' 51: con*ergence

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$

Ste" <: &d*ance s)stem time

5/;<

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 M Q1 1 Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$ ?&?D$

5/;;

Ste" $: 9.ecute statements in D9M and remember out"ut ?&?D$ com"uted using t!is MA+ not t!e remembered 5$

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 1 M Q1 1 Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1 ?&?D$ ?&?D$

Ste" /: 3"date out"uts

5/;>

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1

5/;=

Ste" 0: &dd statements to D9M 9nd Delta c)cle 1 o' 5$

it! e*ent

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 : Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1

Ste" $: 9.ecute statements in D9M and remember out"ut

5/>:

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts MA Q1 : Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D1

Ste" /: 3"date out"uts

5/>1

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D$

5/>$

Ste" 0: &dd statements to D9M 9nd Delta c)cle $ o' 5$

it! e*ent

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 1 Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D$

Ste" $: 9.ecute statements in D9M and remember out"ut

5/>/

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG 4emembered Iut"uts M Q1 1 Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$ ?&?D$

Ste" /: 3"date out"uts Iut"ut does not c!ange

5/>0

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$

5/>5

Ste" 0: &dd statements it! e*ent to D9M 9nd Delta c)cle / o' 5$: con*ergence

R.Lauwereins Imec 2001

Simulation
entit) Fli"'lo" is "ort 6 &+J: in stdPlogicG M+MA: out stdPlogic8G end entit) Fli"'lo"G arc!itecture Struct o' Fli"Flo" is begin ?&?D$: entit) ?&?D$ "ort ma" 6MA+J+M8G ?&?D1: entit) ?&?D$ "ort ma" 6&+M+MA8G end arc!itecture StructG Drocess 9.ecution Mueue 51 & MA M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

& J M MA 51 5$

Drocess 9.ecution Mueue 5$

Ste" <: &d*ance s)stem time

5/><

R.Lauwereins Imec 2001

Drocess
Sometimes+ t!e combinatorial equation in a single statement becomes *er) com"licated:
& J C D entit) Com"le. is "ort6 &+J+C+D+9+F+E+H+%+[: in stdPlogicG F+R: out stdPlogic8G end entit) Com"le.G arc!itecture Struct o' Com"le. is begin F Q1 66& nand J8 nand 6C nand D88 !en 6S 1 @1A8 else 669 nand F8 nand 6E nand H88G R Q1 % nand [G end arc!itecture StructG 9 F E H % [ S F

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/>;

R.Lauwereins Imec 2001

Drocess

3n'ortunatel)+ in VHDL terminolog) t!e) are also called @StatementsA

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5!ere'ore a "rocess !as been de'ined:


a "rocess acts as a single statement t!at is e.ecuted concurrentl) it! all ot!er statements inside a "rocess+ commands are e.ecuted sequentiall) in t!e order t!e) are listed, 5!is ma(es it eas) to brea( do n a *er) com"licated statement into a list o' smaller commands to "ass data 'rom one command to t!e ot!er+ e ma) declare tem"orar) *ariablesG t!e) do not !a*e necessaril) a "!)sical realiLation a statement+ and !ence also a "rocess+ is sensiti*e to all its in"ut signalsG to 'acilitate 'inding out !at t!e in"ut signals o' a "rocess are+ since t!e) can occur in an) command+ e !a*e to e."licitl) add t!em to a sensiti*it) list, & "rocess is recalculated !en a signal in t!e sensiti*it) list !as an e*ent,

5/>>

R.Lauwereins Imec 2001

Drocess
S)nta. o' "rocess: DrocessPname: "rocess 6sensiti*it)Plist8 is -- *ariable declarationsG begin -- sequential commands end "rocess DrocessPnameG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

S)nta. o' *ariable declaration: *ariable VariablePname: t)"eG

S)nta. o' *ariable assignment: VariablePname :1 e."ressionG #!en assigning to *ariable :1 #!en assigning to signal Q1

5/>=

R.Lauwereins Imec 2001

Drocess
4e rite t!e e.am"le using a "rocess:
entit) Com"le. is "ort6 &+J+C+D+9+F+E+H+%+[: in stdPlogicG F+R: out stdPlogic8G end entit) Com"le.G 51 and 5$ !a*e no "!)sical meaning since eac! re'ers to $ di''erent "!)sical ires 51 5$

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/=:

arc!itecture Struct o' Com"le. is Sensiti*it) list begin FP"rocess: "rocess 6&+J+C+D+9+F+E+H+S8 is *ariable 51+5$: stdPlogicG & begin i' 6S1@1A8 t!en J 51 :1 & nand JG C 5$ :1 C nand DG D else 9 51 :1 9 nand FG 5$ :1 E nand HG F end i'G E F Q1 51 nand 5$G H end "rocess FP"rocessG % R Q1 % nand [G end arc!itecture StructG [

F S

R.Lauwereins Imec 2001

Drocess
Drocesses and delta c)cle con*ergence, #!at is t!e be!a*ior o' 'ollo ing "rocess:
9.am"le: "rocess 6&+J+M8 is begin Ild MHHH M gets F Q1 &G onl) ne *alue M Q1 JG at end o' "rocess R Q1 MG end "rocess 9.am"leG 1, &ssume e*ent at J it! ne *alue JA $, Drocess 9.am"le is e.ecuted once sequentiall), Follo ing out"uts are remembered: FA Q1 &G MA Q1 JAG RA Q1 MG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

/, Drocess 9.am"le sus"ends 6i,e, is e.ecuted once com"letel)8, F+ M and R get t!eir ne *alues FA+ MA+ RA, 0, Since M is in t!e sensiti*it) list+ t!e 9.am"le "rocess is "laced again in t!e Drocess 9.ecution Mueue, 5, Drocess 9.am"le is e.ecuted: FY Q1 &G MY Q1 JAG RY Q1 MAG <, Iut"uts F+ M and R get t!eir ne
5/=1

*alues FY+ MY+ RY,

;, ?o signals o' t!e sensiti*it) list c!anged 1V delta c)cle con*ergence

R.Lauwereins Imec 2001

Drocess
Drocesses and delta c)cle con*ergence, #!at is t!e be!a*ior o' 'ollo ing "rocess:
9.am"le: "rocess 6&+J+C+D8 is begin R Q1 & Z JG R Q1 C Z DG end "rocess 9.am"leG 1, &ssume e*ent at J it! ne *alue JA $, 5!e commands o' Drocess 9.am"le are e.ecuted sequentiall), First 'ollo ing out"ut is remembered: RA Q1 & Z JAG /, ?e.t+ t!e second command is e.ecuted and 'ollo ing out"ut is remembered: RA Q1 C Z D, 5!is o*er rites t!e "re*iousl) remembered RA 0, Drocess 9.am"le sus"ends and !ence signal R is u"dated it! its ne *alue C Z D #!en t!e same t o statements ould !a*e occurred outside a "rocess+ bot! ould dri*e signal R and a resol*er ould be necessar)

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/=$

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/=/

R.Lauwereins Imec 2001

Sequential construction statements


Sequential construction statements are onl) allo ed it!in a "rocessHHH 5!ere are / sequential construction statements: %F+ C&S9+ FI4

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

%F statement: i' condition t!en -- sequential statements else -- sequential statements end i'G

multi"le %F statements: i' condition1 t!en -- sequential statements elsei' condition$ t!en -- sequential statements elsei' condition/ t!en -- sequential statements else -- sequential statements end i'G

5!e 'irst condition !ic! turns out to be 5439 determines !ic! sequential statements are e.ecuted: built-in "riorit)
5/=0

R.Lauwereins Imec 2001

Sequential construction statements


case 9."ression is !en ValueP1 1V -- sequential statements !en ValueP$ 1V -- sequential statements -- etc, end caseG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

4equirements: 1, &ll "ossible *alues s!ould be s"eci'ied $, 5!e *alues s!ould be constant and (no n at design time /, 5!e *alues s!ould !a*e t!e same t)"e as t!e e."ression

9.am"le: "rocess 6&+J+C+-8 is begin case - is !en : to 0 1V R Q1 JG !en 5 1V R Q1 CG !en ; \ = 1V R Q1 &G !en ot!ers 1V R Q1 @:AG end "rocess 9.am"leG

5/=5

R.Lauwereins Imec 2001

Sequential construction statements


'or % in : to / loo" -- sequential statements end loo"G 4emar(s: 1, 5!e loo" *ariable must not be declared $, 5!e s)nt!esis tool ill un'old t!e loo" and create logic 'or eac! iteration o' t!e loo", 5!en+ it ill start minimiLing t!e com"lete circuit

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/=<

R.Lauwereins Imec 2001

Sequential construction statements


entit) EeneralPmu. is generic 6 idt! : integer8G "ort 6 %n"ut : in stdPlogicP*ector 6 idt! - 1 do nto :8G Select : in integer range : to idt! - 1G Iut"ut : out stdPlogic8G end entit) EeneralPmu.G arc!itecture Je!a* o' EeneralPmu. is begin Iut"ut Q1 %n"ut6Select8G end arc!itecture Je!a*G

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

#e indicated t!at t!is is not *alid VHDL: inde. is not (no n at design timeH #e ill re"lace t!is no b) *alid code using t!e loo" construct,

5/=;

R.Lauwereins Imec 2001

Sequential construction statements


entit) EeneralPmu. is generic 6 idt! : integer8G "ort 6 %n"ut : in stdPlogicP*ector 6 idt! - 1 do nto :8G Select : in integer range : to idt! - 1G Iut"ut : out stdPlogic8G end entit) EeneralPmu.G arc!itecture Je!a* o' EeneralPmu. is begin Selector: "rocess 6%n"ut+ Select8 is begin 'or % in : to idt!-1 loo" i' Select1% t!en Iut"ut Q1 %n"ut6%8G end i'G end loo"G end "rocess SelectorG end arc!itecture Je!a*G

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/=>

R.Lauwereins Imec 2001

Variables
& *ariable can onl) be used it!in a "rocess & *ariable is u"dated immediatel)G a signal is stored in t!e signal u"date queue till t!e "rocess sus"ends Variables ma) be assigned to signals and *ice *ersa Variables are used as intermediate *alues to 'acilitate t!e s"eci'ication o' t!e "rocessG !en t!e *alue o' a *ariable needs to be accessible outside t!e "rocess+ it s!ould be assigned to a signal

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/==

R.Lauwereins Imec 2001

Variables
#it! !ic! !ard are sc!ematic does 'ollo ing code corres"ond2 entit) Darit) is generic 6 idt! : integer8G "ort 6&: in stdPlogicP*ector 6: to idt!-18G Idd: out stdPlogic8G 5!is is t!e H# structure end entit) Darit)G as it is gi*en to t!e s)nt!esis tool, 5!e s)nt!esis tool arc!itecture Struct o' Darit) is ill o"timiLe a a) t!e .or begin it! constant @:A in"ut Darit): "rocess6&8 is and ill trans'orm it to *ariable 5em": stdPlogicG a binar) tree o' less de"t! begin 5em" :1 @:AG 'or % in &Alo to &A!ig! loo" : 5em" :1 5em" .or &6%8G 5em" end loo"G &6:8 Idd Q1 5em"G end "rocess Darit)G 5em" end arc!itecture StructG &618 Idd &6$8

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1::

R.Lauwereins Imec 2001

4ising cloc( edge


#it! !ic! 'unction does 'ollo ing code corres"ond2 entit) #!at is "ort 6D+Cl(: in stdPlogicG M: out stdPlogic8G end entit) #!atG arc!itecture 45L o' #!at is begin "rocess 6D+ Cl(8 is begin i' 6Cl(1@1A8 t!en M Q1 DG end i'G end "rocessG end arc!itecture 45LG #it! a latc!+ not

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Since t!ere is no 9LS9 "art t!e "re*ious M *alue !as to be remembered 'or t!e case !ere Cl(1@:A, 5!e s)nt!esis tool ill !ence in'er a latc! instead o' Bust combinatorial logicHHH Je are o' unintended latc!es !en 9LS9 "arts are omitted

it! a D-'li"-'lo"HH

#!en a Cl(-e*ent occurs and Cl( is lo + not!ing !a""ens #!en a Cl(-e*ent occurs and Cl( is !ig!+ t!e D in"ut is co"ied to t!e M out"ut
5/1:1

#!en a D-e*ent occurs and Cl( is !ig!+ t!e D in"ut is co"ied to t!e M out"ut 1V !ence a latc!: !en Cl( is !ig!+ M 'ollo s D

R.Lauwereins Imec 2001

4ising cloc( edge


Ho do e describe a rising cloc( edge2 Met!od 1: #&%5 3?5%L entit) DFli"Flo" is "ort 6D+Cl(: in stdPlogicG M: out stdPlogic8G end entit) DFli"Flo"G arc!itecture 45L o' DFli"Flo" is begin 5!is is not s)nt!esisable "rocess is begin ait until Cl(Ae*ent and Cl(1@1AG M Q1 DG end "rocessG end arc!itecture 45LG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1:$

R.Lauwereins Imec 2001

4ising cloc( edge


Ho do e describe a rising cloc( edge2 Dre'erred met!odH Met!od $: Sensiti*it) list entit) DFli"Flo" is "ort 6D+Cl(: in stdPlogicG M: out stdPlogic8G end entit) DFli"Flo"G arc!itecture 45L o' DFli"Flo" is begin "rocess 6D+Cl(8 is begin i' 6Cl(Ae*ent and Cl(1@1A8 t!en M Q1 DG end i'G end "rocessG end arc!itecture 45LG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1:/

R.Lauwereins Imec 2001

4ising cloc( edge


Ho do e describe combinatorial circuits & J Met!od 1: #&%5 3?5%L entit) 4egisteredCircuit is "ort 6&+J+C+D+Cl(: in stdPlogicG R: out stdPlogic8G end entit) 4egisteredCircuitG arc!itecture 45L o' 4egisteredCircuit is begin "rocess is begin ait until Cl(Ae*ent and Cl(1@1AG -- combinatorial circuit R Q1 6& and J8 or 6C and D8G end "rocessG end arc!itecture 45LG C D R

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

it! registered out"uts2

@#ait untilA !as to be 'irst line o' "rocess+ 'ollo ed b) t!e descri"tion o' t!e combinatorial circuit

5/1:0

R.Lauwereins Imec 2001

4ising cloc( edge


Ho do e describe combinatorial circuits & J Met!od $: Sensiti*it) list entit) 4egisteredCircuit is "ort 6&+J+C+D+Cl(: in stdPlogicG R: out stdPlogic8G end entit) 4egisteredCircuitG C D R

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

it! registered out"uts2

arc!itecture 45L o' 4egisteredCircuit is begin "rocess 6&+J+C+D+Cl(8 is begin i' 6Cl(Ae*ent and Cl(1@1A8 t!en -- combinatorial circuit R Q1 6& and J8 or 6C and D8G end i'G end "rocessG end arc!itecture 45LG

@i' Cl(Ae*entA !as to be 'irst line o' "rocess+ it! t!e descri"tion o' t!e combinatorial circuit in t!e 5H9? "art and it! no 9LS9 "art

5/1:5

R.Lauwereins Imec 2001

4ising cloc( edge


5!e amount o' logic e describe in t!e combinatorial "art+ determines t!e combinatorial dela) %t !ence determines t!e ma.imum cloc( 'requenc) it! !ic! e can cloc( t!e 'li"-'lo" 4e-timing requires re- riting t!e VHDL code

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1:<

R.Lauwereins Imec 2001

4ising cloc( edge


Ho do e describe 'li"-'lo"s it! as)nc!ronous reset2

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

entit) DFli"Flo" is "ort 6D+Cl(+ 4eset: in stdPlogicG M: out stdPlogic8G end entit) DFli"Flo"G arc!itecture 45L o' DFli"Flo" is begin "rocess 6D+ Cl(+ 4eset8 is begin i' 64eset 1 @1A8 t!en M Q1 @:AG elsei' 6Cl(Ae*ent and Cl(1@1A8 t!en M Q1 DG end i'G end "rocessG end arc!itecture 45LG

5/1:;

R.Lauwereins Imec 2001

4ising cloc( edge


Ho do e describe 'li"-'lo"s it! s)nc!ronous reset2 entit) DFli"Flo" is "ort 6D+Cl(+ 4eset: in stdPlogicG M: out stdPlogic8G end entit) DFli"Flo"G arc!itecture 45L o' DFli"Flo" is begin "rocess 6D+ Cl(+ 4eset8 is begin i' 6Cl(Ae*ent and Cl(1@1A8 t!en i' 64eset1@1A8 t!en M Q1 :G else M Q1 DG end i'G end i'G end "rocessG end arc!itecture 45LG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1:>

R.Lauwereins Imec 2001

Finite State Mac!ine


Start1: 4eset #ait ::

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Iut Iut"ut "ut logic CurrentState ?e.t ?e.tState state logic

Start11 3"11 3"1 :1

Start11 3"1: Do n/ 11

State 4eg

3"$ 1:

Do n$ 1:

Start
5/1:=

3"

3"/ 11

Do n1 :1

R.Lauwereins Imec 2001

Finite State Mac!ine


entit) FSM is "ort 6 Start+ 3"+ 4eset+ Cl(: in stdPlogicG Iut"ut: out stdPlogicP*ector6: to 188G end entit) FSMG arc!itecture Je!a* o' FSM is t)"e FSMPStates 1 6#ait+3"1+3"$+ 3"/+Do n1+Do n$+Do n/8G signal CurrentState+ ?e.tState : FSMPStatesG begin Iut"utLogic: "rocess6CurrentState8 is 7 end "rocess Iut"utLogicG ?e.tStateLogic: "rocess6CurrentState+Start+3"8 is 7 end "rocess ?e.tStateLogicG State4egister: "rocess6?e.tState+Cl(+4eset8 is 7 end "rocess State4egisterG end arc!itecture Je!a*G Start11 3"11 3"1 :1 Start1: #ait ::

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Start11 3"1: Do n/ 11

3"$ 1:

Do n$ 1:

3"/ 11

Do n1 :1

5/11:

R.Lauwereins Imec 2001

Finite State Mac!ine


Start1: #ait ::

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Iut"utLogic: "rocess6CurrentState8 is begin case CurrentState is !en #ait 1V Iut"ut Q1 X::YG !en 3"1\Do n1 1V Iut"ut Q1 X:1YG !en 3"$\Do n$ 1V Iut"ut Q1 X1:YG !en 3"/\Do n/ 1V Iut"ut Q1 X11YG end caseG end "rocess Iut"utLogicG

Start11 3"11 3"1 :1

Start11 3"1: Do n/ 11

3"$ 1:

Do n$ 1:

3"/ 11

Do n1 :1

5/111

R.Lauwereins Imec 2001

Finite State Mac!ine


?e.tStateLogic: "rocess6CurrentState+Start+3"8 is begin case CurrentState is !en #ait 1V i' 6Start1@:A8 t!en ?e.tState Q1 #aitG elsei' 63"1@1A8 t!en ?e.tState Q1 3"1G else ?e.tState Q1 Do n/G end i'G !en 3"1 1V ?e.tState Q1 3"$G !en 3"$ 1V ?e.tState Q1 3"/G !en 3"/\Do n1 1V ?e.tState Q1 #aitG !en Do n/ 1V ?e.tState Q1 Do n$G !en Do n$ 1V ?e.tState Q1 Do n1G end caseG end "rocess ?e.tStateLogicG Start1: #ait ::

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Start11 3"11 3"1 :1

Start11 3"1: Do n/ 11

3"$ 1:

Do n$ 1:

3"/ 11

Do n1 :1

5/11$

R.Lauwereins Imec 2001

Finite State Mac!ine


Start1: #ait ::

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Start11 3"11 State4egister: "rocess6?e.tState+Cl(+4eset8 is begin i' 4eset1@1A t!en CurrentState Q1 #aitG elsei' 6Cl(Ae*ent and Cl(1@1A8 t!en CurrentState Q1 ?e.tStateG end i'G end "rocess State4egisterG 3"1 :1

Start11 3"1: Do n/ 11

3"$ 1:

Do n$ 1:

3"/ 11

Do n1 :1

5/11/

R.Lauwereins Imec 2001

Language based H# design: a VHDL "rimer


%ntroduction & 'irst loo( at VHDL Signals and data t)"es VHDL o"erators Concurrent *ersus sequential statements Sequential construction statements Hig!er "er'ormance+ less "ortabilit): e,g, s)nt!esis issues 'or -ilin.

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/110

R.Lauwereins Imec 2001

4esource s!aring
#!at is t!e circuit corres"onding to: i' Sel 1 @1A t!en R Q1 & Z JG else R Q1 & Z CG end i'G Sel 5!is is (ind o' stu"id+ since bot! additions are mutuall) e.clusi*e: it is !ence not necessar) to im"lement $ adders, J Some s)nt!esis tools are ca"able to recogniLe t!is 6o'ten onl) it!in t!e sco"e o' a "rocess8 and trans'orm t!is into t!e s!ared use o' one adder 'or bot! additions, -ilin. Foundation Series "er'orms t!is o"timiLation it!in a !ierarc!ical le*el, Sel & J & C

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

M3R C M3&

Z R

5/115

R.Lauwereins Imec 2001

4esource s!aring
%' t!e s)nt!esis tool does not do t!is o"timiLation automaticall)+ )ou s!ould re- rite )our code: i' Sel 1 @1A t!en - :1 JG else - :1 CG end i'G R Q1 & Z -G J Sel C M3&

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Z R

5!e VHDL coding st)le toget!er it! t!e ca"abilities o' t!e s)nt!esis tool determine t!e circuit t!at is e*entuall) s)nt!esiLed,

5/11<

R.Lauwereins Imec 2001

3sing LogiJLI- in VHDL


LogiJLI- modules lead to !ig!l) e''icient FDE& im"lementations 5!e LogiJLI- module generator creates+ a"art 'rom t!e FDE& im"lementation+ also a be!a*ioral le*el VHDL module 'or simulationH Ho to use LogiJLI- modules in )our VHDL code:
use t!e "ac(age containing t!e LogiJLImodules: librar) M)PLibrar)G use M)PLibrar),M)PDac(age,allG instantiate t!e entit)

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/11;

3sing LogiJLI- ma(es )our VHDL im"lementation more e''icient on -ilin. FDE& but less "ortable to ot!er de*icesHH

R.Lauwereins Imec 2001

9ncoding o' State Mac!ines


5!e de'ault encoding in Foundation 9."ress is one-!ot since t!is matc!es ell it! t!e structure o' a CLJ 6little bit o' combinatorial logic in 'ront o' a D-'li"'lo"8 5!e encoding can be s"eci'ied in t!e VHDL code:
t)"e StateP5)"e is 6S1+ S$+ S/+ S08G attribute 9?3MP9?CID%?E: stringG attribute 9?3MP9?CID%?E o' StateP5)"e: t)"e is X11 1: :1 ::YG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/11>

R.Lauwereins Imec 2001

Sa'e state mac!ines


&ssume a state mac!ine o' t!ree states+ encoded it! $ bits #!at ould !a""en !en t!e state mac!ine enters t!e 0t! state+ due to some error 6noise+ "o er-u"+ 782 #ill it be able to reco*er2 Ma(e "ro*isions 'or t!is situation in )our VHDL code:

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

?e.tStateLogic: "rocess6CurrentState8 is begin case CurrentState is !en %dle 1V ?e.tState Q1 S1G !en S1 1V ?e.tState Q1 S$G !en S$ 1V ?e.tState Q1 %dleG !en ot!ers 1V ?e.tState Q1 %dleG end caseG end "rocess ?e.tStateLogicG

5/11=

R.Lauwereins Imec 2001

Famil) s"eci'ic issues


?ot all 'amilies "ro*ide "er 'li"-'lo" bot! as)nc!ronous set as ell as reset, C!ec( !at )our 'amil) "ro*ides be'ore )ou rite VHDL
Can onl) be im"lemented "rocess 6Cl(+ 4st+ Set8 is e''icientl) !en t!e begin 'amil) !as bot! an i' 4st 1 @1A t!en as)nc!ronous set M Q1 @:AG as ell as reset elsei' Set 1 @1A t!en M Q1 @1AG elsei' Cl(Ae*ent and Cl( 1 @1A t!en -- actions end i'G end "rocessG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1$:

R.Lauwereins Imec 2001

Famil) s"eci'ic issues


&l a)s use LogiJLI- 'or 4&M+ because 4&M ould ot!er ise be created out o' se"arate 'li"-'lo"s

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1$1

R.Lauwereins Imec 2001

%/I bu''er t)"es


Dut all t!e core logic in one entit) %n a !ig!er !ierarc!ical le*el+ instantiate t!e %/I bu''ers as ell as t!e core logic 5!e !ierarc!) !ence becomes
5o" le*el: test benc! instantiating D35 D35: %nstantiation o' core logic and %/I bu''ers Core logic: real design

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1$$

R.Lauwereins Imec 2001

%/I bu''er t)"es


Ho to 'orce a /-state out"ut bu''er: i' 69nable 1 @1A8 t!en IutP"ad Q1 JusPoutG else IutP"ad Q1 @RAG end i'G 9nable JusPout IutP"ad

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

Ho

to 'orce a bidirectional bu''er:

JusPin Q1 JidiP"adG "rocess 69nable+ JusPout8 is begin i' 69nable 1 @1A8 t!en JidiP"ad Q1 JusPoutG else JidiP"ad Q1 @RAG end i'G end "rocessG

9nable JusPout JidiP"ad

JusPin

5/1$/

R.Lauwereins Imec 2001

%/I bu''er t)"es


Ho to 'orce a bidirectional bu''er it! registered out"ut: JusPin Q1 JidiP"adG "rocess 69nable+M8 is begin i' 69nable 1 @1A8 t!en JidiP"ad Q1 MG else JidiP"ad Q1 @RAG end i'G end "rocessG "rocess 6Cl(+ JusPout8 is begin i' Cl(Ae*ent and Cl( 1 @1A t!en M Q1 DG end i'G Cl( end "rocessG JusPout D M

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

9nable JidiP"ad

JusPin
5/1$0

R.Lauwereins Imec 2001

Ho
Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

to 'orce a "ull-u" resistor at an in"ut:

%/I bu''er t)"es


Vcc %nP"ad

entit) Dullu"Pin is "ort 6 %nP"ad: in stdPlogicG CorePin: out stdPlogic8G end entit) Dullu"PinG arc!itecture 45L o' Dullu"Pin is com"onent D3LL3D "ort 6I: out stdPlogic8G end com"onent D3LL3DG

CorePin

com"onent %J3F "ort 6%: in stdPlogicG I: out stdPlogic8G end com"onent %J3FG signal Dumm): stdPlogicG begin Dumm) Q1 %nP"adG D3: com"onent D3LL3D "ort ma" 6Dumm)8G Ju': com"onent %J3F "ort ma" 6Dumm)+CorePin8G end arc!itecture 45LG

5/1$5

R.Lauwereins Imec 2001

3sing t!e Elobal Set 4eset bloc(


entit) IneHot is "ort 6 4st+ Cl(: in stdPlogicG M: out stdPlogicP*ector 6: to /88G end entit) IneHotG arc!itecture Je!a* o' IneHot is com"onent S5&453D "ort 6ES4: out stdPlogic8G end com"onent S5&453DG begin 31: com"onent S5&453D "ort ma" 64st 1V ES48G i' 4st 1 @1A t!en M Q1 X:::1YG elsei' Cl(Ae*ent and Cl( 1 @1A t!en M Q1 M61 to /8 C M6:8G endi'G end arc!itecture 45LG

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1$<

R.Lauwereins Imec 2001

Cloc( ?et or(s


Foundation 9."ress s)nt!esiLes automaticall) cloc( bu''ers C!ec( !et!er )ou do not need more cloc( bu''ers t!an are a*ailable in t!e target 'amil)

Digital design Combinatorial circuits Sequential circuits FSMD design VHDL

5/1$;