CpE 690: Digital System Design

Fall 2013

Lecture 8 Transient Response and Delay

Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030

Adapted from Lecture Notes, David Mahoney Harris CMOS VLSI Design

Activity
1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
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Transient Response
DC analysis tells us Vout if Vin is constant Transient analysis tells us Vout(t) in response to a change in Vin Requires solving differential equations Input is usually considered to be a step or ramp
From GND to VDD or vice versa
delay
VDD GND

Vin

Vout
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Delay Definitions
tpdr : rising propagation delay maximum time from input crossing VDD/2 to rising output crossing VDD/2 tpdf : falling propagation delay maximum time from input crossing VDD/2 to falling output crossing VDD/2 tpd : average propagation delay tpd = (tpdr + tpdf)/2 tr : rise time from output crossing 0.2 VDD to 0.8 VDD tf : fall time from output crossing 0.8 VDD to 0.2 VDD

Delay Definitions (cont.)

tcdf : falling contamination delay minimum time from input crossing VDD/2 to falling output crossing VDD/2 tcdr : rising contamination delay minimum time from input crossing VDD/2 to rising output crossing VDD/2 tcdf tcd : avg. contamination delay tpd = (tcdr + tcdf)/2

tpdf

Delay in CMOS Circuits

Switching CMOS gate generates output current in response to changing input voltages All nodes have some finite capacitance (to ground)
gate capacitance parasitic source/drain (diode) capacitance parasitic wiring capacitance

Transient waveforms found by solving: Cnode (dVnode/dt) = I k,node

k

for each node in circuit

I2,node I1,node I3,node Vnode Cnode

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Inverter Step Response

Find step response of inverter driving Cload

Vin(t) = u(t - t0)VDD Vout(t < t0) = VDD dVout(t) dt = - Idsn(t) Cload
0 for t < t0

Vin(t)

Vout(t) Cload Idsn(t)

Vin(t)

Vout(t) for Vout > VDD Vt t0

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Idsn(t)=

(/2)(VDDVt)2

(VDDVtVout(t)/2)Vout(t) for Vout < VDD - Vt

Simulated Inverter Delay

Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write!
2.0

1.5

1.0 (V)

Vin
0.5

tpdf = 66ps

tpdr = 83ps

Vout

0.0

0.0

200p

400p t(s)

600p

800p

1n

Delay Estimation
We would like to be able to easily estimate delay
For exploration of design space, dont need to be as accurate as simulation Want a technique where its easier to ask What if?

The step response usually looks like a 1st order RC response with a decaying exponential. Can we model conducting transistor as effective resistance?
1.0 Shockley SPICE RC model

(V) A 0.5

0.0 0 20p 40p 60p 80p

Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors Too complicated for much hand analysis

Simplification: treat transistor as resistor

Replace Ids(Vds, Vgs) with effective resistance R Ids = Vds/R or 0 depending on gate voltage

R averaged across switching of digital gate

Too inaccurate to predict current at any given time But good enough to predict gate delay

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RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C

Capacitance (gate & diffusion) proportional to width Resistance inversely proportional to width

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RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width in 0.6 m Gradually decline to 1 fF/m in nanometer techs.

Resistance
R 5-10 Km in 0.6 m process Improves with shorter channel lengths

Unit transistors
May refer to minimum contacted device (4/2 ) Or maybe W=1 m device (doesnt matter as long as you are consistent)
AMI 0.6m Rn (k.m) Rn (k.4) Rp (k.m) Rp (k.4) 9.2 7.7 19.9 16.6 TSMC 250nm 4.0 8.0 8.9 17.8 TSMC 180nm 2.7 7.5 6.5 18.1 IBM 130nm 2.5 9.6 6.4 24.7 IBM 65nm 1.3 10 2.9 22.3
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RC Values
Estimate the delay of a fanout-of-1 inverter

6RC
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Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R).

2 3 3 3

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3-input NAND Capacitors

Annotate the 3-input NAND gate with gate and diffusion capacitance.

2C 2

2C 2C

2C 2

2C 2C

2C 2

2C 2C

3C 3C 3C

3 3 3

3C 3C 3C 3C
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3-input NAND Capacitors

Annotate the 3-input NAND gate with gate and diffusion capacitance.

2 5C 5C 5C

2 3 3 3 9C 3C 3C

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Rise & Fall Delay

What are worst-case rise and fall delays?

2 5C 5C 5C

2 3 3 3 9C 3C 3C

How can we estimate delay of these networks?

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 with multiple RC components

= RC

1 1 + 11 + 1 + 2 . 2 + 21122

Second order response is too complicated

defeats whole purpose of simplifying to an RC network

Can approximate to: = 1 + 2 = R1C1 + (R1+R2).C2

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Elmore Delay
ON transistors modeled as resistors Pullup or pulldown network represented as an RC tree
root of tree is voltage source (often VDD or GND) leaves are capacitors at end of branches

Elmore delay to any target (node j) in the branch: = .

where: i represents all the nodes in the branch Ci is the capacitance at node i Rsij is the resistance of the shared path from the source to and from the source to the target

Elmore delay is conservative

over-estimates the delay

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Shared Path
R1 R2 C1 R3 C2 C3 RN CN

delay to node N is: R1C1 + (R1+R2).C2 + + (R1+R2++Rn).CN delay to node 2 is: R1C1 + (R1+R2).C2 + (R1+R2).(C3+C4++CN)

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Example: Elmore Delay

Calculate delay from source to all nodes in circuit:
F
C 3R

G
2C

2R

E
R C

H
C

3R

2R C

R 2C

B
3R

C
C

D
3C

source

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3-input NAND: pull-down delay

Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates.
A B C

h copies

Worst case pull-down delay occurs when ABC goes from (110) to (111)
= 3
3

= 12 + 5

+ 3C

+ + 9 + 5 ( + + ) 3 3 3 3
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3-input NAND: pull-up delay

Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates.
A B C

h copies

Worst case pull-up delay occurs when ABC goes from (111) to (110)
= 9 + 5 C (R) + 3C R + 3C R
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= 15 + 5

Delay Components
= 12 + 5 Delay has two parts Parasitic delay
15 or 12 RC Independent of load

= 15 + 5

Effort delay
5h RC Proportional to load capacitance

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Contamination Delay
Best-case (contamination) delay can be substantially less than propagation delay:
if top nMOS is last to turn on: if all pMOS turn on simultaneously:

i.e. ABC goes from (011) to (111)

i.e. ABC goes from (111) to (000)

= 9 + 5
compare to: = 12 + 5

= 3 + 5 3
= 15 + 5
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Diffusion Capacitance
We assumed contacted diffusion on every s / d.
but shared on series nMOS chain

Good layout minimizes diffusion area Good NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C

Merged un-contacted diffusion also helps

1.5C 1.5C
1.5C1.5C
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Layout Comparison
Which layout is better?
VDD VDD

GND

GND
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Example: Gate delays

For the gate = + .
a) Draw the schematic b) Size the transistors to give pullup and pulldown strength equal to unit size inverter c) Annotate with effective R of each transistor and C of each node d) Calculate worst case rising & falling propagation delay while driving h similar gates (via input B) e) Calculate best case rising & falling contamination delay while driving h similar gates (via input B)

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